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GET /api/patches/2218124/?format=api
{ "id": 2218124, "url": "http://patchwork.ozlabs.org/api/patches/2218124/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260331131256.3499627-1-daniel.barboza@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331131256.3499627-1-daniel.barboza@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-03-31T13:12:56", "name": "tree-ssa-phiopt.cc: add cond_removal_mispredict_memop [PR124667]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "edf2b27f17d7081b02394eeb391ca5b664691993", "submitter": { "id": 92288, "url": "http://patchwork.ozlabs.org/api/people/92288/?format=api", "name": "Daniel Henrique Barboza", "email": "daniel.barboza@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260331131256.3499627-1-daniel.barboza@oss.qualcomm.com/mbox/", "series": [ { "id": 498196, "url": "http://patchwork.ozlabs.org/api/series/498196/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=498196", "date": "2026-03-31T13:12:56", "name": "tree-ssa-phiopt.cc: add cond_removal_mispredict_memop [PR124667]", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498196/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218124/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218124/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=k71eyvsO;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=FKC7U2Dn;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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basic block 2\n bitshift_6 = 1 << bit_5(D);\n # VUSE <.MEM_7(D)>\n _1 = arrD.4593[n_8(D)];\n _2 = _1 & bitshift_6;\n if (_2 == 0) goto <bb 3>; else goto <bb 4>;\n\n ;; basic block 3\n _3 = _1 | bitshift_6;\n # .MEM_9 = VDEF <.MEM_7(D)>\n arrD.4593[n_8(D)] = _3;\n ;; succ: 4 [always] (FALLTHRU,EXECUTABLE)\n\n ;; basic block 4,\n ;; prev block 3\n # .MEM_4 = PHI <.MEM_7(D)(2), .MEM_9(3)>\n # VUSE <.MEM_4>\n _10 = arrD.4593[n_8(D)];\n # .MEM_11 = VDEF <.MEM_4>\n arrD.4593 ={v} {CLOBBER(eos)};\n # VUSE <.MEM_11>\n return _10;\n\nIf we have the right conditions (e.g. we don't have store data races to\nworry about, we're not dealing with read-only memory) we can move the\nbitset operation to the cond_bb (block 2 in the example), removing the\npotential branch mispredict, as long as we're able to identify this \"bit\nN is either already set or will end up being set\" scenario:\n\n bitshift_6 = 1 << bit_5(D);\n # VUSE <.MEM_7(D)>\n _1 = arrD.4593[n_8(D)];\n _2 = _1 & bitshift_6;\n _3 = _1 | bitshift_6;\n # .MEM_9 = VDEF <.MEM_7(D)>\n arrD.4593[n_8(D)] = _3;\n if (_2 == 0) goto <bb 3>; else goto <bb 4>;\n\n ;; basic block 3\n ;; succ: 4 [always] (FALLTHRU,EXECUTABLE)\n (...)\n\nIf the bitcheck result isn't being used as a PHI result there's a good\nchance that this optimization will get rid of both the bitcheck and the\ngcond. The 'optimized' dump for the example above looks like this:\n\n ;; basic block 2\n ;; prev block 0\n bitshift_6 = 1 << bit_5(D);\n # VUSE <.MEM_7(D)>\n _1 = arrD.4593[n_8(D)];\n _3 = _1 | bitshift_6;\n # .MEM_11 = VDEF <.MEM_7(D)>\n arrD.4593 ={v} {CLOBBER(eos)};\n # VUSE <.MEM_11>\n return _3;\n\nThis optimization was motivated by GCC's bitmap_set_bit() before\nPR119482. We're also covering the bitclear equivalent of this opt\n(check if a bit is set, if positive clear it). The bitset\ntransformation only works for single bits. The bitclear variation\ncan handle single or multiple bit masks.\n\nBootstrapped and regression tested in x86, aarch64 and RISC-V.\n\n\tPR tree-optimization/124667\n\ngcc/ChangeLog:\n\n\t* tree-ssa-phiopt.cc (stmt_is_memory_load_assignment): helper to\n\tcheck if a gimple stmt is a memory load.\n\t(stmt_is_memory_store_assignment): helper to check if a gimple\n\tstmt is a memory store.\n\t(cond_removal_mispredict_validate_memregs): helper to check if a\n\tmemory load and a memory store are using the same memory address.\n\t(cond_removal_mispredict_valid_bitmask): helper to validate if\n\tthe bit/bitmask is valid for the current optimization.\n\t(cond_removal_mispredict_check_cond): helper to validate the\n\tgcond and cond_stmt format.\n\t(cond_removal_mispredict_memop): new cselim optimization that,\n\tafter doing checks and validations, move a bitset/bitclear\n\toperation to the end of cond_bb, making it unconditional.\n\t(pass_cselim::execute): call cond_removal_mispredict_memop.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/tree-ssa/pr124667.c: New test.\n---\n gcc/testsuite/gcc.dg/tree-ssa/pr124667.c | 77 ++++\n gcc/tree-ssa-phiopt.cc | 443 ++++++++++++++++++++++-\n 2 files changed, 515 insertions(+), 5 deletions(-)\n create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr124667.c", "diff": "diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr124667.c b/gcc/testsuite/gcc.dg/tree-ssa/pr124667.c\nnew file mode 100644\nindex 00000000000..1074169ac20\n--- /dev/null\n+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr124667.c\n@@ -0,0 +1,77 @@\n+/* { dg-additional-options -O2 } */\n+/* { dg-additional-options -fdump-tree-cselim } */\n+\n+int bitset1 (int n, int bit)\n+{\n+ int arr[16];\n+\n+ int bitshift = 1 << bit;\n+\n+ if ((arr[n] & bitshift) == 0)\n+ arr[n] |= bitshift;\n+\n+ return arr[n];\n+}\n+\n+int bitset2 (int n)\n+{\n+ int arr[16];\n+\n+ int bit = 0x4;\n+\n+ if ((arr[n] & bit) == 0)\n+ arr[n] |= bit;\n+\n+ return arr[n];\n+}\n+\n+int bitset3 (int n)\n+{\n+ int arr[16];\n+\n+ int bits = 0xF;\n+\n+ if ((arr[n] & bits) == 0)\n+ arr[n] |= bits;\n+\n+ return arr[n];\n+}\n+\n+int bitclear1 (int n, int bit)\n+{\n+ int arr[16];\n+\n+ int bitshift = 1 << bit;\n+\n+ if ((arr[n] & bitshift) != 0)\n+ arr[n] &= ~bitshift;\n+\n+ return arr[n];\n+}\n+\n+int bitclear2 (int n)\n+{\n+ int arr[16];\n+\n+ int bit = 0x4;\n+\n+ if ((arr[n] & bit) != 0)\n+ arr[n] &= ~bit;\n+\n+ return arr[n];\n+}\n+\n+int bitclear3 (int n)\n+{\n+ int arr[16];\n+\n+ int bits = 0xF;\n+\n+ if ((arr[n] & bits) != 0)\n+ arr[n] &= ~bits;\n+\n+ return arr[n];\n+}\n+\n+/* bitset3 won't be optimized all willl kept its branch. */\n+/* { dg-final { scan-tree-dump-times \"goto\" 2 cselim } } */\ndiff --git a/gcc/tree-ssa-phiopt.cc b/gcc/tree-ssa-phiopt.cc\nindex 0bf7e58b8f0..32b577ae4cf 100644\n--- a/gcc/tree-ssa-phiopt.cc\n+++ b/gcc/tree-ssa-phiopt.cc\n@@ -3115,6 +3115,436 @@ cond_store_replacement (basic_block middle_bb, basic_block join_bb,\n return true;\n }\n \n+/* Return TRUE if STMT is a memory load, FALSE otherwise. */\n+\n+static bool\n+stmt_is_memory_load_assignment (gimple *stmt)\n+{\n+ if (!stmt\n+ || !gimple_assign_single_p (stmt)\n+ || gimple_has_volatile_ops (stmt)\n+ || !gimple_references_memory_p (stmt))\n+ return false;\n+\n+ tree rhs1 = gimple_assign_rhs1 (stmt);\n+ if ((!REFERENCE_CLASS_P (rhs1)\n+ && !DECL_P (rhs1))\n+ || !is_gimple_reg_type (TREE_TYPE (rhs1)))\n+ return false;\n+\n+ return true;\n+}\n+\n+/* Return TRUE if STMT is a memory store, FALSE otherwise. */\n+\n+static bool\n+stmt_is_memory_store_assignment (gimple *stmt)\n+{\n+ /* Check if middle_bb contains of only one store. */\n+ if (!stmt\n+ || !gimple_assign_single_p (stmt)\n+ || gimple_has_volatile_ops (stmt)\n+ || !gimple_references_memory_p (stmt))\n+ return false;\n+\n+ tree lhs = gimple_assign_lhs (stmt);\n+ if ((!REFERENCE_CLASS_P (lhs)\n+ && !DECL_P (lhs))\n+ || !is_gimple_reg_type (TREE_TYPE (lhs)))\n+ return false;\n+\n+ return true;\n+}\n+\n+/* cond_removal_mispredict_memop helper that checks if a\n+ given memreg operand of a bitop_stmt is a memory load,\n+ and it loads the same mem addr that is later stored\n+ in store_stmt:\n+\n+ # VUSE <.MEM_11>\n+ _1 = ptr_10->bits[word_num_12]; (load_stmt)\n+ (...)\n+ _3 = _1 OP bitmask;\t\t (bitop_stmt)\n+ # .MEM_14 = VDEF <.MEM_11>\n+ ptr_10->bits[word_num_12] = _3; (store_stmt)\n+\n+ For the case above \"_1\" matches the criteria.\n+\n+ We're also validating whether store_stmt supports the\n+ transformation by testing its LHS for read-only memory\n+ and store data races. */\n+\n+static bool\n+cond_removal_mispredict_validate_memregs (gimple *store_stmt,\n+\t\t\t\t\t tree memreg)\n+{\n+ gimple *load_stmt = SSA_NAME_DEF_STMT (memreg);\n+ tree vuse = gimple_vuse (load_stmt);\n+\n+ if (!vuse || TREE_CODE (vuse) != SSA_NAME)\n+ return false;\n+\n+ vuse = SSA_NAME_VAR (vuse);\n+ tree vdef = gimple_vdef (store_stmt);\n+ if (!vdef || TREE_CODE (vdef) != SSA_NAME)\n+ return false;\n+\n+ vdef = SSA_NAME_VAR (vdef);\n+ if (vuse != vdef)\n+ return false;\n+\n+ tree lhs = gimple_assign_lhs (store_stmt);\n+ if (ref_can_have_store_data_races (lhs) && !flag_store_data_races)\n+ return false;\n+\n+ tree base = get_base_address (lhs);\n+ if (DECL_P (base) && TREE_READONLY (base))\n+ return false;\n+\n+ return true;\n+}\n+\n+/* Check if a given node represents a valid bitmask for\n+ the cond_removal_mispredict_memop transformation:\n+ single bit mask for unconditional bit set, multiple\n+ bits mask for unconditional bit clear. */\n+\n+static bool\n+cond_removal_mispredict_valid_bitmask (tree bitmask, bool only_single_bit)\n+{\n+ if (TREE_CODE (bitmask) == INTEGER_CST)\n+ {\n+ if (!only_single_bit)\n+\treturn true;\n+ return wi::popcount (wi::to_wide (bitmask)) == 1;\n+ }\n+\n+ /* There are several ops that can generate any bitmask, but in this\n+ case we want to detect \"SSA_NAME = 1 << X\" that represents a\n+ single bit mask. */\n+ if (TREE_CODE (bitmask) == SSA_NAME)\n+ {\n+ gimple *def_stmt = SSA_NAME_DEF_STMT (bitmask);\n+ return def_stmt\n+\t && gimple_assign_rhs_code (def_stmt) == LSHIFT_EXPR\n+\t && integer_onep (gimple_assign_rhs1 (def_stmt));\n+ }\n+ return false;\n+}\n+\n+/* cond_removal_mispredict helper that checks if the 'cond'\n+ stamement is on the expected format for the possible\n+ transformation we can have:\n+ - a \"bitcheck EQ 0\" comparison that follows a bitset\n+ - a \"bitcheck NE 0\" comparison that follows a bitclear\n+\n+ This also includes checking if the bitmasks involved are\n+ compatible with each other. E.g. if we're checking for\n+ bit N and then clearing a bit other than N, we can't do\n+ the transformation. */\n+\n+static bool\n+cond_removal_mispredict_check_cond (gcond *cond, tree_code bitop_code,\n+\t\t\t\t tree memreg, tree bitop_bitmask,\n+\t\t\t\t bool has_not_stmt)\n+{\n+ /* First check if the conditional has the following format:\n+\n+ # VUSE <.MEM_11>\n+ _1 = ptr_10->bits[word_num_12];\n+ _2 = _1 & bitmask;\n+ if (_2 ==/!= 0)\n+ goto <bb 4>; [50.00%]\n+ else\n+ goto <bb 5>; [50.00%]\n+\n+ I.e. there is a check for an absent bitmask (_2 == 0) that follows\n+ a bit set or a check for an existing bitmask (_2 != 0) that follows\n+ a bit clear. */\n+ if (TREE_CODE (gimple_cond_lhs (cond)) != SSA_NAME)\n+ return false;\n+\n+ if (!integer_zerop (gimple_cond_rhs (cond)))\n+ return false;\n+\n+ gimple *cond_stmt = SSA_NAME_DEF_STMT (gimple_cond_lhs (cond));\n+ tree_code cond_code = gimple_cond_code (cond);\n+\n+ if (cond_code != EQ_EXPR && cond_code != NE_EXPR)\n+ return false;\n+\n+ if (gimple_cond_code (cond) == EQ_EXPR && bitop_code != BIT_IOR_EXPR)\n+ return false;\n+ else if (gimple_cond_code (cond) == NE_EXPR && bitop_code != BIT_AND_EXPR)\n+ return false;\n+\n+ tree cond_rhs1 = gimple_assign_rhs1 (cond_stmt);\n+ tree cond_rhs2 = gimple_assign_rhs2 (cond_stmt);\n+ tree cond_bitmask = NULL_TREE;\n+\n+ /* cond_stmt must use the same memreg as bitop_stmt. */\n+ if (cond_rhs1 == memreg)\n+ cond_bitmask = cond_rhs2;\n+ else if (cond_rhs2 == memreg)\n+ cond_bitmask = cond_rhs1;\n+ else\n+ return false;\n+\n+ /* If \"bitop_stmt == bit_ior\" 'bitmask' must also match.\n+\n+ (cond_bb)\n+ _1 = ptr_10->bits[word_num_12];\n+ _2 = _1 & bit_val_9; <====== cond_stmt\n+\n+ (middle_bb)\n+ _3 = _1 | bit_val_9; <====== bit_ior\n+ # .MEM_14 = VDEF <.MEM_11>\n+ ptr_10->bits[word_num_12] = _3;\n+\n+ Same thing for bit_and with a 'not':\n+\n+ (cond_bb)\n+ _1 = ptr_10->bits[word_num_12];\n+ _2 = _1 & bit_val_9; <==== cond_stmt\n+\n+ (middle_bb)\n+ _3 = ~bit_val_9; <==== not_stmt\n+ _4 = _1 & _3; <==== bit_and\n+ # .MEM_14 = VDEF <.MEM_11>\n+ ptr_10->bits[word_num_12] = _4; */\n+ if (bitop_code == BIT_IOR_EXPR || has_not_stmt)\n+ return cond_bitmask == bitop_bitmask;\n+\n+ /* Finally, for \"bitop_stmt == bit_and\" with an INTEGER_CST\n+ bitop_bitmask, check if we're clearing exactly what we're\n+ checking in cond_bitmask:\n+\n+ (cond_bb)\n+ # VUSE <.MEM_11>\n+ _1 = ptr_10->bits[word_num_12];\n+ _2 = _1 & 15; <==== cond_stmt\n+ if (_2 ==/!= 0)\n+\n+ (middle_bb)\n+ _4 = _1 & 18446744073709551600; <==== ~15\n+ # .MEM_11 = VDEF <.MEM_8>\n+ ptr_10->bits[word_num_12] = _4; */\n+ if (TREE_CODE (bitop_bitmask) == INTEGER_CST\n+ && TREE_CODE (cond_bitmask) == INTEGER_CST\n+ && wi::to_wide (bitop_bitmask) == ~wi::to_wide (cond_bitmask))\n+ return true;\n+\n+ return false;\n+}\n+\n+\n+/* This transformation aims to optimize cases where conditional\n+ bit clear and bit set operations can be made unconditional\n+ if the end result in memory is the same. A conditional\n+ bitset that can be optimized would be:\n+\n+ ;; bb 2\n+ bitshift_6 = 1 << bit_5;\n+ # VUSE <.MEM_7>\n+ _1 = arrD.4593[n_8]; (load_stmt)\n+ _2 = _1 & bitshift_6; (cond_stmt)\n+ if (_2 == 0) goto <bb 3>; else goto <bb 4>;\n+\n+ ;; bb 3\n+ _3 = _1 | bitshift_6; (bitop_stmt)\n+ # .MEM_9 = VDEF <.MEM_7>\n+ arrD.4593[n_8] = _3; (store_stmt)\n+ ;; succ: 4 (FALLTHRU,EXECUTABLE)\n+\n+ As far as the memory pointed by MEM_7 goes the end result at the\n+ start of bb4 is \"bitshift_6 is set\", either because it was already\n+ set before or because it is set it in bb3.\n+\n+ In this case, depending on constraints like store data races and\n+ read only memory, we want to move the stms from bb3 to the end of\n+ bb2, i.e. always do the bitset:\n+\n+ ;; bb 2\n+ bitshift_6 = 1 << bit_5;\n+ # VUSE <.MEM_7>\n+ _1 = arrD.4593[n_8]; (load_stmt)\n+ _2 = _1 & bitshift_6; (cond_stmt)\n+ _3 = _1 | bitshift_6; (bitop_stmt)\n+ # .MEM_9 = VDEF <.MEM_7>\n+ arrD.4593[n_8] = _3; (store_stmt)\n+ if (_2 == 0) goto <bb 3>; else goto <bb 4>;\n+\n+ This will not just remove the gcond but it can also get rid of\n+ 'cond_stmt' in case it's not used anywhere else. */\n+\n+static bool\n+cond_removal_mispredict_memop (basic_block cond_bb,\n+\t\t\t basic_block middle_bb,\n+\t\t\t basic_block join_bb)\n+{\n+ /* 'middle_bb' must have no PHI nodes, it must come via a\n+ TRUE_VALUE edge, and it must have a store preceeding\n+ a bitop:\n+\n+ _3 = _1 BITOP bitmask;\n+ # .MEM_14 = VDEF <.MEM_11>\n+ ptr_10->bits[word_num_12] = _3; */\n+ if (!gimple_seq_empty_p (phi_nodes (middle_bb)))\n+ return false;\n+\n+ edge e_cond_middle = single_pred_edge (middle_bb);\n+ if (!(e_cond_middle->flags & EDGE_TRUE_VALUE))\n+ return false;\n+\n+ gimple_stmt_iterator gsi = gsi_last_nondebug_bb (middle_bb);\n+ gimple *store_stmt = gsi_stmt (gsi);\n+ if (!store_stmt)\n+ return false;\n+\n+ if (!stmt_is_memory_store_assignment (store_stmt))\n+ return false;\n+\n+ gsi = gsi_start_nondebug_after_labels_bb (middle_bb);\n+ gimple *bitop_stmt = gsi_stmt (gsi);\n+\n+ if (!is_gimple_assign (bitop_stmt))\n+ return false;\n+\n+ tree_code bitop_code = gimple_assign_rhs_code (bitop_stmt);\n+ gimple *not_stmt = NULL;\n+\n+ if (bitop_code != BIT_IOR_EXPR && bitop_code != BIT_AND_EXPR)\n+ {\n+ /* For a bit clear case we can also expect a pattern like this:\n+\t if (_2 != 0)\n+\t goto <bb 4>; [50.00%]\n+\t else\n+\t goto <bb 5>; [50.00%]\n+\n+\t ;; basic block 4,\n+\t _3 = ~bit_val_9;\n+\t _4 = _1 & _3;\n+\t # .MEM_14 = VDEF <.MEM_11>\n+\t ptr_10->bitsD.4594[word_num_12] = _4; */\n+ if (bitop_code != BIT_NOT_EXPR)\n+\treturn false;\n+\n+ not_stmt = bitop_stmt;\n+ gsi_next (&gsi);\n+ bitop_stmt = gsi_stmt (gsi);\n+\n+ if (!is_gimple_assign (bitop_stmt))\n+\treturn false;\n+\n+ bitop_code = gimple_assign_rhs_code (bitop_stmt);\n+ if (bitop_code != BIT_AND_EXPR)\n+\treturn false;\n+ }\n+\n+ /* Verify that after bitop_stmt we only have store_stmt. */\n+ gsi_next (&gsi);\n+ if (gsi_stmt (gsi) != store_stmt)\n+ return false;\n+\n+ /* Check if the register being stored by 'store_stmt'\n+ is the result of the previous bitop_stmt. */\n+ tree store_rhs1 = gimple_assign_rhs1 (store_stmt);\n+ if (TREE_CODE (store_rhs1) != SSA_NAME\n+ || SSA_NAME_DEF_STMT (store_rhs1) != bitop_stmt)\n+ return false;\n+\n+ /* One of the BITOP operands must be a memory load. Assume for\n+ now that the other operand will be a valid bitmask. */\n+ tree memreg = NULL_TREE, bitmask = NULL_TREE;\n+\n+ if (TREE_CODE (gimple_assign_rhs1 (bitop_stmt)) == SSA_NAME\n+ && stmt_is_memory_load_assignment (\n+\t\tSSA_NAME_DEF_STMT (gimple_assign_rhs1 (bitop_stmt))))\n+ {\n+ memreg = gimple_assign_rhs1 (bitop_stmt);\n+ bitmask = gimple_assign_rhs2 (bitop_stmt);\n+ }\n+ else if (TREE_CODE (gimple_assign_rhs2 (bitop_stmt)) == SSA_NAME\n+\t && stmt_is_memory_load_assignment (\n+\t\tSSA_NAME_DEF_STMT (gimple_assign_rhs2 (bitop_stmt))))\n+ {\n+ memreg = gimple_assign_rhs2 (bitop_stmt);\n+ bitmask = gimple_assign_rhs1 (bitop_stmt);\n+ }\n+\n+ if (!memreg)\n+ return false;\n+\n+ /* For the conditional bitclear case with a not_stmt,\n+ 'bitmask' would be pointing to the LHS of not_stmt,\n+ and the actual bitmask we want to verify is its RHS1. */\n+ if (not_stmt)\n+ {\n+ if (gimple_assign_lhs (not_stmt) == bitmask)\n+\tbitmask = gimple_assign_rhs1 (not_stmt);\n+ else\n+\treturn false;\n+ }\n+\n+ /* Validate 'bitmask' before proceeding. Only single bit masks\n+ are supported for the bit_ior pattern. */\n+ if (!cond_removal_mispredict_valid_bitmask (bitmask,\n+\t\t\t\t\t bitop_code == BIT_IOR_EXPR))\n+ return false;\n+\n+ /* Validate store_stmt LHS and memreg. */\n+ if (!cond_removal_mispredict_validate_memregs (store_stmt, memreg))\n+ return false;\n+\n+ gcond *cond = safe_dyn_cast <gcond *> (*gsi_last_bb (cond_bb));\n+ if (!cond)\n+ return false;\n+\n+ if (!cond_removal_mispredict_check_cond (cond, bitop_code,\n+\t\t\t\t\t memreg, bitmask,\n+\t\t\t\t\t not_stmt != NULL))\n+ return false;\n+\n+ /* At this point we're certain we can always execute\n+ the store. We could make more analysis to determine\n+ if the gcond result is being used as a PHI result,\n+ or we can just move things to cond_bb, right before\n+ the gcond, and trust that cfg_cleanup will do\n+ the right thing. */\n+ gimple_stmt_iterator gsi_from;\n+ gsi = gsi_for_stmt (cond);\n+\n+ if (not_stmt)\n+ {\n+ gsi_from = gsi_for_stmt (not_stmt);\n+ gsi_move_before (&gsi_from, &gsi);\n+ update_stmt (not_stmt);\n+ }\n+\n+ gsi_from = gsi_for_stmt (bitop_stmt);\n+ gsi_move_before (&gsi_from, &gsi);\n+ update_stmt (bitop_stmt);\n+\n+ gsi_from = gsi_for_stmt (store_stmt);\n+ gsi_move_before (&gsi_from, &gsi);\n+ update_stmt (store_stmt);\n+\n+ gphi *vphi = get_virtual_phi (join_bb);\n+ edge e_cond_join = find_edge (cond_bb, join_bb);\n+ SET_PHI_ARG_DEF (vphi, e_cond_join->dest_idx, gimple_vdef (store_stmt));\n+ update_stmt (vphi);\n+\n+ if (dump_file && (dump_flags & TDF_DETAILS))\n+ {\n+ fprintf (dump_file, \"\\n Conditional store turned unconditional.\");\n+ print_gimple_stmt (dump_file, store_stmt, 0, TDF_VOPS|TDF_MEMSYMS);\n+ }\n+ statistics_counter_event (cfun,\n+\t\t\t \"conditional store turned unconditional\", 1);\n+\n+ return true;\n+}\n+\n /* Do the main work of conditional store replacement. */\n \n static bool\n@@ -4255,11 +4685,14 @@ pass_cselim::execute (function *)\n \treturn;\n \n /* bb1 is the middle block, bb2 the join block, bb the split block,\n-\t e1 the fallthrough edge from bb1 to bb2. We can't do the\n-\t optimization if the join block has more than two predecessors. */\n- if (EDGE_COUNT (bb2->preds) > 2)\n-\treturn;\n- if (cond_store_replacement (bb1, bb2, e1, e2, nontrap))\n+\t e1 the fallthrough edge from bb1 to bb2. */\n+\n+ /* We can't do cond_store_replacement if the join block has more\n+\t than two predecessors. */\n+ if (EDGE_COUNT (bb2->preds) <= 2\n+\t && cond_store_replacement (bb1, bb2, e1, e2, nontrap))\n+\tcfgchanged = true;\n+ else if (cond_removal_mispredict_memop (bb, bb1, bb2))\n \tcfgchanged = true;\n };\n \n", "prefixes": [] }