Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2218108/?format=api
{ "id": 2218108, "url": "http://patchwork.ozlabs.org/api/patches/2218108/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-i2c/patch/20260331114742.2896317-5-mukesh.savaliya@oss.qualcomm.com/", "project": { "id": 35, "url": "http://patchwork.ozlabs.org/api/projects/35/?format=api", "name": "Linux I2C development", "link_name": "linux-i2c", "list_id": "linux-i2c.vger.kernel.org", "list_email": "linux-i2c@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331114742.2896317-5-mukesh.savaliya@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-03-31T11:47:42", "name": "[v6,4/4] i2c: qcom-geni: Support multi-owner controllers in GPI mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "eb558163ded150e9914a742905173f21aea71ae1", "submitter": { "id": 91179, "url": "http://patchwork.ozlabs.org/api/people/91179/?format=api", "name": "Mukesh Kumar Savaliya", "email": "mukesh.savaliya@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-i2c/patch/20260331114742.2896317-5-mukesh.savaliya@oss.qualcomm.com/mbox/", "series": [ { "id": 498183, "url": "http://patchwork.ozlabs.org/api/series/498183/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-i2c/list/?series=498183", "date": "2026-03-31T11:47:38", "name": "Enable multi-owner I2C support for QCOM GENI controllers", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498183/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218108/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218108/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-i2c+bounces-16897-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-i2c@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=oeeQeodj;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; helo=sin.lore.kernel.org;\n envelope-from=linux-i2c+bounces-16897-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"oeeQeodj\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=205.220.168.131", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=qualcomm.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4flRLx57wfz1y1q\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 31 Mar 2026 22:52:41 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id 9EFA2301F6BC\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 31 Mar 2026 11:49:06 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 1ED393E1D03;\n\tTue, 31 Mar 2026 11:48:46 +0000 (UTC)", "from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 6653B3822B5;\n\tTue, 31 Mar 2026 11:48:44 +0000 (UTC)", "from pps.filterd (m0279866.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 62VBk1ce2391342;\n\tTue, 31 Mar 2026 11:48:40 GMT", "from apblrppmta02.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d7ue7mc9b-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tTue, 31 Mar 2026 11:48:39 +0000 (GMT)", "from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1])\n\tby APBLRPPMTA02.qualcomm.com (8.18.1.7/8.18.1.7) with ESMTP id\n 62VBmaMY011366;\n\tTue, 31 Mar 2026 11:48:36 GMT", "from pps.reinject (localhost [127.0.0.1])\n\tby APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 4d6qk1ven0-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tTue, 31 Mar 2026 11:48:36 +0000 (GMT)", "from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com\n [127.0.0.1])\n\tby pps.reinject (8.18.1.12/8.18.1.12) with ESMTP id 62VBmaZT011361;\n\tTue, 31 Mar 2026 11:48:36 GMT", "from hu-maiyas-hyd.qualcomm.com (hu-msavaliy-hyd.qualcomm.com\n [10.213.110.207])\n\tby APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 62VBmZqh011359\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tTue, 31 Mar 2026 11:48:36 +0000 (GMT)", "by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 429934)\n\tid 387792579A; Tue, 31 Mar 2026 17:18:35 +0530 (+0530)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774957725; cv=none;\n b=HPigsCHRndjcR5fCC9krGCKvpxF7m3avlJIcgITPkpUqK/ZNg4Rorh+E2vEYkg0XOSP3a6X3VygYFGSMUlgXwK3Wq561ni+1qNwZDaNvXNvMuU7LLJ8p1KarXQKmTk2nashmpIX4e9MC+JjtHMSaLWXC88jQwLUCuXe6YE5Ho/Y=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774957725; c=relaxed/simple;\n\tbh=OrTPCLFoy/lXjg+kOZqJZMWotZiwF1YBFeK6SAao5D0=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t MIME-Version;\n b=kfQA3D/ZO8t2Du6Ii/QoPFuR1qlznRpjLAtPNDmB+jv8DjzhgVoCbDtycNEFVfolRZHi8i5eDL1dBaGQGk+bVb4myy8ySsV58fJYX+RS07WnpIBlnLHecQZ7fMLh9LFODfoE2qy0iObrHVJRgt8qxg98d/F6su1+IF7pehQ8xVo=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com;\n spf=pass smtp.mailfrom=qualcomm.com;\n dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=oeeQeodj; arc=none smtp.client-ip=205.220.168.131", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n\tcc:content-transfer-encoding:date:from:in-reply-to:message-id\n\t:mime-version:references:subject:to; s=qcppdkim1; bh=FJDNGZLM93w\n\tQFe5ymtZ0GbdfY8lxJ4Mzqty5jJep6hw=; b=oeeQeodjHaLJIHQeXRJRdQbp/W5\n\tcCK9A2pRkyrMQw4MestTJdMRZhdnuPpw+Cr438RyFbOaogXmDjlfeHEx4fjjcFVI\n\t7Lw11qgHL9KSX/5q5Y7FLCSJ6RRocoWvScIzAybrcGf7HXDbLLEy8fxM+GpZYa9g\n\t8O1RyZrjSXzkku46x9p3Q7ogJc6Js1uasCr1UO53G0DUCVKgN7IhldkfOJJg9qI8\n\tK3c69kMAIbbqO1GPCiyyLOF+s0DSOsEL1o7recktiLQoi0q9mLa3XdW2EYc7OaO4\n\tSZlB5qUAsH8WXnkRrQPr+1EM2Tcx9FGJCiRrJSZgjWaI8L1lSYaVtBLxF+A==", "From": "Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>", "To": "viken.dadhaniya@oss.qualcomm.com, andi.shyti@kernel.org, robh@kernel.org,\n krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org,\n Frank.Li@kernel.org, andersson@kernel.org, konradybcio@kernel.org,\n dmitry.baryshkov@oss.qualcomm.com, linmq006@gmail.com,\n quic_jseerapu@quicinc.com, agross@kernel.org,\n linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n dmaengine@vger.kernel.org", "Cc": "krzysztof.kozlowski@oss.qualcomm.com,\n bartosz.golaszewski@oss.qualcomm.com,\n bjorn.andersson@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com,\n Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>", "Subject": "[PATCH v6 4/4] i2c: qcom-geni: Support multi-owner controllers in GPI\n mode", "Date": "Tue, 31 Mar 2026 17:17:42 +0530", "Message-Id": "<20260331114742.2896317-5-mukesh.savaliya@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260331114742.2896317-1-mukesh.savaliya@oss.qualcomm.com>", "References": "<20260331114742.2896317-1-mukesh.savaliya@oss.qualcomm.com>", "Precedence": "bulk", "X-Mailing-List": "linux-i2c@vger.kernel.org", "List-Id": "<linux-i2c.vger.kernel.org>", "List-Subscribe": "<mailto:linux-i2c+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-i2c+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QCInternal": [ "smtphost", "smtphost" ], "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMzMxMDExNCBTYWx0ZWRfX4EIMPCC6+G3F\n kaPnwIABJWb7zWX2OeVj9elD2aGSc4+espdoQMsLQnF+svLGcV8jvoJ5OpkO9I5fnvTtZSLq9KT\n xOLdyuV/Om4GMZjWf1uOnQJzoYlvFHqURQfLPDIaypBdQeslexEd8f9j+bTF7+2DyT7swPDxmzH\n OF6oTTD7eIAo41HLT3Iab2C4/fM0u9m12JYp2RXizqJodWf8n80ttVd0q/V2Zu1tmoEVlg6NWJc\n aksIIZggqc5EFSfnB7alWfc/3uNwHmW/GePh/6n2bJhF4s6yWep1CjTw3QPLEFQhzW+eSnqS2y6\n Lee+3FuWASkQyW+as/oh0or2FD3dxuKtWF8UjGEtvcTyVLcrTa5zT4Wd//UAwefCwmjvtgQ7yEr\n xAViIg7/58FhCEhwQCozM0uHGlfW217zo6o81WhMFYk0Zza83auWQJwNKIqoOn+PXz6pSaUYJPI\n 9v5ZeBZx/ekAV39CE0A==", "X-Proofpoint-GUID": "Za3FSEG0VLwaC8DqKNHp_YFTAWkpSgaS", "X-Authority-Analysis": "v=2.4 cv=G7sR0tk5 c=1 sm=1 tr=0 ts=69cbb498 cx=c_pps\n a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22\n a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=r5MnBgDnrAiVjouRZIUA:9", "X-Proofpoint-ORIG-GUID": "Za3FSEG0VLwaC8DqKNHp_YFTAWkpSgaS", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-03-31_02,2026-03-31_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n clxscore=1015 phishscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0\n priorityscore=1501 spamscore=0 adultscore=0 impostorscore=0 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603310114" }, "content": "Some platforms use a QUP-based I2C controller in a configuration where the\ncontroller is shared with another system processor. In this setup the\noperating system must not assume exclusive ownership of the controller or\nits associated pins.\n\nAdd support for enabling multi-owner operation when DeviceTree specifies\nqcom,qup-multi-owner. When enabled, mark the underlying serial engine as\nshared so the common GENI resource handling avoids selecting the \"sleep\"\npinctrl state, which could disrupt transfers initiated by the other\nprocessor.\n\nFor GPI mode transfers, request lock/unlock TRE sequencing from the GPI\ndriver by setting a single lock_action selector per message, emitting lock\nbefore the first message and unlock after the last message (handling the\nsingle-message case as well). This serializes access to the shared\ncontroller without requiring message-position flags to be passed into the\nDMA engine layer.\n\nSigned-off-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>\n---\n drivers/i2c/busses/i2c-qcom-geni.c | 27 ++++++++++++++++++++++++++-\n 1 file changed, 26 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c\nindex ae609bdd2ec4..1925e4ec9842 100644\n--- a/drivers/i2c/busses/i2c-qcom-geni.c\n+++ b/drivers/i2c/busses/i2c-qcom-geni.c\n@@ -815,6 +815,14 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], i\n \t\tif (i < num - 1)\n \t\t\tperipheral.stretch = 1;\n \n+\t\tperipheral.lock_action = GPI_LOCK_NONE;\n+\t\tif (gi2c->se.multi_owner) {\n+\t\t\tif (i == 0)\n+\t\t\t\tperipheral.lock_action = GPI_LOCK_ACQUIRE;\n+\t\t\telse if (i == num - 1)\n+\t\t\t\tperipheral.lock_action = GPI_LOCK_RELEASE;\n+\t\t}\n+\n \t\tperipheral.addr = msgs[i].addr;\n \t\tif (i > 0 && (!(msgs[i].flags & I2C_M_RD)))\n \t\t\tperipheral.multi_msg = false;\n@@ -1014,6 +1022,17 @@ static int geni_i2c_probe(struct platform_device *pdev)\n \t\tgi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ;\n \t}\n \n+\tif (of_property_read_bool(pdev->dev.of_node, \"qcom,qup-multi-owner\")) {\n+\t\t/*\n+\t\t * Multi-owner controller configuration: the controller may be\n+\t\t * used by another system processor. Mark the SE as shared so\n+\t\t * common GENI resource handling can avoid pin state changes\n+\t\t * that would disrupt the other user.\n+\t\t */\n+\t\tgi2c->se.multi_owner = true;\n+\t\tdev_dbg(&pdev->dev, \"I2C controller is shared with another system processor\\n\");\n+\t}\n+\n \tif (has_acpi_companion(dev))\n \t\tACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));\n \n@@ -1089,7 +1108,9 @@ static int geni_i2c_probe(struct platform_device *pdev)\n \t}\n \n \tif (fifo_disable) {\n-\t\t/* FIFO is disabled, so we can only use GPI DMA */\n+\t\t/* FIFO is disabled, so we can only use GPI DMA.\n+\t\t * SE can be shared in GSI mode between subsystems, each SS owns a GPII.\n+\t\t */\n \t\tgi2c->gpi_mode = true;\n \t\tret = setup_gpi_dma(gi2c);\n \t\tif (ret)\n@@ -1098,6 +1119,10 @@ static int geni_i2c_probe(struct platform_device *pdev)\n \t\tdev_dbg(dev, \"Using GPI DMA mode for I2C\\n\");\n \t} else {\n \t\tgi2c->gpi_mode = false;\n+\n+\t\tif (gi2c->se.multi_owner)\n+\t\t\tdev_err_probe(dev, -EINVAL, \"I2C sharing not supported in non GSI mode\\n\");\n+\n \t\ttx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);\n \n \t\t/* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */\n", "prefixes": [ "v6", "4/4" ] }