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GET /api/patches/2218104/?format=api
{ "id": 2218104, "url": "http://patchwork.ozlabs.org/api/patches/2218104/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-i2c/patch/20260331114742.2896317-3-mukesh.savaliya@oss.qualcomm.com/", "project": { "id": 35, "url": "http://patchwork.ozlabs.org/api/projects/35/?format=api", "name": "Linux I2C development", "link_name": "linux-i2c", "list_id": "linux-i2c.vger.kernel.org", "list_email": "linux-i2c@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331114742.2896317-3-mukesh.savaliya@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-03-31T11:47:40", "name": "[v6,2/4] dmaengine: qcom: gpi: Add lock/unlock TREs for multi-owner I2C transfers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "db89ccc278abfdcedfd6319058f1df4721cab437", "submitter": { "id": 91179, "url": "http://patchwork.ozlabs.org/api/people/91179/?format=api", "name": "Mukesh Kumar Savaliya", "email": "mukesh.savaliya@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-i2c/patch/20260331114742.2896317-3-mukesh.savaliya@oss.qualcomm.com/mbox/", "series": [ { "id": 498183, "url": "http://patchwork.ozlabs.org/api/series/498183/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-i2c/list/?series=498183", "date": "2026-03-31T11:47:38", "name": "Enable multi-owner I2C support for QCOM GENI controllers", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498183/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218104/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218104/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-i2c+bounces-16895-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-i2c@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=HQ2CQPPy;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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arc=none smtp.client-ip=205.220.180.131", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n\tcc:content-transfer-encoding:date:from:in-reply-to:message-id\n\t:mime-version:references:subject:to; s=qcppdkim1; bh=wytVJC3ShD2\n\t5GSoHro9KhTpoqcx3xwCJ8CUBne86Gu4=; b=HQ2CQPPysvff/kgnUICSh76Sc8Q\n\twNYlTnw1COeAZboFZMFhDLNUn8F7vDHxQT/BCIX166lnGdlLErHGcTEfvbI/NZRK\n\tPqf5OcVWPfTeLoWB3BuW55fZd0gknGIk5zaWzNYCT/IrWbyIZhOcPFHj6QEcEK5D\n\ttvQ1sfRAV54PsIcFVRjg1V2iVJtbAbwS8nz6VJR5GQpTlD70slYbX+B1B8g9BRys\n\t2uDWEWwxKjGFJwWD3J3UEL+0DjAjD3mu2+7pw5mJZSaVlZFwPBqAg3YAtUy94KGY\n\tTOEZzL0S05YNV39sdHCnzjBvL8UjA9EoVKJzQ6vO7u6FW7DRE4kru0pTaeA==", "From": "Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>", "To": "viken.dadhaniya@oss.qualcomm.com, andi.shyti@kernel.org, robh@kernel.org,\n krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org,\n Frank.Li@kernel.org, andersson@kernel.org, konradybcio@kernel.org,\n dmitry.baryshkov@oss.qualcomm.com, linmq006@gmail.com,\n quic_jseerapu@quicinc.com, agross@kernel.org,\n linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n dmaengine@vger.kernel.org", "Cc": "krzysztof.kozlowski@oss.qualcomm.com,\n bartosz.golaszewski@oss.qualcomm.com,\n bjorn.andersson@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com,\n Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>", "Subject": "[PATCH v6 2/4] dmaengine: qcom: gpi: Add lock/unlock TREs for\n multi-owner I2C transfers", "Date": "Tue, 31 Mar 2026 17:17:40 +0530", "Message-Id": "<20260331114742.2896317-3-mukesh.savaliya@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260331114742.2896317-1-mukesh.savaliya@oss.qualcomm.com>", "References": "<20260331114742.2896317-1-mukesh.savaliya@oss.qualcomm.com>", "Precedence": "bulk", "X-Mailing-List": "linux-i2c@vger.kernel.org", "List-Id": "<linux-i2c.vger.kernel.org>", "List-Subscribe": "<mailto:linux-i2c+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-i2c+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QCInternal": [ "smtphost", "smtphost" ], "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMzMxMDExNCBTYWx0ZWRfX9Dd28/okfEFT\n qQH4hL9xPSK/zgTSzBPrrlrQkeei6r2X1Eiys+56wEwrp8ADbX/QfhNa2ZyC4KiEiAUUoyXuV/g\n 1WAzOVIAK2WUsHGLtUaLxX7c5hHlP1WKQNMKi2i7XVoQDPXahc9JkTW8yj5YfAGbCJOboUs88Pt\n Az+XJ8/yfwo+aIjmWnMqwqmOtvxbjTA3WdkjNpCLohIvRctEbbQWVj5gg8hMy7esl3IHG9gjIGL\n zTkaf4/4IvJ9d4nixSR2qkyf2KaudurxD1r+6SKVLRbF5Atdu/v9KvI1u+fRBGofT7o2xB0sPoy\n BXZ88sGJNNGQc3nJK+CzxohGLMh3IvunYdqAaATOqgqXvcn/ZA7M3HP3vorp5vaYoIb6m+eTOL0\n 8iOmvIVMr7jPX9Nz87TpOHHxg4TIiRKbVQAhnoBsLpdzY+ACW20hT1CnbwCdDpotmMPGCbZtbCs\n 3V9Wawr+CXmCq4d2Ilg==", "X-Authority-Analysis": "v=2.4 cv=K4wv3iWI c=1 sm=1 tr=0 ts=69cbb48a cx=c_pps\n a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22\n a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=mSgB-p_1VGLq_7tLs9EA:9", "X-Proofpoint-ORIG-GUID": "KTaOPoN9Od7DZSzgQNaOBqO80y4xZe-y", "X-Proofpoint-GUID": "KTaOPoN9Od7DZSzgQNaOBqO80y4xZe-y", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-03-31_02,2026-03-31_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 clxscore=1015 bulkscore=0 priorityscore=1501\n malwarescore=0 spamscore=0 adultscore=0 impostorscore=0 phishscore=0\n suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001\n definitions=main-2603310114" }, "content": "Some platforms use a QUP-based I2C controller in a configuration where the\ncontroller is shared with another system processor (described in DT using\nqcom,qup-multi-owner). In such setups, GPI hardware lock/unlock TREs can be\nused to serialize access to the controller.\n\nAdd support to emit lock and unlock TREs around I2C transfers and increase\nthe maximum TRE count to account for the additional elements.\n\nAlso simplify the client interface by replacing multiple boolean fields\n(shared flag and message position tracking) with a single lock_action\nselector (acquire/release/none), as the GPI driver only needs to know\nwhether to emit lock/unlock TREs for a given transfer.\n\nSigned-off-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>\n---\n drivers/dma/qcom/gpi.c | 44 +++++++++++++++++++++++++++++++-\n include/linux/dma/qcom-gpi-dma.h | 18 +++++++++++++\n 2 files changed, 61 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c\nindex 6e30f3aa401e..a1f391dd1747 100644\n--- a/drivers/dma/qcom/gpi.c\n+++ b/drivers/dma/qcom/gpi.c\n@@ -2,6 +2,7 @@\n /*\n * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.\n * Copyright (c) 2020, Linaro Limited\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n */\n \n #include <dt-bindings/dma/qcom-gpi.h>\n@@ -67,6 +68,14 @@\n #define TRE_DMA_LEN\t\tGENMASK(23, 0)\n #define TRE_DMA_IMMEDIATE_LEN\tGENMASK(3, 0)\n \n+/* Lock TRE */\n+#define TRE_LOCK\t\tBIT(0)\n+#define TRE_MINOR_TYPE\t\tGENMASK(19, 16)\n+#define TRE_MAJOR_TYPE\t\tGENMASK(23, 20)\n+\n+/* Unlock TRE */\n+#define TRE_UNLOCK\t\tBIT(8)\n+\n /* Register offsets from gpi-top */\n #define GPII_n_CH_k_CNTXT_0_OFFS(n, k)\t(0x20000 + (0x4000 * (n)) + (0x80 * (k)))\n #define GPII_n_CH_k_CNTXT_0_EL_SIZE\tGENMASK(31, 24)\n@@ -518,7 +527,7 @@ struct gpii {\n \tbool ieob_set;\n };\n \n-#define MAX_TRE 3\n+#define MAX_TRE 5\n \n struct gpi_desc {\n \tstruct virt_dma_desc vd;\n@@ -1625,12 +1634,27 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc,\n \t\t\t unsigned long flags)\n {\n \tstruct gpi_i2c_config *i2c = chan->config;\n+\tenum gpi_lock_action lock_action = i2c->lock_action;\n \tstruct device *dev = chan->gpii->gpi_dev->dev;\n \tunsigned int tre_idx = 0;\n \tdma_addr_t address;\n \tstruct gpi_tre *tre;\n \tunsigned int i;\n \n+\t/* Optional lock TRE before transfer */\n+\tif (lock_action == GPI_LOCK_ACQUIRE) {\n+\t\ttre = &desc->tre[tre_idx];\n+\t\ttre_idx++;\n+\n+\t\ttre->dword[0] = 0;\n+\t\ttre->dword[1] = 0;\n+\t\ttre->dword[2] = 0;\n+\t\ttre->dword[3] = u32_encode_bits(1, TRE_LOCK);\n+\t\ttre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOB);\n+\t\ttre->dword[3] |= u32_encode_bits(0, TRE_MINOR_TYPE);\n+\t\ttre->dword[3] |= u32_encode_bits(3, TRE_MAJOR_TYPE);\n+\t}\n+\n \t/* first create config tre if applicable */\n \tif (i2c->set_config) {\n \t\ttre = &desc->tre[tre_idx];\n@@ -1690,6 +1714,24 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc,\n \n \t\tif (!(flags & DMA_PREP_INTERRUPT))\n \t\t\ttre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_BEI);\n+\n+\t\t/* If multi-owner and this is the release boundary, chain it */\n+\t\tif (i2c->lock_action == GPI_LOCK_RELEASE)\n+\t\t\ttre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN);\n+\t}\n+\n+\t/* Optional unlock TRE after transfer */\n+\tif (lock_action == GPI_LOCK_RELEASE && i2c->op != I2C_READ) {\n+\t\ttre = &desc->tre[tre_idx];\n+\t\ttre_idx++;\n+\n+\t\ttre->dword[0] = 0;\n+\t\ttre->dword[1] = 0;\n+\t\ttre->dword[2] = 0;\n+\t\ttre->dword[3] = u32_encode_bits(1, TRE_UNLOCK);\n+\t\ttre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOB);\n+\t\ttre->dword[3] |= u32_encode_bits(1, TRE_MINOR_TYPE);\n+\t\ttre->dword[3] |= u32_encode_bits(3, TRE_MAJOR_TYPE);\n \t}\n \n \tfor (i = 0; i < tre_idx; i++)\ndiff --git a/include/linux/dma/qcom-gpi-dma.h b/include/linux/dma/qcom-gpi-dma.h\nindex 6680dd1a43c6..36cbb85499b4 100644\n--- a/include/linux/dma/qcom-gpi-dma.h\n+++ b/include/linux/dma/qcom-gpi-dma.h\n@@ -1,6 +1,7 @@\n /* SPDX-License-Identifier: GPL-2.0 */\n /*\n * Copyright (c) 2020, Linaro Limited\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n */\n \n #ifndef QCOM_GPI_DMA_H\n@@ -51,6 +52,21 @@ enum i2c_op {\n \tI2C_READ,\n };\n \n+/**\n+ * enum gpi_lock_action - request lock/unlock TRE sequencing\n+ * @GPI_LOCK_NONE: No lock/unlock TRE requested for this transfer\n+ * @GPI_LOCK_ACQUIRE: Emit a lock TRE before the transfer\n+ * @GPI_LOCK_RELEASE: Emit an unlock TRE after the transfer\n+ *\n+ * Used by protocol drivers for multi-owner controller setups (e.g. when\n+ * DeviceTree indicates the controller is shared via qcom,qup-multi-owner).\n+ */\n+enum gpi_lock_action {\n+\tGPI_LOCK_NONE = 0,\n+\tGPI_LOCK_ACQUIRE,\n+\tGPI_LOCK_RELEASE,\n+};\n+\n /**\n * struct gpi_i2c_config - i2c config for peripheral\n *\n@@ -65,6 +81,7 @@ enum i2c_op {\n * @rx_len: receive length for buffer\n * @op: i2c cmd\n * @muli-msg: is part of multi i2c r-w msgs\n+ * @lock_action: request lock/unlock TRE sequencing for this transfer\n */\n struct gpi_i2c_config {\n \tu8 set_config;\n@@ -78,6 +95,7 @@ struct gpi_i2c_config {\n \tu32 rx_len;\n \tenum i2c_op op;\n \tbool multi_msg;\n+\tenum gpi_lock_action lock_action;\n };\n \n #endif /* QCOM_GPI_DMA_H */\n", "prefixes": [ "v6", "2/4" ] }