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GET /api/patches/2218100/?format=api
{ "id": 2218100, "url": "http://patchwork.ozlabs.org/api/patches/2218100/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260331113835.3510341-2-eleanor.lin@realtek.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331113835.3510341-2-eleanor.lin@realtek.com>", "list_archive_url": null, "date": "2026-03-31T11:38:33", "name": "[1/3] dt-bindings: gpio: realtek: Add realtek,rtd1625-gpio", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "661e645a6c1baa60a7a58a0db3562f4ccc7cd6a4", "submitter": { "id": 92797, "url": "http://patchwork.ozlabs.org/api/people/92797/?format=api", "name": "Yu-Chun Lin", "email": "eleanor.lin@realtek.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260331113835.3510341-2-eleanor.lin@realtek.com/mbox/", "series": [ { "id": 498182, "url": "http://patchwork.ozlabs.org/api/series/498182/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=498182", "date": "2026-03-31T11:38:35", "name": "gpio: realtek: Add support for Realtek DHC RTD1625", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498182/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218100/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218100/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-34475-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=realtek.com header.i=@realtek.com header.a=rsa-sha256\n header.s=dkim header.b=tsHvh5lN;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-gpio+bounces-34475-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com\n header.b=\"tsHvh5lN\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=211.75.126.72", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=realtek.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=realtek.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4flRGV0SPMz1xtJ\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 31 Mar 2026 22:48:50 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 2B33E3095C08\n\tfor <incoming@patchwork.ozlabs.org>; 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Tue, 31 Mar 2026 19:38:35 +0800", "from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS04.realtek.com.tw\n (10.21.1.54) with Microsoft SMTP Server id 15.2.1748.10 via Frontend\n Transport; Tue, 31 Mar 2026 19:38:35 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774957297; cv=none;\n b=mbXuhPiqGdM/l9jaWG3lTPmWvsuYfez3ezfinZzN/R3YNmgfHJqKnpUjg0gmvcHQQp8Ctn2HxInepGNylK7/IoIopbkOtcrYV7yApEbT6Cxlp4lSH9d6e/8EMEVMk9mjkF3vwUQE5qfY/HbYebs6ViAcG51ZkY3nCol+evPuIes=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774957297; c=relaxed/simple;\n\tbh=+L/K8+O6tMPwhjokt9uI6DRjPbeTQNlOvbn7Q7JVKSk=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=dl6VIlwnUeKvnNEXUZZiPcN875coO39MqUtrQXGQRU+Ldws96fXK8bx7tPCRcpnuKjB8wdBHhxxzLAYkEEi2Kxc/wA4If9RZiB3UaKG2pIGk2XgtSXzgpCK132YSEnKYsJU+TvVOsGccdSsQzqqtsvERdTULaFq80EjMF7uX3Cs=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=realtek.com;\n spf=pass smtp.mailfrom=realtek.com;\n dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com\n header.b=tsHvh5lN; arc=none smtp.client-ip=211.75.126.72", "X-SpamFilter-By": "ArmorX SpamTrap 5.80 with qID 62VBcZbgD3149080,\n This message is accepted by code: ctloc85258", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim;\n\tt=1774957115; bh=R54LgNHSFQobFVsX7fHxSQcvp4mTFC0QLJ2acEvsUu0=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Transfer-Encoding:Content-Type;\n\tb=tsHvh5lNzoiQ+YHoqn6jZtfHdalvYo5kI0cm/1ZfK4UWlg1UoGjaECW6jsKQo5D54\n\t ZO54s58KfMspsCXJFa1a/+qAhT9DywFtmu4rXkLAf/sVxINdgG4E16YCEA4w1R1s+D\n\t SOeSBT+oEL/rbC48rcfM8yorE4izp+sPgel5sYmQB4Z101+XGD7SPbWKO7ngyU88+j\n\t J1VVxoocQJvC+rYfh3YwBjj2NBzZ0J6aQsJamtb4K+7LizZqciodPuJpWSQfh9vhdc\n\t o3vymAno8Nr7rdBOrZqeSV3uibkeupVZ8vwgEVaVXPFFPCw9FgzmMnTkVpzIN7dgiq\n\t w4szu6zwXlReg==", "From": "Yu-Chun Lin <eleanor.lin@realtek.com>", "To": "<linusw@kernel.org>, <brgl@kernel.org>, <robh@kernel.org>,\n <krzk+dt@kernel.org>, <conor+dt@kernel.org>, <afaerber@suse.com>,\n <tychang@realtek.com>", "CC": "<linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>,\n <linux-kernel@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>,\n <linux-realtek-soc@lists.infradead.org>, <cy.huang@realtek.com>,\n <stanley_chang@realtek.com>, <eleanor.lin@realtek.com>,\n <james.tai@realtek.com>", "Subject": "[PATCH 1/3] dt-bindings: gpio: realtek: Add realtek,rtd1625-gpio", "Date": "Tue, 31 Mar 2026 19:38:33 +0800", "Message-ID": "<20260331113835.3510341-2-eleanor.lin@realtek.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260331113835.3510341-1-eleanor.lin@realtek.com>", "References": "<20260331113835.3510341-1-eleanor.lin@realtek.com>", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain" }, "content": "From: Tzuyi Chang <tychang@realtek.com>\n\nAdd the device tree bindings for the Realtek DHC (Digital Home Center)\nRTD1625 GPIO controllers.\n\nThe RTD1625 GPIO controller features a per-pin register architecture\nthat differs significantly from previous generations. It utilizes\nseparate register blocks for GPIO configuration and interrupt control.\n\nSigned-off-by: Tzuyi Chang <tychang@realtek.com>\nSigned-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>\n---\n .../bindings/gpio/realtek,rtd1625-gpio.yaml | 74 +++++++++++++++++++\n 1 file changed, 74 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml", "diff": "diff --git a/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml b/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml\nnew file mode 100644\nindex 000000000000..e81d13dfefc2\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml\n@@ -0,0 +1,74 @@\n+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)\n+# Copyright 2023 Realtek Semiconductor Corporation\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/gpio/realtek,rtd1625-gpio.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Realtek DHC RTD1625 GPIO controller\n+\n+maintainers:\n+ - Tzuyi Chang <tychang@realtek.com>\n+\n+description: |\n+ GPIO controller for the Realtek RTD1625 SoC, featuring a per-pin register\n+ architecture that differs significantly from earlier RTD series controllers.\n+ Each GPIO has dedicated registers for configuration (direction, input/output\n+ values, debounce), and interrupt control supporting edge and level detection\n+ modes.\n+\n+properties:\n+ compatible:\n+ enum:\n+ - realtek,rtd1625-iso-gpio\n+ - realtek,rtd1625-isom-gpio\n+\n+ reg:\n+ items:\n+ - description: GPIO controller registers\n+ - description: GPIO interrupt registers\n+\n+ interrupts:\n+ items:\n+ - description: Interrupt number of the assert GPIO interrupt, which is\n+ triggered when there is a rising edge.\n+ - description: Interrupt number of the deassert GPIO interrupt, which is\n+ triggered when there is a falling edge.\n+ - description: Interrupt number of the level-sensitive GPIO interrupt,\n+ triggered by a configured logic level.\n+\n+ interrupt-controller: true\n+\n+ \"#interrupt-cells\":\n+ const: 2\n+\n+ gpio-ranges: true\n+\n+ gpio-controller: true\n+\n+ \"#gpio-cells\":\n+ const: 2\n+\n+required:\n+ - compatible\n+ - reg\n+ - gpio-ranges\n+ - gpio-controller\n+ - \"#gpio-cells\"\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ gpio@89120 {\n+ compatible = \"realtek,rtd1625-isom-gpio\";\n+ reg = <0x89120 0x10>,\n+ <0x89100 0x20>;\n+ interrupt-parent = <&iso_m_irq_mux>;\n+ interrupts = <0>, <1>, <2>;\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+ gpio-ranges = <&isom_pinctrl 0 0 4>;\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+ };\n", "prefixes": [ "1/3" ] }