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GET /api/patches/2218096/?format=api
{ "id": 2218096, "url": "http://patchwork.ozlabs.org/api/patches/2218096/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260331113025.1566878-14-wei.fang@nxp.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20260331113025.1566878-14-wei.fang@nxp.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20260331113025.1566878-14-wei.fang@nxp.com/", "date": "2026-03-31T11:30:24", "name": "[v4,net-next,13/14] net: dsa: netc: initialize buffer bool table and implement flow-control", "commit_ref": null, "pull_url": null, "state": "handled-elsewhere", "archived": false, "hash": "8b7c06030ce991e03f6b13e4f94d9a773ad94a98", "submitter": { "id": 84380, "url": "http://patchwork.ozlabs.org/api/people/84380/?format=api", "name": "Wei Fang", "email": "wei.fang@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260331113025.1566878-14-wei.fang@nxp.com/mbox/", "series": [ { "id": 498181, "url": "http://patchwork.ozlabs.org/api/series/498181/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=498181", "date": "2026-03-31T11:30:11", "name": "Add preliminary NETC switch support for i.MX94", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/498181/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218096/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218096/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linuxppc-dev+bounces-19078-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256\n header.s=selector1 header.b=JwgA6V0Z;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; helo=lists.ozlabs.org;\n envelope-from=linuxppc-dev+bounces-19078-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)", "lists.ozlabs.org;\n arc=pass smtp.remote-ip=\"2a01:111:f403:c207::3\" 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envelope-from=wei.fang@nxp.com;\n receiver=lists.ozlabs.org) smtp.mailfrom=nxp.com", "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass\n header.d=nxp.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=WzQ+KWO9NQuMMRcE0+jYRNxdluvpUt367q/0E31+7x4=;\n b=JwgA6V0ZJo1UefJ8xbgGAcDz/wRUgJRehuO3198K4HrwldxAg1unpVvioCbIAaC/tVqs09i8Bi4mD/LsugDGRyc5GnvYjjB3yQl+sEvIUkcGTzfyPSWseKaEjlcnHUlA61NRAXKTUCY+445RpGdWKA+Zn0ziEv/QyvTDArOklcju+rs49TRwtyGw/Lp17J73ryULWMwEHwl9y1dkhTq2GLY9ysOE2u9smy/DTf5Sstf6hms0CT5Xiz0rmJhdW9e4dSF4D/a77V0QFX1okfFhw+to872Yj769HW+etaVefTgFTko0DYsJGVjs3a4e6u304zgoa3wZ2B8iC/orSxKcOw==", "From": "Wei Fang <wei.fang@nxp.com>", "To": "claudiu.manoil@nxp.com,\n\tvladimir.oltean@nxp.com,\n\txiaoning.wang@nxp.com,\n\tandrew+netdev@lunn.ch,\n\tdavem@davemloft.net,\n\tedumazet@google.com,\n\tkuba@kernel.org,\n\tpabeni@redhat.com,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tf.fainelli@gmail.com,\n\tfrank.li@nxp.com,\n\tchleroy@kernel.org,\n\thorms@kernel.org,\n\tlinux@armlinux.org.uk,\n\tandrew@lunn.ch", "Cc": "netdev@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinuxppc-dev@lists.ozlabs.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\timx@lists.linux.dev", "Subject": "[PATCH v4 net-next 13/14] net: dsa: netc: initialize buffer bool\n table and implement flow-control", "Date": "Tue, 31 Mar 2026 19:30:24 +0800", "Message-Id": "<20260331113025.1566878-14-wei.fang@nxp.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260331113025.1566878-1-wei.fang@nxp.com>", "References": "<20260331113025.1566878-1-wei.fang@nxp.com>", "Content-Type": "text/plain; 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"X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0d83c257-0f07-4972-0559-08de8f18daa2", "X-MS-Exchange-CrossTenant-AuthSource": "AM8PR04MB7284.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Mar 2026 11:30:04.4182\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n mJr36oWhe2Nm2UrjA71m+KCYiNaAb6byanmykXxSWa6k9yrxbK9PVGfcOne+UyxXJO7YDcVkxhKrcgz0asZuvQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DU4PR04MB12064", "X-Spam-Status": "No, score=0.8 required=3.0 tests=ARC_SIGNED,ARC_VALID,\n\tDKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,\n\tSPF_HELO_PASS,T_SPF_PERMERROR autolearn=disabled version=4.0.1 OzLabs 8", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org" }, "content": "The buffer pool is a quantity of memory available for buffering a group\nof flows (e.g. frames having the same priority, frames received from the\nsame port), while waiting to be transmitted on a port. The buffer pool\ntracks internal memory consumption with upper bound limits and optionally\na non-shared portion when associated with a shared buffer pool. Currently\nthe shared buffer pool is not supported, it will be added in the future.\n\nFor i.MX94, the switch has 4 ports and 8 buffer pools, so each port is\nallocated two buffer pools. For frames with priorities of 0 to 3, they\nwill be mapped to the first buffer pool; For frames with priorities of\n4 to 7, they will be mapped to the second buffer pool. Each buffer pool\nhas a flow control on threshold and a flow control off threshold. By\nsetting these threshold, add the flow control support to each port.\n\nSigned-off-by: Wei Fang <wei.fang@nxp.com>\n---\n drivers/net/dsa/netc/netc_main.c | 133 ++++++++++++++++++++++++++\n drivers/net/dsa/netc/netc_switch.h | 9 ++\n drivers/net/dsa/netc/netc_switch_hw.h | 13 +++\n 3 files changed, 155 insertions(+)", "diff": "diff --git a/drivers/net/dsa/netc/netc_main.c b/drivers/net/dsa/netc/netc_main.c\nindex 3609d83ac363..688dceb486c2 100644\n--- a/drivers/net/dsa/netc/netc_main.c\n+++ b/drivers/net/dsa/netc/netc_main.c\n@@ -379,6 +379,8 @@ static void netc_port_set_mlo(struct netc_port *np, enum netc_mlo mlo)\n \n static void netc_port_fixed_config(struct netc_port *np)\n {\n+\tu32 pqnt = 0xffff, qth = 0xff00;\n+\n \t/* Default IPV and DR setting */\n \tnetc_port_rmw(np, NETC_PQOSMR, PQOSMR_VS | PQOSMR_VE,\n \t\t PQOSMR_VS | PQOSMR_VE);\n@@ -386,6 +388,15 @@ static void netc_port_fixed_config(struct netc_port *np)\n \t/* Enable L2 and L3 DOS */\n \tnetc_port_rmw(np, NETC_PCR, PCR_L2DOSE | PCR_L3DOSE,\n \t\t PCR_L2DOSE | PCR_L3DOSE);\n+\n+\t/* Set the quanta value of TX PAUSE frame */\n+\tnetc_mac_port_wr(np, NETC_PM_PAUSE_QUANTA(0), pqnt);\n+\n+\t/* When a quanta timer counts down and reaches this value,\n+\t * the MAC sends a refresh PAUSE frame with the programmed\n+\t * full quanta value if a pause condition still exists.\n+\t */\n+\tnetc_mac_port_wr(np, NETC_PM_PAUSE_TRHESH(0), qth);\n }\n \n static void netc_port_default_config(struct netc_port *np)\n@@ -617,6 +628,87 @@ static int netc_add_standalone_fdb_bcast_entry(struct netc_switch *priv)\n \t\t\t\t bcast, NETC_STANDALONE_PVID);\n }\n \n+static u32 netc_get_buffer_pool_num(struct netc_switch *priv)\n+{\n+\t/* The BPCAPR register is a read only register, the hardware\n+\t * guarantees that the BPCAPR_NUM_BP field will not be 0.\n+\t */\n+\treturn netc_base_rd(&priv->regs, NETC_BPCAPR) & BPCAPR_NUM_BP;\n+}\n+\n+static void netc_port_set_pbpmcr(struct netc_port *np, u64 mapping)\n+{\n+\tu32 pbpmcr0 = lower_32_bits(mapping);\n+\tu32 pbpmcr1 = upper_32_bits(mapping);\n+\n+\tnetc_port_wr(np, NETC_PBPMCR0, pbpmcr0);\n+\tnetc_port_wr(np, NETC_PBPMCR1, pbpmcr1);\n+}\n+\n+static void netc_ipv_to_buffer_pool_mapping(struct netc_switch *priv)\n+{\n+\tint bp_per_port = priv->num_bp / priv->info->num_ports;\n+\tint q = NETC_IPV_NUM / bp_per_port;\n+\tint r = NETC_IPV_NUM % bp_per_port;\n+\tint num = q + r;\n+\n+\t/* IPV-to–buffer-pool mapping per port:\n+\t * Each port is allocated 'bp_per_port' buffer pools and supports 8\n+\t * IPVs, where a higher IPV indicates a higher frame priority. Each\n+\t * IPV can be mapped to only one buffer pool.\n+\t *\n+\t * The mapping rule is as follows:\n+\t * - The first 'num' IPVs share the port's first buffer pool (index\n+\t * 'base_id').\n+\t * - After that, every 'q' IPVs share one buffer pool, with pool\n+\t * indices increasing sequentially.\n+\t */\n+\tfor (int i = 0; i < priv->info->num_ports; i++) {\n+\t\tu32 base_id = i * bp_per_port;\n+\t\tu32 bp_id = base_id;\n+\t\tu64 mapping = 0;\n+\n+\t\tfor (int ipv = 0; ipv < NETC_IPV_NUM; ipv++) {\n+\t\t\t/* Update the buffer pool index */\n+\t\t\tif (ipv >= num)\n+\t\t\t\tbp_id = base_id + ((ipv - num) / q) + 1;\n+\n+\t\t\tmapping |= (u64)bp_id << (ipv * 8);\n+\t\t}\n+\n+\t\tnetc_port_set_pbpmcr(priv->ports[i], mapping);\n+\t}\n+}\n+\n+static int netc_switch_bpt_default_config(struct netc_switch *priv)\n+{\n+\t/* priv->num_bp is read from register, based on the NETC block\n+\t * guide, its value is hardcoded to a non-zero value. And it\n+\t * is greater than the number of ports (priv->info->num_ports).\n+\t */\n+\tpriv->num_bp = netc_get_buffer_pool_num(priv);\n+\tpriv->bpt_list = devm_kcalloc(priv->dev, priv->num_bp,\n+\t\t\t\t sizeof(struct bpt_cfge_data),\n+\t\t\t\t GFP_KERNEL);\n+\tif (!priv->bpt_list)\n+\t\treturn -ENOMEM;\n+\n+\t/* Initialize the maximum threshold of each buffer pool entry */\n+\tfor (int i = 0; i < priv->num_bp; i++) {\n+\t\tstruct bpt_cfge_data *cfge = &priv->bpt_list[i];\n+\t\tint err;\n+\n+\t\tcfge->max_thresh = cpu_to_le16(NETC_BP_THRESH);\n+\t\terr = ntmp_bpt_update_entry(&priv->ntmp, i, cfge);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n+\n+\tnetc_ipv_to_buffer_pool_mapping(priv);\n+\n+\treturn 0;\n+}\n+\n static int netc_setup(struct dsa_switch *ds)\n {\n \tstruct netc_switch *priv = ds->priv;\n@@ -644,6 +736,10 @@ static int netc_setup(struct dsa_switch *ds)\n \tdsa_switch_for_each_available_port(dp, ds)\n \t\tnetc_port_default_config(priv->ports[dp->index]);\n \n+\terr = netc_switch_bpt_default_config(priv);\n+\tif (err)\n+\t\tgoto free_lock_and_ntmp_user;\n+\n \terr = netc_add_standalone_vlan_entry(priv);\n \tif (err)\n \t\tgoto free_lock_and_ntmp_user;\n@@ -1195,6 +1291,41 @@ static void netc_port_set_rmii_mii_mac(struct netc_port *np,\n \tnetc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val);\n }\n \n+static void netc_port_set_tx_pause(struct netc_port *np, bool tx_pause)\n+{\n+\tstruct netc_switch *priv = np->switch_priv;\n+\tint port = np->dp->index;\n+\tint i, j, num_bp;\n+\n+\tnum_bp = priv->num_bp / priv->info->num_ports;\n+\tfor (i = 0, j = port * num_bp; i < num_bp; i++, j++) {\n+\t\tstruct bpt_cfge_data *cfge = &priv->bpt_list[j];\n+\t\tstruct bpt_cfge_data old_cfge = *cfge;\n+\n+\t\tif (tx_pause) {\n+\t\t\tcfge->fc_on_thresh = cpu_to_le16(NETC_FC_THRESH_ON);\n+\t\t\tcfge->fc_off_thresh = cpu_to_le16(NETC_FC_THRESH_OFF);\n+\t\t\tcfge->fccfg_sbpen = FIELD_PREP(BPT_FC_CFG,\n+\t\t\t\t\t\t BPT_FC_CFG_EN_BPFC);\n+\t\t\tcfge->fc_ports = cpu_to_le32(BIT(port));\n+\t\t} else {\n+\t\t\tcfge->fc_on_thresh = cpu_to_le16(0);\n+\t\t\tcfge->fc_off_thresh = cpu_to_le16(0);\n+\t\t\tcfge->fccfg_sbpen = 0;\n+\t\t\tcfge->fc_ports = cpu_to_le32(0);\n+\t\t}\n+\n+\t\tif (ntmp_bpt_update_entry(&priv->ntmp, j, cfge))\n+\t\t\t*cfge = old_cfge;\n+\t}\n+}\n+\n+static void netc_port_set_rx_pause(struct netc_port *np, bool rx_pause)\n+{\n+\tnetc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_PAUSE_IGN,\n+\t\t\t rx_pause ? 0 : PM_CMD_CFG_PAUSE_IGN);\n+}\n+\n static void netc_port_mac_rx_enable(struct netc_port *np)\n {\n \tnetc_port_rmw(np, NETC_POR, PCR_RXDIS, 0);\n@@ -1256,6 +1387,8 @@ static void netc_mac_link_up(struct phylink_config *config,\n \t interface == PHY_INTERFACE_MODE_MII)\n \t\tnetc_port_set_rmii_mii_mac(np, speed, duplex);\n \n+\tnetc_port_set_tx_pause(np, tx_pause);\n+\tnetc_port_set_rx_pause(np, rx_pause);\n \tnetc_port_mac_rx_enable(np);\n }\n \ndiff --git a/drivers/net/dsa/netc/netc_switch.h b/drivers/net/dsa/netc/netc_switch.h\nindex 4b229a71578e..7ebffb136b2f 100644\n--- a/drivers/net/dsa/netc/netc_switch.h\n+++ b/drivers/net/dsa/netc/netc_switch.h\n@@ -32,6 +32,12 @@\n \n #define NETC_STANDALONE_PVID\t\t0\n \n+#define NETC_IPV_NUM\t\t\t8\n+/* MANT = bits 11:4, EXP = bits 3:0, threshold = MANT * 2 ^ EXP */\n+#define NETC_BP_THRESH\t\t\t0x334\n+#define NETC_FC_THRESH_ON\t\t0x533\n+#define NETC_FC_THRESH_OFF\t\t0x3c3\n+\n struct netc_switch;\n \n struct netc_switch_info {\n@@ -90,6 +96,9 @@ struct netc_switch {\n \tstruct ntmp_user ntmp;\n \tstruct hlist_head fdb_list;\n \tstruct mutex fdbt_lock; /* FDB table lock */\n+\n+\tu32 num_bp;\n+\tstruct bpt_cfge_data *bpt_list;\n };\n \n #define NETC_PRIV(ds)\t\t\t((struct netc_switch *)((ds)->priv))\ndiff --git a/drivers/net/dsa/netc/netc_switch_hw.h b/drivers/net/dsa/netc/netc_switch_hw.h\nindex c6a0c0a8ff8a..1e1c0d279a21 100644\n--- a/drivers/net/dsa/netc/netc_switch_hw.h\n+++ b/drivers/net/dsa/netc/netc_switch_hw.h\n@@ -12,6 +12,12 @@\n #define NETC_SWITCH_DEVICE_ID\t\t0xeef2\n \n /* Definition of Switch base registers */\n+#define NETC_BPCAPR\t\t\t0x0008\n+#define BPCAPR_NUM_BP\t\t\tGENMASK(7, 0)\n+\n+#define NETC_PBPMCR0\t\t\t0x0400\n+#define NETC_PBPMCR1\t\t\t0x0404\n+\n #define NETC_CBDRMR(a)\t\t\t(0x0800 + (a) * 0x30)\n #define NETC_CBDRBAR0(a)\t\t(0x0810 + (a) * 0x30)\n #define NETC_CBDRBAR1(a)\t\t(0x0814 + (a) * 0x30)\n@@ -138,6 +144,7 @@ enum netc_stg_stage {\n #define NETC_PM_CMD_CFG(a)\t\t(0x1008 + (a) * 0x400)\n #define PM_CMD_CFG_TX_EN\t\tBIT(0)\n #define PM_CMD_CFG_RX_EN\t\tBIT(1)\n+#define PM_CMD_CFG_PAUSE_IGN\t\tBIT(8)\n \n #define NETC_PM_MAXFRM(a)\t\t(0x1014 + (a) * 0x400)\n #define PM_MAXFRAM\t\t\tGENMASK(15, 0)\n@@ -145,6 +152,12 @@ enum netc_stg_stage {\n #define NETC_PM_IEVENT(a)\t\t(0x1040 + (a) * 0x400)\n #define PM_IEVENT_RX_EMPTY\t\tBIT(6)\n \n+#define NETC_PM_PAUSE_QUANTA(a)\t\t(0x1054 + (a) * 0x400)\n+#define PAUSE_QUANTA_PQNT\t\tGENMASK(15, 0)\n+\n+#define NETC_PM_PAUSE_TRHESH(a)\t\t(0x1064 + (a) * 0x400)\n+#define PAUSE_TRHESH_QTH\t\tGENMASK(15, 0)\n+\n #define NETC_PM_IF_MODE(a)\t\t(0x1300 + (a) * 0x400)\n #define PM_IF_MODE_IFMODE\t\tGENMASK(2, 0)\n #define IFMODE_MII\t\t\t1\n", "prefixes": [ "v4", "net-next", "13/14" ] }