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GET /api/patches/2218060/?format=api
{ "id": 2218060, "url": "http://patchwork.ozlabs.org/api/patches/2218060/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260331102303.33181-5-akhilrajeev@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331102303.33181-5-akhilrajeev@nvidia.com>", "list_archive_url": null, "date": "2026-03-31T10:22:57", "name": "[v6,04/10] dmaengine: tegra: Make reset control optional", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "47cd0af4b6a4c1b8bbcc43813a962dff5dbceca4", "submitter": { "id": 81965, "url": "http://patchwork.ozlabs.org/api/people/81965/?format=api", "name": "Akhil R", "email": "akhilrajeev@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260331102303.33181-5-akhilrajeev@nvidia.com/mbox/", "series": [ { "id": 498169, "url": "http://patchwork.ozlabs.org/api/series/498169/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=498169", "date": "2026-03-31T10:22:54", "name": "Add GPCDMA support in Tegra264", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498169/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218060/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218060/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13474-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Ylvma1zm;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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pr=C", "From": "Akhil R <akhilrajeev@nvidia.com>", "To": "Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>, Rob Herring\n\t<robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley\n\t<conor+dt@kernel.org>, Thierry Reding <thierry.reding@gmail.com>, \"Jonathan\n Hunter\" <jonathanh@nvidia.com>, Laxman Dewangan <ldewangan@nvidia.com>,\n\tPhilipp Zabel <p.zabel@pengutronix.de>, <dmaengine@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "Akhil R <akhilrajeev@nvidia.com>, Frank Li <Frank.Li@nxp.com>", "Subject": "[PATCH v6 04/10] dmaengine: tegra: Make reset control optional", "Date": "Tue, 31 Mar 2026 15:52:57 +0530", "Message-ID": "<20260331102303.33181-5-akhilrajeev@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260331102303.33181-1-akhilrajeev@nvidia.com>", "References": "<20260331102303.33181-1-akhilrajeev@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS3PEPF0000C380:EE_|MN0PR12MB5834:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0d7ccb5b-f0e0-490e-03af-08de8f0fa7d2", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|7416014|921020|18002099003|22082099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\tWPa3lXIKNcUrVCIJuB9waxCww+6y5UvLsKwxtMCsT0qiVr2y4ue5FFG5ACshjimq6uQrsUAJmYKyuCOx/FBIdN8VJfO9efn26uBV85YEKFqg7JPhG6hi8Cpv2zUCnyORrNjDkWcBT7S9/q/VwONvNa4THcfSjmOt4Y90v/C6IHsb08A+6dGR8Z1p6I3urpsPGEIVSVk8JoL7kv5YRFDPG5aYZg/mCb/zKoIrBxZz1Ynn0GAw71kAW7HL2/vJXO2UsTKf0etcYIzjfB59GYUYBbFxaDWSrC2MidA6+BgrHxtYZOagyif7jJWwmrDo3lA0MzEzXbZm2eZMKmYerwF3UOwsYS1cl93zwr6UpZ3kUigRljNxF4nC+nLPCif0bSfmHk8foAEHOlMJwqwLI7+dy72wRk/f2f9Dr9b2hZsBMBNtycsmQ8FoiKEUYylGEt7gtsQOnvZgbfK9FyBGvDQWj5df6BJsr7b4vF8PjayTDKIYFUvYM74Lyp3VimBomWvf7mPulbljCHUBYnM3+XkQYM/4V2IKEKXOrw8wyx33xA79tLe7LCU/fpyx0fijjpwWQJ/J8bzPKSLc4JTgcHGHt3tfvz2OOc/k1coWIQaBjay+u4vqu2dLGdw5s18IVLL947fJ6R45R3IKC+z/C9dx8pkQW22EK15LofxHqKjn4aPZDPcUjC8EmiEUIuS2WSD4AMWh5A8yoR4D0HejxFJYek2QzedQP8zKY1ufZL62jUmI7MoNHqDK9klySLXB6yyCAhxRbLIQFDz9OKaPPr65F+MIh1k4dRqhFGJ9+CeqU/Q2Q83NBB8TUcjlX8m+Sa0S", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(7416014)(921020)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tfrqWwC1OBWLGFWtwmGRUINlEPNqUJfwxXF4EUCLLD8DZQ5tfX/oRenCc4bX+s5Z9FGroJ10BaSzqB4sjzCKIXYuq0bRbtMsyHgrvDoC+cxLZr5cqa+WVqd0bz59P0F0+df2PvexYtxIbD4veElZ3wGvzu688lKfKXz/2D86vz2EwwfxNb+zwRAw0GL0yGK3rzAHbFBiilBR2haXHwIUK4Ti3N16GpDZM1JHFkfqJQOViASSLBj4YBxyeO4JMMDiyB5y3MkHTq+PyEgcMl1D+YetvVGovilbZobxU//vMEwj5fx63/JYRfmXNyv8gFReVCZfyZYVL7HSL6z4od2HqBXs42nBI8uWsGi+ILkeThiCP+P8St8HeMDLM5DpHtXiJVRg3JACZFDk442CTV72zITjHkfMpzOpwbk1DStt9/2wJFkUmlCOGtjavsW7yoxH4", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Mar 2026 10:24:13.4797\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0d7ccb5b-f0e0-490e-03af-08de8f0fa7d2", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tDS3PEPF0000C380.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN0PR12MB5834" }, "content": "On Tegra264, reset is not available for the driver to control as\nthis is handled by the boot firmware. Hence make the reset control\noptional and update the error message to reflect the correct error.\n\nSigned-off-by: Akhil R <akhilrajeev@nvidia.com>\nReviewed-by: Frank Li <Frank.Li@nxp.com>\n---\n drivers/dma/tegra186-gpc-dma.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c\nindex 5948fbf32c21..a0522a992ebc 100644\n--- a/drivers/dma/tegra186-gpc-dma.c\n+++ b/drivers/dma/tegra186-gpc-dma.c\n@@ -1381,10 +1381,10 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \tif (IS_ERR(tdma->base_addr))\n \t\treturn PTR_ERR(tdma->base_addr);\n \n-\ttdma->rst = devm_reset_control_get_exclusive(&pdev->dev, \"gpcdma\");\n+\ttdma->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, \"gpcdma\");\n \tif (IS_ERR(tdma->rst)) {\n \t\treturn dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst),\n-\t\t\t \"Missing controller reset\\n\");\n+\t\t\t \"Failed to get controller reset\\n\");\n \t}\n \treset_control_reset(tdma->rst);\n \n", "prefixes": [ "v6", "04/10" ] }