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GET /api/patches/2218003/?format=api
{ "id": 2218003, "url": "http://patchwork.ozlabs.org/api/patches/2218003/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260331085252.1243108-1-hongxing.zhu@nxp.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331085252.1243108-1-hongxing.zhu@nxp.com>", "list_archive_url": null, "date": "2026-03-31T08:52:52", "name": "[v3] PCI: imx6: Don't remove MSI capability for i.MX7D/i.MX8M", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cf98ff362e873d9ecafdff1687b1458282914052", "submitter": { "id": 68324, "url": "http://patchwork.ozlabs.org/api/people/68324/?format=api", "name": "Richard Zhu", "email": "hongxing.zhu@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260331085252.1243108-1-hongxing.zhu@nxp.com/mbox/", "series": [ { "id": 498150, "url": "http://patchwork.ozlabs.org/api/series/498150/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498150", "date": "2026-03-31T08:52:52", "name": "[v3] PCI: imx6: Don't remove MSI capability for i.MX7D/i.MX8M", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/498150/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218003/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218003/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51542-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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"DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=4nlAq0sErq8j6lFkQ/QG1cZ7OEglX2oyCECUl3r9THg=;\n b=PByHfIoBvQstfeTz1fN3cbbA7miQQaHLtkQc78xpHrpmGWq7iio6y7rFUGpoJ5LSbEUnQatWhspD92UHIis4rhu3WJnJmoaIvXJDeryETf737VwxSaWGPEqPWOlf3tYFwdhpGO3k7OEO1PWPJ9uDvJwHe+bpm0dd2FVdObL2PxkjhW04W6mz6V8GOxEV0+BpNcTOf8i0MqFd2sadIbZ+r9BbviGRCMEI/mmXuqZ51X5/ZfMCn/vYP3OVZAwJ8XxInDMvyGhiNNxRl9qK4RMDvUB2BS+d7dMJvoDeV8enoHsNpHWUO5Nh1VXNyDyZRbsERbqRr3M0xgE7RwgKgiBePw==", "From": "Richard Zhu <hongxing.zhu@nxp.com>", "To": "frank.li@nxp.com,\n\tl.stach@pengutronix.de,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\trobh@kernel.org,\n\tbhelgaas@google.com,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com", "Cc": "linux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\timx@lists.linux.dev,\n\tlinux-kernel@vger.kernel.org,\n\tRichard Zhu <hongxing.zhu@nxp.com>,\n\tstable@vger.kernel.org", "Subject": "[PATCH v3] PCI: imx6: Don't remove MSI capability for i.MX7D/i.MX8M", "Date": "Tue, 31 Mar 2026 16:52:52 +0800", "Message-Id": "<20260331085252.1243108-1-hongxing.zhu@nxp.com>", "X-Mailer": "git-send-email 2.37.1", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SI2P153CA0003.APCP153.PROD.OUTLOOK.COM\n (2603:1096:4:140::20) To AS8PR04MB8833.eurprd04.prod.outlook.com\n (2603:10a6:20b:42c::19)", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": 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PeX+hVZ/eFwWbvB9TtgwJtNg8206lmermNQlldVL4gIv/pFhzPnA3X6vuAVFirSvtJoYqHG995qSD4ZiMksJi9NjIeeQFrJNuVwWRUw/wPE6Z+cCw6+/PYFDZmz+JBKf7t8GJ1OewDk1aqI4EeYleU7IOMN2WSewdxs8yqKFJ2uU41/zaTeOskOmcQ64Thc7iyiRYly1N5fu/WIAlzDWP+Ai3hxxsaOn20iVIBv+Y7NpTeoaWC916NShJH/xE+F74HdxE6x17NhImC99Iozv7c9yHMpb+ikgmhU+CH7AFsnTqY2RgMEEgjr9W2Q6aLUg5zqcFtKX/TBHbze97pqtH+6MT7MdfePKOpz3fXDfebzJ9aOU60Y4Du0lPhXDoaZVr8lJRD5q90HeyEk4qBpOybZhz6CNoNuHJeDBKWNR7A/eAKV8QRd6iVMF14YlL+AbRyGXhsZYww44qmBMPblTv2eXLwFBMDhKEK24y4i8T3KSy8znyUVWZAvHotTes57xesmUAnojL3sa6HGD0HZUYfPABo+uWYSIG3/QZKwM3wyq36mIRgoBtbZrurc3fO+8bEWCNGYvQKp8C/YRCa0NN8vbq66oJXSwx7vMxy8cHQBGgU7JRHctVLShaZGJczaljr/52NhEIMZqfhpv8yExA0U9a1XniZl1o2Rbt9r/zgHLcPDNWPfnzkLo5tvHFgscDMbXRLHL1b9sGpecsc6M7v+gQktIJj1C4O9mSbIADWpsrAAMFAPrg10riDRKPdpz9GbFYphqqjAXkxb1ZVS/y8PV+tVGgWK9CdwpNPOXTUs7qicil5TjrocwJAl6pmFmGP5Zr1q7/rv9UD35pmV6ps5EBreF+MT0kcsUcw13P0knxf/6dopthWbrxZyHX/O9AXV26cikOIkgk/J6moCEKGzV1+xZLSjcZGMt72DWb+DGTTpqOBVbH7F5UrKNncMJUtn+8GlrWE5NEWH0PxgF2m05CDGED6+qihijtaKAnnGel0rmbUSezY1pM3vu/4ujL0MVp7ZSo9YMV5kZ+6GZmgFYCRG/vKcOnGoiWf5O6fUQ4kyeXdpmBc2WwLtO56r/v0FMObXGt3jMe7Ie+cDrl4OwzJrmUlm2oGPWR9jV9dFVU1FDN0ghCB+Yqdgl9d/3QmQXMT6UiSdzLCyenByvqeHc3qYlrQzjhG0CbKzK8wARAZ4F1bB8ge479mnYyKDZOnGXLLyJeC0TruQH/ZC5Ys5V4OJcf2yppQTggGSrk3Dp8ugcZM7YkLqF1dgJ7rBacBbF2DSxAQhA5lMBtfDhy0zoYrBR5gAFWe6GTA4HYXdZ8h4wnvO9sHV1rC94GrPwrRzLN3GcqHq+LXd8HEpHeHR3aRX/2iiRNbDGHJnBh1fGl09KVmSB0o8Bc/KAg/n7iOuQXFJUlyO0/FG7moOCA5kavVNFJc9nuUolvJ3LZXVR+TJdlRzUhjoqT9ZYkdFRqwEuoQ3IR52HbYHvqTo9TbbjwjBCtpIzFCyMXUJ/HaBq1/PhgWeZhZIIQrazf1TknGqy5UFXSCvYM7bZCvloZBULL1O17zkKkIMSWkkIo0AVbkh/Dqkd/nQWrFKO7zvlqUTDkBIrTBILjINaRO/Kfy80Zr8q9WS7zdmO2+r7HPY96qYCYqIL40sElqjEgx3vnPM5ArfaNoCQEW8sfiN7YsKsGNLo5to04ypdrupy3Rq0SBxFqEU9D8OIxG4b7sLyaTfYENoPp6d+W69BmqZaIg==", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8df983d5-4bd5-442a-b83a-08de8f02b594", "X-MS-Exchange-CrossTenant-AuthSource": "AS8PR04MB8833.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Mar 2026 08:51:33.4494\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n +ngt9ggx4EsotuZDBWeDEu9pBD/mfxskOFZOYGk5nAzF0U02agE5edL8Rqkvp/5ND7gNx+tJ2Tso57E2i8NlAQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PAXPR04MB9220" }, "content": "The MSI trigger mechanism for endpoint devices connected to i.MX7D,\ni.MX8MM, and i.MX8MQ PCIe root complex ports depends on the MSI\ncapability register settings in the root complex. Removing the MSI\ncapability breaks MSI functionality for these endpoints.\n\nAdd keep_rp_msi_en flag to indicate platforms (i.MX7D, i.MX8MM, i.MX8MQ)\nthat should preserve the MSI capability during initialization.\n\nCc: stable@vger.kernel.org\nFixes: f5cd8a929c825 (\"PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller\")\nSuggested-by: Manivannan Sadhasivam <mani@kernel.org>\nSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>\n---\nv3 changes:\nUse a flag 'dw_pcie_rp::keep_rp_msi_en' to identify SoCs that require MSI\ncapability preservation, and skip the capability removal in\npcie-designware-host.c accordingly.\n\nv2 changes:\nCC stable tree.\n---\n drivers/pci/controller/dwc/pci-imx6.c | 7 +++++++\n drivers/pci/controller/dwc/pcie-designware-host.c | 2 +-\n drivers/pci/controller/dwc/pcie-designware.h | 1 +\n 3 files changed, 9 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c\nindex 20dafd2710a3..fde173770933 100644\n--- a/drivers/pci/controller/dwc/pci-imx6.c\n+++ b/drivers/pci/controller/dwc/pci-imx6.c\n@@ -117,6 +117,8 @@ enum imx_pcie_variants {\n #define IMX_PCIE_FLAG_HAS_LUT\t\t\tBIT(10)\n #define IMX_PCIE_FLAG_8GT_ECN_ERR051586\t\tBIT(11)\n #define IMX_PCIE_FLAG_SKIP_L23_READY\t\tBIT(12)\n+/* Preserve MSI capability for platforms that require it */\n+#define IMX_PCIE_FLAG_KEEP_MSI_CAP\t\tBIT(13)\n \n #define imx_check_flag(pci, val)\t(pci->drvdata->flags & val)\n \n@@ -1820,6 +1822,8 @@ static int imx_pcie_probe(struct platform_device *pdev)\n \t} else {\n \t\tif (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_SKIP_L23_READY))\n \t\t\tpci->pp.skip_l23_ready = true;\n+\t\tif (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_KEEP_MSI_CAP))\n+\t\t\tpci->pp.keep_rp_msi_en = true;\n \t\tpci->pp.use_atu_msg = true;\n \t\tret = dw_pcie_host_init(&pci->pp);\n \t\tif (ret < 0)\n@@ -1897,6 +1901,7 @@ static const struct imx_pcie_drvdata drvdata[] = {\n \t[IMX7D] = {\n \t\t.variant = IMX7D,\n \t\t.flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |\n+\t\t\t IMX_PCIE_FLAG_KEEP_MSI_CAP |\n \t\t\t IMX_PCIE_FLAG_HAS_APP_RESET |\n \t\t\t IMX_PCIE_FLAG_SKIP_L23_READY |\n \t\t\t IMX_PCIE_FLAG_HAS_PHY_RESET,\n@@ -1909,6 +1914,7 @@ static const struct imx_pcie_drvdata drvdata[] = {\n \t[IMX8MQ] = {\n \t\t.variant = IMX8MQ,\n \t\t.flags = IMX_PCIE_FLAG_HAS_APP_RESET |\n+\t\t\t IMX_PCIE_FLAG_KEEP_MSI_CAP |\n \t\t\t IMX_PCIE_FLAG_HAS_PHY_RESET |\n \t\t\t IMX_PCIE_FLAG_SUPPORTS_SUSPEND,\n \t\t.gpr = \"fsl,imx8mq-iomuxc-gpr\",\n@@ -1923,6 +1929,7 @@ static const struct imx_pcie_drvdata drvdata[] = {\n \t[IMX8MM] = {\n \t\t.variant = IMX8MM,\n \t\t.flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |\n+\t\t\t IMX_PCIE_FLAG_KEEP_MSI_CAP |\n \t\t\t IMX_PCIE_FLAG_HAS_PHYDRV |\n \t\t\t IMX_PCIE_FLAG_HAS_APP_RESET,\n \t\t.gpr = \"fsl,imx8mm-iomuxc-gpr\",\ndiff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c\nindex a74339982c24..7b5558561e15 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-host.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-host.c\n@@ -1171,7 +1171,7 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)\n \t * the MSI and MSI-X capabilities of the Root Port to allow the drivers\n \t * to fall back to INTx instead.\n \t */\n-\tif (pp->use_imsi_rx) {\n+\tif (pp->use_imsi_rx && !pp->keep_rp_msi_en) {\n \t\tdw_pcie_remove_capability(pci, PCI_CAP_ID_MSI);\n \t\tdw_pcie_remove_capability(pci, PCI_CAP_ID_MSIX);\n \t}\ndiff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h\nindex ae6389dd9caa..b12c5334552c 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.h\n+++ b/drivers/pci/controller/dwc/pcie-designware.h\n@@ -421,6 +421,7 @@ struct dw_pcie_host_ops {\n \n struct dw_pcie_rp {\n \tbool\t\t\tuse_imsi_rx:1;\n+\tbool\t\t\tkeep_rp_msi_en:1;\n \tbool\t\t\tcfg0_io_shared:1;\n \tu64\t\t\tcfg0_base;\n \tvoid __iomem\t\t*va_cfg0_base;\n", "prefixes": [ "v3" ] }