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GET /api/patches/2217973/?format=api
{ "id": 2217973, "url": "http://patchwork.ozlabs.org/api/patches/2217973/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/patch/20260331-upstream_pinctrl-v5-3-8994f59ff367@aspeedtech.com/", "project": { "id": 56, "url": "http://patchwork.ozlabs.org/api/projects/56/?format=api", "name": "OpenBMC development", "link_name": "openbmc", "list_id": "openbmc.lists.ozlabs.org", "list_email": "openbmc@lists.ozlabs.org", "web_url": "http://github.com/openbmc/", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331-upstream_pinctrl-v5-3-8994f59ff367@aspeedtech.com>", "list_archive_url": null, "date": "2026-03-31T07:31:18", "name": "[v5,3/3] pinctrl: aspeed: Add AST2700 SoC0 support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bf44d3fc19c99da6dc16a470c78be270d85d6b1a", "submitter": { "id": 80235, "url": "http://patchwork.ozlabs.org/api/people/80235/?format=api", "name": "Billy Tsai", "email": "billy_tsai@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/openbmc/patch/20260331-upstream_pinctrl-v5-3-8994f59ff367@aspeedtech.com/mbox/", "series": [ { "id": 498133, "url": "http://patchwork.ozlabs.org/api/series/498133/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/list/?series=498133", "date": "2026-03-31T07:31:15", "name": "pinctrl: aspeed: Add AST2700 SoC0 support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/498133/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217973/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217973/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <openbmc+bounces-1765-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "openbmc@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; helo=lists.ozlabs.org;\n envelope-from=openbmc+bounces-1765-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)", "lists.ozlabs.org;\n arc=none smtp.remote-ip=211.20.114.72", "lists.ozlabs.org;\n dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com", "lists.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com\n (client-ip=211.20.114.72; helo=twmbx01.aspeed.com;\n envelope-from=billy_tsai@aspeedtech.com; receiver=lists.ozlabs.org)" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org\n [IPv6:2404:9400:21b9:f100::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4flKb41cwJz1yGH\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 31 Mar 2026 18:32:48 +1100 (AEDT)", "from boromir.ozlabs.org (localhost [127.0.0.1])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4flKZL05Vdz2ygl;\n\tTue, 31 Mar 2026 18:32:10 +1100 (AEDT)", "from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 4flKZJ2BPlz2yhY;\n\tTue, 31 Mar 2026 18:32:08 +1100 (AEDT)", "from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 31 Mar\n 2026 15:31:46 +0800", "from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend\n Transport; Tue, 31 Mar 2026 15:31:46 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1774942329;\n\tcv=none;\n b=eqhPkESPnl7omejXNmJccqPkIsjx7v/R5DrRgQDwE3COm08F68xGgPKdkoCV5FJONzgXpEHvFMW4HalfmWKd95sKyXgl1QVpmvWhupfP3HXu1jWU/lWLumFcixyrxrWPm7jO1ZI+f7/7Ce6ZaxAIA5Ouwh7jcwUZ6w8SpSmW7M7vIKxEIvsjYE1yRs7CebdF/BWR1vFS9qAzOBaUWo4QOXWMHe+LcieTuu1sio3Y07skfR9U6bQ+ElvH3jfbXE8qgDj7DC+HTzrPSl7inJeZu3MF6lk+WDYEGcz0wjKoRNTgNaQIIbhEGKgGQbBYpK6623+ALbIIUv2+gW2sMEx9Ig==", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707;\n\tt=1774942329; c=relaxed/relaxed;\n\tbh=OsoICE2uB0Y+L6MtwqLweLXt2sz8YdWbYWn8gUfl1jc=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References:\n\t In-Reply-To:To:CC;\n b=gNL54tE6rGRme1UOm84hz/1lIFKLgb9xL3hAO8TaCzD3JDLtf5pvY4RelMzzQLQyaV/ahc9TR1HcaoxrGh74CfW6A/B2/MKDeYZt9XChMD507wqjDbCovtwXDdnoX/oTTjKV1Ow2Ixi6Q7IeyABfSN68qm6LbHzzTbGL3vlbKmyA/FiDZKHj/7urtBAMKQrO5aPoPV24swQaQBI03hlSsqZySrTGYS+/sBYklj5lcn0kN9Otz49e5LZlwJhf+0zpABPDr4WQE6MLph/G0QvmTN5NzcvJXRx/wJL0ibYfaCPo9t6HdIvmty2UJ79MzIOlezQMlGVVCrbvr+w4F0nu/Q==", "ARC-Authentication-Results": "i=1; lists.ozlabs.org;\n dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com;\n spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeed.com;\n envelope-from=billy_tsai@aspeedtech.com;\n receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com", "From": "Billy Tsai <billy_tsai@aspeedtech.com>", "Date": "Tue, 31 Mar 2026 15:31:18 +0800", "Subject": "[PATCH v5 3/3] pinctrl: aspeed: Add AST2700 SoC0 support", "X-Mailing-List": "openbmc@lists.ozlabs.org", "List-Id": "<openbmc.lists.ozlabs.org>", "List-Help": "<mailto:openbmc+help@lists.ozlabs.org>", "List-Owner": "<mailto:openbmc+owner@lists.ozlabs.org>", "List-Post": "<mailto:openbmc@lists.ozlabs.org>", "List-Subscribe": "<mailto:openbmc+subscribe@lists.ozlabs.org>,\n <mailto:openbmc+subscribe-digest@lists.ozlabs.org>,\n <mailto:openbmc+subscribe-nomail@lists.ozlabs.org>", "List-Unsubscribe": "<mailto:openbmc+unsubscribe@lists.ozlabs.org>", "Precedence": "list", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-ID": "<20260331-upstream_pinctrl-v5-3-8994f59ff367@aspeedtech.com>", "References": "<20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com>", "In-Reply-To": "<20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com>", "To": "Lee Jones <lee@kernel.org>, Rob Herring <robh@kernel.org>, \"Krzysztof\n Kozlowski\" <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, \"Joel\n Stanley\" <joel@jms.id.au>, Andrew Jeffery <andrew@codeconstruct.com.au>,\n\t\"Linus Walleij\" <linusw@kernel.org>, Billy Tsai <billy_tsai@aspeedtech.com>,\n\t\"Bartosz Golaszewski\" <brgl@kernel.org>, Ryan Chen <ryan_chen@aspeedtech.com>", "CC": "Andrew Jeffery <andrew@aj.id.au>, <devicetree@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>, <linux-aspeed@lists.ozlabs.org>,\n\t<linux-kernel@vger.kernel.org>, <openbmc@lists.ozlabs.org>,\n\t<linux-gpio@vger.kernel.org>, <linux-clk@vger.kernel.org>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1774942306; l=32567;\n i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id;\n bh=HG077U9u5x9WY8NwfGaSNNsie08HwZMlYJDUDn5neCo=;\n b=kbz5R1LvqTV6q15G6ZgH2z/WasUcIRU7ibzv8vTVwtJRgxCDI0Q5UnzmjvkPieP3t1xSdruf8\n 5/MZp8eW0X4AHWDw+m1z3bhau0K1hryk60CyHvYsInPiR/K45NwqBvz", "X-Developer-Key": "i=billy_tsai@aspeedtech.com; a=ed25519;\n pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ=", "X-Spam-Status": "No, score=0.8 required=5.0 tests=SPF_HELO_FAIL,SPF_PASS,\n\tUPPERCASE_50_75 autolearn=disabled version=4.0.1", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org" }, "content": "Add pinctrl support for the SoC0 instance of the ASPEED AST2700.\n\nAST2700 consists of two interconnected SoC instances, each with its own\npinctrl register block.\n\nThe SoC0 pinctrl hardware closely follows the design found in previous\nASPEED BMC generations, allowing the driver to build upon the common\nASPEED pinctrl infrastructure.\n\nSigned-off-by: Billy Tsai <billy_tsai@aspeedtech.com>\n---\n drivers/pinctrl/aspeed/Kconfig | 9 +\n drivers/pinctrl/aspeed/Makefile | 1 +\n drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c | 710 ++++++++++++++++++++++++\n 3 files changed, 720 insertions(+)", "diff": "diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig\nindex 1a4e5b9ed471..f9672cca891e 100644\n--- a/drivers/pinctrl/aspeed/Kconfig\n+++ b/drivers/pinctrl/aspeed/Kconfig\n@@ -31,3 +31,12 @@ config PINCTRL_ASPEED_G6\n \thelp\n \t Say Y here to enable pin controller support for Aspeed's 6th\n \t generation SoCs. GPIO is provided by a separate GPIO driver.\n+\n+config PINCTRL_ASPEED_G7_SOC0\n+\tbool \"Aspeed G7 SoC pin control\"\n+\tdepends on (ARCH_ASPEED || COMPILE_TEST) && OF\n+\tselect PINCTRL_ASPEED\n+\thelp\n+\t Say Y here to enable pin controller support for the SoC0 instance\n+\t of Aspeed's 7th generation SoCs. GPIO is provided by a separate\n+\t GPIO driver.\ndiff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile\nindex db2a7600ae2b..0de524ca2c72 100644\n--- a/drivers/pinctrl/aspeed/Makefile\n+++ b/drivers/pinctrl/aspeed/Makefile\n@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_ASPEED)\t+= pinctrl-aspeed.o pinmux-aspeed.o\n obj-$(CONFIG_PINCTRL_ASPEED_G4)\t+= pinctrl-aspeed-g4.o\n obj-$(CONFIG_PINCTRL_ASPEED_G5)\t+= pinctrl-aspeed-g5.o\n obj-$(CONFIG_PINCTRL_ASPEED_G6)\t+= pinctrl-aspeed-g6.o\n+obj-$(CONFIG_PINCTRL_ASPEED_G7_SOC0) += pinctrl-aspeed-g7-soc0.o\ndiff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c\nnew file mode 100644\nindex 000000000000..b1a09db65635\n--- /dev/null\n+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c\n@@ -0,0 +1,710 @@\n+// SPDX-License-Identifier: GPL-2.0\n+\n+#include <linux/bitops.h>\n+#include <linux/bits.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/of.h>\n+#include <linux/pinctrl/pinconf-generic.h>\n+#include <linux/pinctrl/pinconf.h>\n+#include <linux/pinctrl/pinctrl.h>\n+#include <linux/pinctrl/pinmux.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+\n+#include \"pinctrl-aspeed.h\"\n+#include \"pinmux-aspeed.h\"\n+#include \"../pinctrl-utils.h\"\n+\n+#define SCU200 0x200 /* System Reset Control #1 */\n+\n+#define SCU010 0x010 /* Hardware Strap Register */\n+#define SCU400 0x400 /* Multi-function Pin Control #1 */\n+#define SCU404 0x404 /* Multi-function Pin Control #2 */\n+#define SCU408 0x408 /* Multi-function Pin Control #3 */\n+#define SCU40C 0x40C /* Multi-function Pin Control #3 */\n+#define SCU410 0x410 /* USB Multi-function Control Register */\n+#define SCU414 0x414 /* VGA Function Control Register */\n+\n+#define SCU480 0x480 /* GPIO18A0 IO Control Register */\n+#define SCU484 0x484 /* GPIO18A1 IO Control Register */\n+#define SCU488 0x488 /* GPIO18A2 IO Control Register */\n+#define SCU48C 0x48c /* GPIO18A3 IO Control Register */\n+#define SCU490 0x490 /* GPIO18A4 IO Control Register */\n+#define SCU494 0x494 /* GPIO18A5 IO Control Register */\n+#define SCU498 0x498 /* GPIO18A6 IO Control Register */\n+#define SCU49C 0x49c /* GPIO18A7 IO Control Register */\n+#define SCU4A0 0x4A0 /* GPIO18B0 IO Control Register */\n+#define SCU4A4 0x4A4 /* GPIO18B1 IO Control Register */\n+#define SCU4A8 0x4A8 /* GPIO18B2 IO Control Register */\n+#define SCU4AC 0x4AC /* GPIO18B3 IO Control Register */\n+\n+enum {\n+\tAC14,\n+\tAE15,\n+\tAD14,\n+\tAE14,\n+\tAF14,\n+\tAB13,\n+\tAB14,\n+\tAF15,\n+\tAF13,\n+\tAC13,\n+\tAD13,\n+\tAE13,\n+\tJTAG_PORT,\n+\tPCIERC0_PERST,\n+\tPCIERC1_PERST,\n+\tPORTA_MODE,\n+\tPORTA_U2,\n+\tPORTB_MODE,\n+\tPORTB_U2,\n+\tPORTA_U2_PHY,\n+\tPORTB_U2_PHY,\n+\tPORTA_U3,\n+\tPORTB_U3,\n+\tPORTA_U3_PHY,\n+\tPORTB_U3_PHY,\n+};\n+\n+SIG_EXPR_LIST_DECL_SEMG(AC14, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 0));\n+SIG_EXPR_LIST_DECL_SESG(AC14, VB1CS, VB1, SIG_DESC_SET(SCU404, 0));\n+PIN_DECL_2(AC14, GPIO18A0, EMMCCLK, VB1CS);\n+\n+SIG_EXPR_LIST_DECL_SEMG(AE15, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 1));\n+SIG_EXPR_LIST_DECL_SESG(AE15, VB1CK, VB1, SIG_DESC_SET(SCU404, 1));\n+PIN_DECL_2(AE15, GPIO18A1, EMMCCMD, VB1CK);\n+\n+SIG_EXPR_LIST_DECL_SEMG(AD14, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 2));\n+SIG_EXPR_LIST_DECL_SESG(AD14, VB1MOSI, VB1, SIG_DESC_SET(SCU404, 2));\n+PIN_DECL_2(AD14, GPIO18A2, EMMCDAT0, VB1MOSI);\n+\n+SIG_EXPR_LIST_DECL_SEMG(AE14, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 3));\n+SIG_EXPR_LIST_DECL_SESG(AE14, VB1MISO, VB1, SIG_DESC_SET(SCU404, 3));\n+PIN_DECL_2(AE14, GPIO18A3, EMMCDAT1, VB1MISO);\n+\n+SIG_EXPR_LIST_DECL_SEMG(AF14, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 4));\n+PIN_DECL_1(AF14, GPIO18A4, EMMCDAT2);\n+\n+SIG_EXPR_LIST_DECL_SEMG(AB13, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 5));\n+PIN_DECL_1(AB13, GPIO18A5, EMMCDAT3);\n+\n+SIG_EXPR_LIST_DECL_SEMG(AB14, EMMCCDN, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 6));\n+SIG_EXPR_LIST_DECL_SESG(AB14, VB0CS, VB0, SIG_DESC_SET(SCU010, 17));\n+PIN_DECL_2(AB14, GPIO18A6, EMMCCDN, VB0CS);\n+\n+SIG_EXPR_LIST_DECL_SEMG(AF15, EMMCWPN, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 7));\n+SIG_EXPR_LIST_DECL_SESG(AF15, VB0CK, VB0, SIG_DESC_SET(SCU010, 17));\n+PIN_DECL_2(AF15, GPIO18A7, EMMCWPN, VB0CK);\n+\n+SIG_EXPR_LIST_DECL_SESG(AF13, TSPRSTN, TSPRSTN, SIG_DESC_SET(SCU010, 9));\n+SIG_EXPR_LIST_DECL_SEMG(AF13, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 8));\n+SIG_EXPR_LIST_DECL_SESG(AF13, VB0MOSI, VB0, SIG_DESC_SET(SCU010, 17));\n+PIN_DECL_3(AF13, GPIO18B0, TSPRSTN, EMMCDAT4, VB0MOSI);\n+\n+SIG_EXPR_LIST_DECL_SESG(AC13, UFSCLKI, UFSCLKI, SIG_DESC_SET(SCU010, 19));\n+SIG_EXPR_LIST_DECL_SEMG(AC13, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 9));\n+SIG_EXPR_LIST_DECL_SESG(AC13, VB0MISO, VB0, SIG_DESC_SET(SCU010, 17));\n+PIN_DECL_3(AC13, GPIO18B1, UFSCLKI, EMMCDAT5, VB0MISO);\n+\n+SIG_EXPR_LIST_DECL_SEMG(AD13, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 10));\n+SIG_EXPR_LIST_DECL_SESG(AD13, DDCCLK, VGADDC, SIG_DESC_SET(SCU404, 10));\n+PIN_DECL_2(AD13, GPIO18B2, EMMCDAT6, DDCCLK);\n+\n+SIG_EXPR_LIST_DECL_SEMG(AE13, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 11));\n+SIG_EXPR_LIST_DECL_SESG(AE13, DDCDAT, VGADDC, SIG_DESC_SET(SCU404, 11));\n+PIN_DECL_2(AE13, GPIO18B3, EMMCDAT7, DDCDAT);\n+\n+GROUP_DECL(EMMCG1, AC14, AE15, AD14);\n+GROUP_DECL(EMMCG4, AC14, AE15, AD14, AE14, AF14, AB13);\n+GROUP_DECL(EMMCG8, AC14, AE15, AD14, AE14, AF14, AB13, AF13, AC13, AD13, AE13);\n+GROUP_DECL(EMMCWPN, AF15);\n+GROUP_DECL(EMMCCDN, AB14);\n+FUNC_DECL_(EMMC, \"EMMCG1\", \"EMMCG4\", \"EMMCG8\", \"EMMCWPN\", \"EMMCCDN\");\n+\n+GROUP_DECL(VB1, AC14, AE15, AD14, AE14);\n+GROUP_DECL(VB0, AF15, AB14, AF13, AC13);\n+FUNC_DECL_2(VB, VB1, VB0);\n+\n+FUNC_GROUP_DECL(TSPRSTN, AF13);\n+\n+FUNC_GROUP_DECL(UFSCLKI, AC13);\n+\n+FUNC_GROUP_DECL(VGADDC, AD13, AE13);\n+\n+/* JTAG Port Selection */\n+#define JTAG_PORT_PSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x0, 0 }\n+#define JTAG_PORT_SSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x41, 0 }\n+#define JTAG_PORT_TSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x42, 0 }\n+#define JTAG_PORT_DDR_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x43, 0 }\n+#define JTAG_PORT_USB3A_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x44, 0 }\n+#define JTAG_PORT_USB3B_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x45, 0 }\n+#define JTAG_PORT_PCIEA_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x46, 0 }\n+#define JTAG_PORT_PCIEB_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x47, 0 }\n+#define JTAG_PORT_JTAGM0_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x8, 0 }\n+\n+SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPSP, JTAG0, JTAGPSP, JTAG_PORT_PSP_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGSSP, JTAG0, JTAGSSP, JTAG_PORT_SSP_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGTSP, JTAG0, JTAGTSP, JTAG_PORT_TSP_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGDDR, JTAG0, JTAGDDR, JTAG_PORT_DDR_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGUSB3A, JTAG0, JTAGUSB3A, JTAG_PORT_USB3A_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGUSB3B, JTAG0, JTAGUSB3B, JTAG_PORT_USB3B_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPCIEA, JTAG0, JTAGPCIEA, JTAG_PORT_PCIEA_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPCIEB, JTAG0, JTAGPCIEB, JTAG_PORT_PCIEB_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGM0, JTAG0, JTAGM0, JTAG_PORT_JTAGM0_DESC);\n+PIN_DECL_(JTAG_PORT, SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPSP), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGSSP),\n+\t SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGTSP), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGDDR),\n+\t SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGUSB3A), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGUSB3B),\n+\t SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPCIEA), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPCIEB),\n+\t SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGM0));\n+\n+GROUP_DECL(JTAG0, JTAG_PORT);\n+\n+FUNC_DECL_1(JTAGPSP, JTAG0);\n+FUNC_DECL_1(JTAGSSP, JTAG0);\n+FUNC_DECL_1(JTAGTSP, JTAG0);\n+FUNC_DECL_1(JTAGDDR, JTAG0);\n+FUNC_DECL_1(JTAGUSB3A, JTAG0);\n+FUNC_DECL_1(JTAGUSB3B, JTAG0);\n+FUNC_DECL_1(JTAGPCIEA, JTAG0);\n+FUNC_DECL_1(JTAGPCIEB, JTAG0);\n+FUNC_DECL_1(JTAGM0, JTAG0);\n+\n+/* PCIe Reset Control */\n+SIG_EXPR_LIST_DECL_SESG(PCIERC0_PERST, PCIERC0PERST, PCIERC0PERST, SIG_DESC_SET(SCU200, 21));\n+PIN_DECL_(PCIERC0_PERST, SIG_EXPR_LIST_PTR(PCIERC0_PERST, PCIERC0PERST));\n+FUNC_GROUP_DECL(PCIERC0PERST, PCIERC0_PERST);\n+\n+SIG_EXPR_LIST_DECL_SESG(PCIERC1_PERST, PCIERC1PERST, PCIERC1PERST, SIG_DESC_SET(SCU200, 19));\n+PIN_DECL_(PCIERC1_PERST, SIG_EXPR_LIST_PTR(PCIERC1_PERST, PCIERC1PERST));\n+FUNC_GROUP_DECL(PCIERC1PERST, PCIERC1_PERST);\n+\n+#define PORTA_MODE_HPD0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 0, 0 }\n+#define PORTA_MODE_D0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 1, 0 }\n+#define PORTA_MODE_H_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 2, 0 }\n+#define PORTA_MODE_HP_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 3, 0 }\n+\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AHPD0, USB2AH, USB2AHPD0, PORTA_MODE_HPD0_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AH, USB2AHAP, USB2AH, PORTA_MODE_H_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AHP, USB2AHAP, USB2AHP, PORTA_MODE_HP_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AD0, USB2AHAP, USB2AD0, PORTA_MODE_D0_DESC);\n+PIN_DECL_(PORTA_MODE, SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AHPD0),\n+\t SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AH), SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AHP),\n+\t SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AD0));\n+\n+#define PORTA_U2_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 0, 0 }\n+#define PORTA_U2_D1_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 1, 0 }\n+#define PORTA_U2_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 2, 0 }\n+#define PORTA_U2_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 3, 0 }\n+\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHD1, USB2A, USB2AXHD1, PORTA_U2_XHD_DESC,\n+\t\t\tSIG_DESC_SET(SCU410, 9));\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHPD1, USB2A, USB2AXHPD1, PORTA_U2_XHD_DESC,\n+\t\t\tSIG_DESC_CLEAR(SCU410, 9));\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXH, USB2AAP, USB2AXH, PORTA_U2_XH_DESC,\n+\t\t\tSIG_DESC_SET(SCU410, 9));\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHP, USB2AAP, USB2AXHP, PORTA_U2_XH_DESC,\n+\t\t\tSIG_DESC_CLEAR(SCU410, 9));\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXH2B, USB2ABP, USB2AXH2B, PORTA_U2_XH2E_DESC,\n+\t\t\tSIG_DESC_SET(SCU410, 9));\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHP2B, USB2ABP, USB2AXHP2B, PORTA_U2_XH2E_DESC,\n+\t\t\tSIG_DESC_CLEAR(SCU410, 9));\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AD1, USB2ADAP, USB2AD1, PORTA_U2_D1_DESC);\n+PIN_DECL_(PORTA_U2, SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHD1), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHPD1),\n+\t SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXH), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHP),\n+\t SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXH2B), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHP2B),\n+\t SIG_EXPR_LIST_PTR(PORTA_U2, USB2AD1));\n+\n+#define PORTB_MODE_HPD0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 0, 0 }\n+#define PORTB_MODE_D0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 1, 0 }\n+#define PORTB_MODE_H_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 2, 0 }\n+#define PORTB_MODE_HP_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 3, 0 }\n+\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BHPD0, USB2BH, USB2BHPD0, PORTB_MODE_HPD0_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BH, USB2BHBP, USB2BH, PORTB_MODE_H_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BHP, USB2BHBP, USB2BHP, PORTB_MODE_HP_DESC);\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BD0, USB2BHBP, USB2BD0, PORTB_MODE_D0_DESC);\n+PIN_DECL_(PORTB_MODE, SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BHPD0),\n+\t SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BH), SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BHP),\n+\t SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BD0));\n+\n+#define PORTB_U2_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 0, 0 }\n+#define PORTB_U2_D1_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 1, 0 }\n+#define PORTB_U2_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 2, 0 }\n+#define PORTB_U2_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 3, 0 }\n+\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHD1, USB2B, USB2BXHD1, PORTB_U2_XHD_DESC,\n+\t\t\tSIG_DESC_SET(SCU410, 10));\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHPD1, USB2B, USB2BXHPD1, PORTB_U2_XHD_DESC,\n+\t\t\tSIG_DESC_CLEAR(SCU410, 10));\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXH, USB2BBP, USB2BXH, PORTB_U2_XHD_DESC,\n+\t\t\tSIG_DESC_SET(SCU410, 10));\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHP, USB2BBP, USB2BXHP, PORTB_U2_XHD_DESC,\n+\t\t\tSIG_DESC_CLEAR(SCU410, 10));\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXH2A, USB2BAP, USB2BXH2A, PORTB_U2_XH2E_DESC,\n+\t\t\tSIG_DESC_SET(SCU410, 10));\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHP2A, USB2BAP, USB2BXHP2A, PORTB_U2_XH2E_DESC,\n+\t\t\tSIG_DESC_CLEAR(SCU410, 10));\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BD1, USB2BDBP, USB2BD1, PORTB_U2_D1_DESC);\n+PIN_DECL_(PORTB_U2, SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHD1), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHPD1),\n+\t SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXH), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHP),\n+\t SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXH2A), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHP2A),\n+\t SIG_EXPR_LIST_PTR(PORTB_U2, USB2BD1));\n+/*\n+ * USB2 virtual PHY pins.\n+ *\n+ * PORTA_U2_PHY and PORTB_U2_PHY are logical endpoints, not package pins.\n+ * They alias existing USB2 expressions so pin groups can model direct and\n+ * cross-coupled routing for host and mode paths.\n+ *\n+ * - USB2AAP/USB2ADAP/USB2AHAP: use PORTA_U2_PHY\n+ * - USB2ABP : use PORTB_U2_PHY\n+ * - USB2BBP/USB2BDBP/USB2BHBP: use PORTB_U2_PHY\n+ * - USB2BAP : use PORTA_U2_PHY\n+ *\n+ * They do not have any registers to configure this behaviour; the goal is\n+ * simply for the driver to prevent conflicting selections. For example,\n+ * selecting group USB2ABP and USB2BBP at the same time should not be\n+ * allowed.\n+ */\n+SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AXH, USB2AAP);\n+SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AXHP, USB2AAP);\n+SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2BXH2A, USB2BAP);\n+SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2BXHP2A, USB2BAP);\n+SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AD1, USB2ADAP);\n+SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AH, USB2AHAP);\n+SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AHP, USB2AHAP);\n+SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AD0, USB2AHAP);\n+PIN_DECL_(PORTA_U2_PHY, SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AXH),\n+\t SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AXHP), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2BXH2A),\n+\t SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2BXHP2A), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AD1),\n+\t SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AH), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AHP),\n+\t SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AD0));\n+\n+SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2AXH2B, USB2ABP);\n+SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2AXHP2B, USB2ABP);\n+SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BXH, USB2BBP);\n+SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BXHP, USB2BBP);\n+SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BD1, USB2BDBP);\n+SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BH, USB2BHBP);\n+SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BHP, USB2BHBP);\n+SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BD0, USB2BHBP);\n+PIN_DECL_(PORTB_U2_PHY, SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2AXH2B),\n+\t SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2AXHP2B), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BXH),\n+\t SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BXHP), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BD1),\n+\t SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BH), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BHP),\n+\t SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BD0));\n+\n+GROUP_DECL(USB2A, PORTA_U2);\n+GROUP_DECL(USB2AAP, PORTA_U2, PORTA_U2_PHY);\n+GROUP_DECL(USB2ABP, PORTA_U2, PORTB_U2_PHY);\n+GROUP_DECL(USB2ADAP, PORTA_U2, PORTA_U2_PHY);\n+GROUP_DECL(USB2AH, PORTA_MODE);\n+GROUP_DECL(USB2AHAP, PORTA_MODE, PORTA_U2_PHY);\n+\n+FUNC_DECL_1(USB2AXHD1, USB2A);\n+FUNC_DECL_1(USB2AXHPD1, USB2A);\n+FUNC_DECL_1(USB2AXH, USB2AAP);\n+FUNC_DECL_1(USB2AXHP, USB2AAP);\n+FUNC_DECL_1(USB2AXH2B, USB2ABP);\n+FUNC_DECL_1(USB2AXHP2B, USB2ABP);\n+FUNC_DECL_1(USB2AD1, USB2ADAP);\n+FUNC_DECL_1(USB2AHPD0, USB2AH);\n+FUNC_DECL_1(USB2AH, USB2AHAP);\n+FUNC_DECL_1(USB2AHP, USB2AHAP);\n+FUNC_DECL_1(USB2AD0, USB2AHAP);\n+\n+GROUP_DECL(USB2B, PORTB_U2);\n+GROUP_DECL(USB2BBP, PORTB_U2, PORTB_U2_PHY);\n+GROUP_DECL(USB2BAP, PORTB_U2, PORTA_U2_PHY);\n+GROUP_DECL(USB2BDBP, PORTB_U2, PORTB_U2_PHY);\n+GROUP_DECL(USB2BH, PORTB_MODE);\n+GROUP_DECL(USB2BHBP, PORTB_MODE, PORTB_U2_PHY);\n+\n+FUNC_DECL_1(USB2BXHD1, USB2B);\n+FUNC_DECL_1(USB2BXHPD1, USB2B);\n+FUNC_DECL_1(USB2BXH, USB2BBP);\n+FUNC_DECL_1(USB2BXHP, USB2BBP);\n+FUNC_DECL_1(USB2BXH2A, USB2BAP);\n+FUNC_DECL_1(USB2BXHP2A, USB2BAP);\n+FUNC_DECL_1(USB2BD1, USB2BDBP);\n+FUNC_DECL_1(USB2BHPD0, USB2BH);\n+FUNC_DECL_1(USB2BH, USB2BHBP);\n+FUNC_DECL_1(USB2BHP, USB2BHBP);\n+FUNC_DECL_1(USB2BD0, USB2BHBP);\n+\n+#define PORTA_U3_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 0, 0 }\n+#define PORTA_U3_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 2, 0 }\n+#define PORTA_U3_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 3, 0 }\n+\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHD, USB3A, USB3AXHD, PORTA_U3_XHD_DESC,\n+\t\t\tSIG_DESC_SET(SCU410, 9));\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHPD, USB3A, USB3AXHPD, PORTA_U3_XHD_DESC,\n+\t\t\tSIG_DESC_CLEAR(SCU410, 9));\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXH, USB3AAP, USB3AXH, PORTA_U3_XH_DESC,\n+\t\t\tSIG_DESC_SET(SCU410, 9));\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHP, USB3AAP, USB3AXHP, PORTA_U3_XH_DESC,\n+\t\t\tSIG_DESC_CLEAR(SCU410, 9));\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXH2B, USB3ABP, USB3AXH2B, PORTA_U3_XH2E_DESC,\n+\t\t\tSIG_DESC_SET(SCU410, 9));\n+SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHP2B, USB3ABP, USB3AXHP2B, PORTA_U3_XH2E_DESC,\n+\t\t\tSIG_DESC_CLEAR(SCU410, 9));\n+PIN_DECL_(PORTA_U3, SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHD), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHPD),\n+\t SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXH), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHP),\n+\t SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXH2B), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHP2B));\n+\n+#define PORTB_U3_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 0, 0 }\n+#define PORTB_U3_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 2, 0 }\n+#define PORTB_U3_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 3, 0 }\n+\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHD, USB3B, USB3BXHD, PORTB_U3_XHD_DESC,\n+\t\t\tSIG_DESC_SET(SCU410, 10));\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHPD, USB3B, USB3BXHPD, PORTB_U3_XHD_DESC,\n+\t\t\tSIG_DESC_CLEAR(SCU410, 10));\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXH, USB3BBP, USB3BXH, PORTB_U3_XH_DESC,\n+\t\t\tSIG_DESC_SET(SCU410, 10));\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHP, USB3BBP, USB3BXHP, PORTB_U3_XH_DESC,\n+\t\t\tSIG_DESC_CLEAR(SCU410, 10));\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXH2A, USB3BAP, USB3BXH2A, PORTB_U3_XH2E_DESC,\n+\t\t\tSIG_DESC_SET(SCU410, 10));\n+SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHP2A, USB3BAP, USB3BXHP2A, PORTB_U3_XH2E_DESC,\n+\t\t\tSIG_DESC_CLEAR(SCU410, 10));\n+PIN_DECL_(PORTB_U3, SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHD), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHPD),\n+\t SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXH), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHP),\n+\t SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXH2A), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHP2A));\n+\n+/*\n+ * USB3 virtual PHY pins.\n+ *\n+ * PORTA_U3_PHY and PORTB_U3_PHY are logical endpoints, not package pins.\n+ * They alias existing USB3 expressions so pin groups can model both direct and\n+ * cross-coupled routing to PHY A/B.\n+ *\n+ * - USB3AAP: PORTA_U3 + PORTA_U3_PHY (A -> PHY A)\n+ * - USB3ABP: PORTA_U3 + PORTB_U3_PHY (A -> PHY B)\n+ * - USB3BBP: PORTB_U3 + PORTB_U3_PHY (B -> PHY B)\n+ * - USB3BAP: PORTB_U3 + PORTA_U3_PHY (B -> PHY A)\n+ *\n+ * They do not have any registers to configure this behavior; the goal is\n+ * simply for the driver to prevent conflicting selections. For example,\n+ * selecting group USB3ABP and USB3BBP at the same time should not be\n+ * allowed.\n+ */\n+SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3AXH, USB3AAP);\n+SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3AXHP, USB3AAP);\n+SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3BXH2A, USB3BAP);\n+SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3BXHP2A, USB3BAP);\n+PIN_DECL_(PORTA_U3_PHY, SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3AXH),\n+\t SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3AXHP), SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3BXH2A),\n+\t SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3BXHP2A));\n+\n+SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3AXH2B, USB3ABP);\n+SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3AXHP2B, USB3ABP);\n+SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3BXH, USB3BBP);\n+SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3BXHP, USB3BBP);\n+PIN_DECL_(PORTB_U3_PHY, SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3AXH2B),\n+\t SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3AXHP2B), SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3BXH),\n+\t SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3BXHP));\n+\n+/* USB3A xHCI to vHUB */\n+GROUP_DECL(USB3A, PORTA_U3);\n+/* USB3A xHCI to USB3A PHY */\n+GROUP_DECL(USB3AAP, PORTA_U3, PORTA_U3_PHY);\n+/* USB3A xHCI to USB3B PHY */\n+GROUP_DECL(USB3ABP, PORTA_U3, PORTB_U3_PHY);\n+\n+FUNC_DECL_1(USB3AXHD, USB3A);\n+FUNC_DECL_1(USB3AXHPD, USB3A);\n+FUNC_DECL_1(USB3AXH, USB3AAP);\n+FUNC_DECL_1(USB3AXHP, USB3AAP);\n+FUNC_DECL_1(USB3AXH2B, USB3ABP);\n+FUNC_DECL_1(USB3AXHP2B, USB3ABP);\n+\n+/* USB3B xHCI to vHUB */\n+GROUP_DECL(USB3B, PORTB_U3);\n+/* USB3B xHCI to USB3A PHY */\n+GROUP_DECL(USB3BAP, PORTB_U3, PORTA_U3_PHY);\n+/* USB3B xHCI to USB3B PHY */\n+GROUP_DECL(USB3BBP, PORTB_U3, PORTB_U3_PHY);\n+\n+FUNC_DECL_1(USB3BXHD, USB3B);\n+FUNC_DECL_1(USB3BXHPD, USB3B);\n+FUNC_DECL_1(USB3BXH, USB3BBP);\n+FUNC_DECL_1(USB3BXHP, USB3BBP);\n+FUNC_DECL_1(USB3BXH2A, USB3BAP);\n+FUNC_DECL_1(USB3BXHP2A, USB3BAP);\n+\n+static const struct pinctrl_pin_desc aspeed_g7_soc0_pins[] = {\n+\tASPEED_PINCTRL_PIN(AC14),\n+\tASPEED_PINCTRL_PIN(AE15),\n+\tASPEED_PINCTRL_PIN(AD14),\n+\tASPEED_PINCTRL_PIN(AE14),\n+\tASPEED_PINCTRL_PIN(AF14),\n+\tASPEED_PINCTRL_PIN(AB13),\n+\tASPEED_PINCTRL_PIN(AB14),\n+\tASPEED_PINCTRL_PIN(AF15),\n+\tASPEED_PINCTRL_PIN(AF13),\n+\tASPEED_PINCTRL_PIN(AC13),\n+\tASPEED_PINCTRL_PIN(AD13),\n+\tASPEED_PINCTRL_PIN(AE13),\n+\tASPEED_PINCTRL_PIN(JTAG_PORT),\n+\tASPEED_PINCTRL_PIN(PCIERC0_PERST),\n+\tASPEED_PINCTRL_PIN(PCIERC1_PERST),\n+\tASPEED_PINCTRL_PIN(PORTA_MODE),\n+\tASPEED_PINCTRL_PIN(PORTA_U2),\n+\tASPEED_PINCTRL_PIN(PORTA_U3),\n+\tASPEED_PINCTRL_PIN(PORTA_U2_PHY),\n+\tASPEED_PINCTRL_PIN(PORTA_U3_PHY),\n+\tASPEED_PINCTRL_PIN(PORTB_MODE),\n+\tASPEED_PINCTRL_PIN(PORTB_U2),\n+\tASPEED_PINCTRL_PIN(PORTB_U3),\n+\tASPEED_PINCTRL_PIN(PORTB_U2_PHY),\n+\tASPEED_PINCTRL_PIN(PORTB_U3_PHY),\n+};\n+\n+static const struct aspeed_pin_group aspeed_g7_soc0_groups[] = {\n+\tASPEED_PINCTRL_GROUP(EMMCCDN),\n+\tASPEED_PINCTRL_GROUP(EMMCG1),\n+\tASPEED_PINCTRL_GROUP(EMMCG4),\n+\tASPEED_PINCTRL_GROUP(EMMCG8),\n+\tASPEED_PINCTRL_GROUP(EMMCWPN),\n+\tASPEED_PINCTRL_GROUP(TSPRSTN),\n+\tASPEED_PINCTRL_GROUP(UFSCLKI),\n+\tASPEED_PINCTRL_GROUP(VB0),\n+\tASPEED_PINCTRL_GROUP(VB1),\n+\tASPEED_PINCTRL_GROUP(VGADDC),\n+\t/* JTAG groups */\n+\tASPEED_PINCTRL_GROUP(JTAG0),\n+\t/* PCIE RC groups */\n+\tASPEED_PINCTRL_GROUP(PCIERC0PERST),\n+\tASPEED_PINCTRL_GROUP(PCIERC1PERST),\n+\t/* USB3A groups */\n+\tASPEED_PINCTRL_GROUP(USB3A),\n+\tASPEED_PINCTRL_GROUP(USB3AAP),\n+\tASPEED_PINCTRL_GROUP(USB3ABP),\n+\t/* USB3B groups */\n+\tASPEED_PINCTRL_GROUP(USB3B),\n+\tASPEED_PINCTRL_GROUP(USB3BAP),\n+\tASPEED_PINCTRL_GROUP(USB3BBP),\n+\t/* USB2A groups */\n+\tASPEED_PINCTRL_GROUP(USB2A),\n+\tASPEED_PINCTRL_GROUP(USB2AAP),\n+\tASPEED_PINCTRL_GROUP(USB2ABP),\n+\tASPEED_PINCTRL_GROUP(USB2ADAP),\n+\tASPEED_PINCTRL_GROUP(USB2AH),\n+\tASPEED_PINCTRL_GROUP(USB2AHAP),\n+\t/* USB2B groups */\n+\tASPEED_PINCTRL_GROUP(USB2B),\n+\tASPEED_PINCTRL_GROUP(USB2BAP),\n+\tASPEED_PINCTRL_GROUP(USB2BBP),\n+\tASPEED_PINCTRL_GROUP(USB2BDBP),\n+\tASPEED_PINCTRL_GROUP(USB2BH),\n+\tASPEED_PINCTRL_GROUP(USB2BHBP),\n+};\n+\n+static const struct aspeed_pin_function aspeed_g7_soc0_functions[] = {\n+\tASPEED_PINCTRL_FUNC(EMMC),\n+\tASPEED_PINCTRL_FUNC(TSPRSTN),\n+\tASPEED_PINCTRL_FUNC(UFSCLKI),\n+\tASPEED_PINCTRL_FUNC(VB),\n+\tASPEED_PINCTRL_FUNC(VGADDC),\n+\t/* JTAG functions */\n+\tASPEED_PINCTRL_FUNC(JTAGDDR),\n+\tASPEED_PINCTRL_FUNC(JTAGM0),\n+\tASPEED_PINCTRL_FUNC(JTAGPCIEA),\n+\tASPEED_PINCTRL_FUNC(JTAGPCIEB),\n+\tASPEED_PINCTRL_FUNC(JTAGPSP),\n+\tASPEED_PINCTRL_FUNC(JTAGSSP),\n+\tASPEED_PINCTRL_FUNC(JTAGTSP),\n+\tASPEED_PINCTRL_FUNC(JTAGUSB3A),\n+\tASPEED_PINCTRL_FUNC(JTAGUSB3B),\n+\t/* PCIE RC functions */\n+\tASPEED_PINCTRL_FUNC(PCIERC0PERST),\n+\tASPEED_PINCTRL_FUNC(PCIERC1PERST),\n+\t/* USB3A functions */\n+\tASPEED_PINCTRL_FUNC(USB3AXH),\n+\tASPEED_PINCTRL_FUNC(USB3AXH2B),\n+\tASPEED_PINCTRL_FUNC(USB3AXHD),\n+\tASPEED_PINCTRL_FUNC(USB3AXHP),\n+\tASPEED_PINCTRL_FUNC(USB3AXHP2B),\n+\tASPEED_PINCTRL_FUNC(USB3AXHPD),\n+\t/* USB3B functions */\n+\tASPEED_PINCTRL_FUNC(USB3BXH),\n+\tASPEED_PINCTRL_FUNC(USB3BXH2A),\n+\tASPEED_PINCTRL_FUNC(USB3BXHD),\n+\tASPEED_PINCTRL_FUNC(USB3BXHP),\n+\tASPEED_PINCTRL_FUNC(USB3BXHP2A),\n+\tASPEED_PINCTRL_FUNC(USB3BXHPD),\n+\t/* USB2A functions */\n+\tASPEED_PINCTRL_FUNC(USB2AD0),\n+\tASPEED_PINCTRL_FUNC(USB2AD1),\n+\tASPEED_PINCTRL_FUNC(USB2AH),\n+\tASPEED_PINCTRL_FUNC(USB2AHP),\n+\tASPEED_PINCTRL_FUNC(USB2AHPD0),\n+\tASPEED_PINCTRL_FUNC(USB2AXH),\n+\tASPEED_PINCTRL_FUNC(USB2AXH2B),\n+\tASPEED_PINCTRL_FUNC(USB2AXHD1),\n+\tASPEED_PINCTRL_FUNC(USB2AXHP),\n+\tASPEED_PINCTRL_FUNC(USB2AXHP2B),\n+\tASPEED_PINCTRL_FUNC(USB2AXHPD1),\n+\t/* USB2B functions */\n+\tASPEED_PINCTRL_FUNC(USB2BD0),\n+\tASPEED_PINCTRL_FUNC(USB2BD1),\n+\tASPEED_PINCTRL_FUNC(USB2BH),\n+\tASPEED_PINCTRL_FUNC(USB2BHP),\n+\tASPEED_PINCTRL_FUNC(USB2BHPD0),\n+\tASPEED_PINCTRL_FUNC(USB2BXH),\n+\tASPEED_PINCTRL_FUNC(USB2BXH2A),\n+\tASPEED_PINCTRL_FUNC(USB2BXHD1),\n+\tASPEED_PINCTRL_FUNC(USB2BXHP),\n+\tASPEED_PINCTRL_FUNC(USB2BXHP2A),\n+\tASPEED_PINCTRL_FUNC(USB2BXHPD1),\n+};\n+\n+static const struct pinmux_ops aspeed_g7_soc0_pinmux_ops = {\n+\t.get_functions_count = aspeed_pinmux_get_fn_count,\n+\t.get_function_name = aspeed_pinmux_get_fn_name,\n+\t.get_function_groups = aspeed_pinmux_get_fn_groups,\n+\t.set_mux = aspeed_pinmux_set_mux,\n+\t.gpio_request_enable = aspeed_gpio_request_enable,\n+\t.strict = true,\n+};\n+\n+static const struct pinctrl_ops aspeed_g7_soc0_pinctrl_ops = {\n+\t.get_groups_count = aspeed_pinctrl_get_groups_count,\n+\t.get_group_name = aspeed_pinctrl_get_group_name,\n+\t.get_group_pins = aspeed_pinctrl_get_group_pins,\n+\t.pin_dbg_show = aspeed_pinctrl_pin_dbg_show,\n+\t.dt_node_to_map = pinconf_generic_dt_node_to_map_all,\n+\t.dt_free_map = pinctrl_utils_free_map,\n+};\n+\n+static const struct pinconf_ops aspeed_g7_soc0_pinconf_ops = {\n+\t.is_generic = true,\n+\t.pin_config_get = aspeed_pin_config_get,\n+\t.pin_config_set = aspeed_pin_config_set,\n+\t.pin_config_group_get = aspeed_pin_config_group_get,\n+\t.pin_config_group_set = aspeed_pin_config_group_set,\n+};\n+\n+/* pinctrl_desc */\n+static const struct pinctrl_desc aspeed_g7_soc0_pinctrl_desc = {\n+\t.name = \"aspeed-g7-soc0-pinctrl\",\n+\t.pins = aspeed_g7_soc0_pins,\n+\t.npins = ARRAY_SIZE(aspeed_g7_soc0_pins),\n+\t.pctlops = &aspeed_g7_soc0_pinctrl_ops,\n+\t.pmxops = &aspeed_g7_soc0_pinmux_ops,\n+\t.confops = &aspeed_g7_soc0_pinconf_ops,\n+};\n+\n+static const struct aspeed_pin_config aspeed_g7_soc0_configs[] = {\n+\t/* GPIO18A */\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, { AC14, AC14 }, SCU480, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, { AE15, AE15 }, SCU484, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, { AD14, AD14 }, SCU488, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, { AE14, AE14 }, SCU48C, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, { AF14, AF14 }, SCU490, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, { AB13, AB13 }, SCU494, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, { AB14, AB14 }, SCU498, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, { AF15, AF15 }, SCU49C, GENMASK(3, 0) },\n+\t/* GPIO18B */\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, { AF13, AF13 }, SCU4A0, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, { AC13, AC13 }, SCU4A4, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, { AD13, AD13 }, SCU4A8, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, { AE13, AE13 }, SCU4AC, GENMASK(3, 0) },\n+};\n+\n+static const struct aspeed_pin_config_map aspeed_g7_soc0_pin_config_map[] = {\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 3, 0, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 6, 1, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 8, 2, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 11, 3, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 16, 4, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 18, 5, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 20, 6, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 23, 7, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 30, 8, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 32, 9, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 33, 10, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 35, 11, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 37, 12, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 38, 13, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 39, 14, GENMASK(3, 0) },\n+\t{ PIN_CONFIG_DRIVE_STRENGTH, 41, 15, GENMASK(3, 0) },\n+\n+};\n+\n+static int aspeed_g7_soc0_sig_expr_set(struct aspeed_pinmux_data *ctx,\n+\t\t\t\t const struct aspeed_sig_expr *expr, bool enable)\n+{\n+\tint ret;\n+\tint i;\n+\n+\tfor (i = 0; i < expr->ndescs; i++) {\n+\t\tconst struct aspeed_sig_desc *desc = &expr->descs[i];\n+\t\tu32 pattern = enable ? desc->enable : desc->disable;\n+\t\tu32 val = (pattern << __ffs(desc->mask));\n+\n+\t\tif (!ctx->maps[desc->ip])\n+\t\t\treturn -ENODEV;\n+\n+\t\tWARN_ON_ONCE(desc->ip != ASPEED_IP_SCU);\n+\n+\t\tret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,\n+\t\t\t\t\t desc->mask, val);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tret = aspeed_sig_expr_eval(ctx, expr, enable);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn ret ? 0 : -EPERM;\n+}\n+\n+static const struct aspeed_pinmux_ops aspeed_g7_soc0_ops = {\n+\t.set = aspeed_g7_soc0_sig_expr_set,\n+};\n+\n+static struct aspeed_pinctrl_data aspeed_g7_soc0_pinctrl_data = {\n+\t.pins = aspeed_g7_soc0_pins,\n+\t.npins = ARRAY_SIZE(aspeed_g7_soc0_pins),\n+\t.pinmux = {\n+\t\t.ops = &aspeed_g7_soc0_ops,\n+\t\t.groups = aspeed_g7_soc0_groups,\n+\t\t.ngroups = ARRAY_SIZE(aspeed_g7_soc0_groups),\n+\t\t.functions = aspeed_g7_soc0_functions,\n+\t\t.nfunctions = ARRAY_SIZE(aspeed_g7_soc0_functions),\n+\t},\n+\t.configs = aspeed_g7_soc0_configs,\n+\t.nconfigs = ARRAY_SIZE(aspeed_g7_soc0_configs),\n+\t.confmaps = aspeed_g7_soc0_pin_config_map,\n+\t.nconfmaps = ARRAY_SIZE(aspeed_g7_soc0_pin_config_map),\n+};\n+\n+static int aspeed_g7_soc0_pinctrl_probe(struct platform_device *pdev)\n+{\n+\treturn aspeed_pinctrl_probe(pdev, &aspeed_g7_soc0_pinctrl_desc,\n+\t\t\t\t &aspeed_g7_soc0_pinctrl_data);\n+}\n+\n+static const struct of_device_id aspeed_g7_soc0_pinctrl_match[] = {\n+\t{ .compatible = \"aspeed,ast2700-soc0-pinctrl\" },\n+\t{}\n+};\n+MODULE_DEVICE_TABLE(of, aspeed_g7_soc0_pinctrl_match);\n+\n+static struct platform_driver aspeed_g7_soc0_pinctrl_driver = {\n+\t.probe = aspeed_g7_soc0_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"aspeed-g7-soc0-pinctrl\",\n+\t\t.of_match_table = aspeed_g7_soc0_pinctrl_match,\n+\t\t.suppress_bind_attrs = true,\n+\t},\n+};\n+\n+static int __init aspeed_g7_soc0_pinctrl_init(void)\n+{\n+\treturn platform_driver_register(&aspeed_g7_soc0_pinctrl_driver);\n+}\n+arch_initcall(aspeed_g7_soc0_pinctrl_init);\n", "prefixes": [ "v5", "3/3" ] }