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GET /api/patches/2217970/?format=api
{ "id": 2217970, "url": "http://patchwork.ozlabs.org/api/patches/2217970/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20260331-upstream_pinctrl-v5-2-8994f59ff367@aspeedtech.com/", "project": { "id": 57, "url": "http://patchwork.ozlabs.org/api/projects/57/?format=api", "name": "Linux ASPEED SoC development", "link_name": "linux-aspeed", "list_id": "linux-aspeed.lists.ozlabs.org", "list_email": "linux-aspeed@lists.ozlabs.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331-upstream_pinctrl-v5-2-8994f59ff367@aspeedtech.com>", "list_archive_url": null, "date": "2026-03-31T07:31:17", "name": "[v5,2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe AST2700 SCU0", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "808938a5a478d7b17fcc187f3361e08da1e8e694", "submitter": { "id": 80235, "url": "http://patchwork.ozlabs.org/api/people/80235/?format=api", "name": "Billy Tsai", "email": "billy_tsai@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20260331-upstream_pinctrl-v5-2-8994f59ff367@aspeedtech.com/mbox/", "series": [ { "id": 498132, "url": "http://patchwork.ozlabs.org/api/series/498132/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/list/?series=498132", "date": "2026-03-31T07:31:15", "name": "pinctrl: aspeed: Add AST2700 SoC0 support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/498132/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217970/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217970/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-aspeed+bounces-3818-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; helo=lists.ozlabs.org;\n envelope-from=linux-aspeed+bounces-3818-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)", "lists.ozlabs.org;\n arc=none smtp.remote-ip=211.20.114.72", "lists.ozlabs.org;\n dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com", "lists.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com\n (client-ip=211.20.114.72; helo=twmbx01.aspeed.com;\n envelope-from=billy_tsai@aspeedtech.com; receiver=lists.ozlabs.org)" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org\n [IPv6:2404:9400:21b9:f100::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4flKZm26gtz1yGH\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 31 Mar 2026 18:32:32 +1100 (AEDT)", "from boromir.ozlabs.org (localhost [127.0.0.1])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4flKZJ0swtz2yhV;\n\tTue, 31 Mar 2026 18:32:08 +1100 (AEDT)", "from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 4flKZH2kX2z2ygl;\n\tTue, 31 Mar 2026 18:32:07 +1100 (AEDT)", "from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 31 Mar\n 2026 15:31:46 +0800", "from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend\n Transport; Tue, 31 Mar 2026 15:31:46 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1774942328;\n\tcv=none;\n b=JPSq/JziNzcx9rByZRQkY/NtZ6Hwkv1XxqC95jvn6VKnHbfcXDTJ7D1r9xlDNgw2+SN8gc8ng9RB5hQT8nppLGk+ftGen9sq9pbZrLEVV7H+BHd/yglUltrq07vQKMd23IzpuunvKs6/rd4BpQK1rLPYa+BH9egbBFRgN6ed8zyG1gQF8dspvigreqyUkr21JYLgVFRSTuBjftMjOAW2+3vRLqCUvdl2YUILjvyw09TvlLwL/TAvFMG75xwgsXawV8gSMYA04wvnyNt5wAX1fUe8oMdJo1PIYdNvjW8pTgKAMN0jxH9U6dxKExaQsj+WqgN1i8vCU7mGQVJuVTcAKw==", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707;\n\tt=1774942328; c=relaxed/relaxed;\n\tbh=9b68g3MrncOCCbFm09UJ1DjbJGnN2x1rFED6IrGOwEE=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References:\n\t In-Reply-To:To:CC;\n b=E5Y6lr5mk/f1J8s2uIl4xcX8lkXHqxG6KWThYBHkniLJamgjtHyVL1jbhtSDFJUYfXP9jlTwAzksMYFWfqU34dxLXiGgKCdrvEQQSTIXDhDFvzDYm68VlL0KMAjHoscBzWQodRqlUK4PUvoxakEpvAOHf5DOCdoEhA6hnMSp6QjH6Vu/CoGbz2DNvMMECn4DyLu+t4DQTCBYVtk0UGqC231lQXNazTg/SzlJBXplYeaPNkEhuy/+R8dnm5oJ2W7Y+LpZ05IP+A6XRkKf/tQ0NuIM6fGEPomyTdnQHtgnh4vi95bDQGknf3ACRbdos75lS5yRHIEcqW8WIcNNGFsbHA==", "ARC-Authentication-Results": "i=1; lists.ozlabs.org;\n dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com;\n spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeed.com;\n envelope-from=billy_tsai@aspeedtech.com;\n receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com", "From": "Billy Tsai <billy_tsai@aspeedtech.com>", "Date": "Tue, 31 Mar 2026 15:31:17 +0800", "Subject": "[PATCH v5 2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe\n AST2700 SCU0", "X-Mailing-List": "linux-aspeed@lists.ozlabs.org", "List-Id": "<linux-aspeed.lists.ozlabs.org>", "List-Help": "<mailto:linux-aspeed+help@lists.ozlabs.org>", "List-Owner": "<mailto:linux-aspeed+owner@lists.ozlabs.org>", "List-Post": "<mailto:linux-aspeed@lists.ozlabs.org>", "List-Archive": "<https://lore.kernel.org/linux-aspeed/>,\n <https://lists.ozlabs.org/pipermail/linux-aspeed/>", "List-Subscribe": "<mailto:linux-aspeed+subscribe@lists.ozlabs.org>,\n <mailto:linux-aspeed+subscribe-digest@lists.ozlabs.org>,\n <mailto:linux-aspeed+subscribe-nomail@lists.ozlabs.org>", "List-Unsubscribe": "<mailto:linux-aspeed+unsubscribe@lists.ozlabs.org>", "Precedence": "list", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-ID": "<20260331-upstream_pinctrl-v5-2-8994f59ff367@aspeedtech.com>", "References": "<20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com>", "In-Reply-To": "<20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com>", "To": "Lee Jones <lee@kernel.org>, Rob Herring <robh@kernel.org>, \"Krzysztof\n Kozlowski\" <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, \"Joel\n Stanley\" <joel@jms.id.au>, Andrew Jeffery <andrew@codeconstruct.com.au>,\n\t\"Linus Walleij\" <linusw@kernel.org>, Billy Tsai <billy_tsai@aspeedtech.com>,\n\t\"Bartosz Golaszewski\" <brgl@kernel.org>, Ryan Chen <ryan_chen@aspeedtech.com>", "CC": "Andrew Jeffery <andrew@aj.id.au>, <devicetree@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>, <linux-aspeed@lists.ozlabs.org>,\n\t<linux-kernel@vger.kernel.org>, <openbmc@lists.ozlabs.org>,\n\t<linux-gpio@vger.kernel.org>, <linux-clk@vger.kernel.org>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1774942306; l=5430;\n i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id;\n bh=e8lq+jY2HQ8zkEhRGvXd0EB5NimGHYNLx+RsdCMXlGY=;\n b=U6PvlIaG6lQgky0Cd+1D873t79J5YadAVzAkpw/hYzf/1pEAbOoJr6JobnLw7SGZf/5sZvDw7\n om5Tqd2kJM0Ckvw4eClyvtL0bhcJ/KOtvDn2QucSBCLPPxW4FNg3bND", "X-Developer-Key": "i=billy_tsai@aspeedtech.com; a=ed25519;\n pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ=", "X-Spam-Status": "No, score=0.0 required=5.0 tests=SPF_HELO_FAIL,SPF_PASS\n\tautolearn=disabled version=4.0.1", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org" }, "content": "AST2700 consists of two interconnected SoC instances, each with its own\nSystem Control Unit (SCU). The SCU0 provides pin control, interrupt\ncontrollers, clocks, resets, and address-space mappings for the\nSecondary and Tertiary Service Processors (SSP and TSP).\n\nDescribe the SSP/TSP address mappings using the standard\nmemory-region and memory-region-names properties.\n\nDisallow legacy child nodes that are not present on AST2700, including\np2a-control and smp-memram. The latter is unnecessary as software can\naccess the scratch registers via the SCU syscon.\n\nAlso allow the AST2700 SoC0 pin controller to be described as a child\nnode of the SCU0, and add an example illustrating the SCU0 layout,\nincluding reserved-memory, interrupt controllers, and pinctrl.\n\nSigned-off-by: Billy Tsai <billy_tsai@aspeedtech.com>\n---\n .../bindings/mfd/aspeed,ast2x00-scu.yaml | 117 +++++++++++++++++++++\n 1 file changed, 117 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml\nindex a87f31fce019..86d51389689c 100644\n--- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml\n+++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml\n@@ -46,6 +46,9 @@ properties:\n '#reset-cells':\n const: 1\n \n+ memory-region: true\n+ memory-region-names: true\n+\n patternProperties:\n '^p2a-control@[0-9a-f]+$':\n description: >\n@@ -87,6 +90,7 @@ patternProperties:\n - aspeed,ast2400-pinctrl\n - aspeed,ast2500-pinctrl\n - aspeed,ast2600-pinctrl\n+ - aspeed,ast2700-soc0-pinctrl\n \n required:\n - compatible\n@@ -156,6 +160,42 @@ required:\n - '#clock-cells'\n - '#reset-cells'\n \n+allOf:\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ anyOf:\n+ - const: aspeed,ast2700-scu0\n+ - const: aspeed,ast2700-scu1\n+ then:\n+ patternProperties:\n+ '^p2a-control@[0-9a-f]+$': false\n+ '^smp-memram@[0-9a-f]+$': false\n+\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ const: aspeed,ast2700-scu0\n+ then:\n+ properties:\n+ memory-region:\n+ items:\n+ - description: Region mapped through the first SSP address window.\n+ - description: Region mapped through the second SSP address window.\n+ - description: Region mapped through the TSP address window.\n+\n+ memory-region-names:\n+ items:\n+ - const: ssp-0\n+ - const: ssp-1\n+ - const: tsp\n+ else:\n+ properties:\n+ memory-region: false\n+ memory-region-names: false\n+\n additionalProperties: false\n \n examples:\n@@ -180,4 +220,81 @@ examples:\n reg = <0x7c 0x4>, <0x150 0x8>;\n };\n };\n+\n+ - |\n+ / {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ reserved-memory {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+ ranges;\n+\n+ ssp_region_0: memory@400000000 {\n+ reg = <0x4 0x00000000 0x0 0x01000000>;\n+ no-map;\n+ };\n+\n+ ssp_region_1: memory@401000000 {\n+ reg = <0x4 0x01000000 0x0 0x01000000>;\n+ no-map;\n+ };\n+\n+ tsp_region: memory@402000000 {\n+ reg = <0x4 0x02000000 0x0 0x01000000>;\n+ no-map;\n+ };\n+ };\n+\n+ bus {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ syscon@12c02000 {\n+ compatible = \"aspeed,ast2700-scu0\", \"syscon\", \"simple-mfd\";\n+ reg = <0 0x12c02000 0 0x1000>;\n+ ranges = <0x0 0x0 0x12c02000 0x1000>;\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ #clock-cells = <1>;\n+ #reset-cells = <1>;\n+\n+ memory-region = <&ssp_region_0>, <&ssp_region_1>,\n+ <&tsp_region>;\n+ memory-region-names = \"ssp-0\", \"ssp-1\", \"tsp\";\n+\n+ silicon-id@0 {\n+ compatible = \"aspeed,ast2700-silicon-id\", \"aspeed,silicon-id\";\n+ reg = <0x0 0x4>;\n+ };\n+\n+ interrupt-controller@1b0 {\n+ compatible = \"aspeed,ast2700-scu-ic0\";\n+ reg = <0x1b0 0x4>;\n+ #interrupt-cells = <1>;\n+ interrupts-extended = <&intc0 97>;\n+ interrupt-controller;\n+ };\n+\n+ interrupt-controller@1e0 {\n+ compatible = \"aspeed,ast2700-scu-ic1\";\n+ reg = <0x1e0 0x4>;\n+ #interrupt-cells = <1>;\n+ interrupts-extended = <&intc0 98>;\n+ interrupt-controller;\n+ };\n+\n+ pinctrl@400 {\n+ compatible = \"aspeed,ast2700-soc0-pinctrl\";\n+ reg = <0x400 0x318>;\n+ emmc-state {\n+ function = \"EMMC\";\n+ groups = \"EMMCG1\";\n+ };\n+ };\n+ };\n+ };\n+ };\n+\n ...\n", "prefixes": [ "v5", "2/3" ] }