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GET /api/patches/2217962/?format=api
{ "id": 2217962, "url": "http://patchwork.ozlabs.org/api/patches/2217962/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260331065831.423094-1-pbonzini@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331065831.423094-1-pbonzini@redhat.com>", "list_archive_url": null, "date": "2026-03-31T06:58:31", "name": "target/i386/tcg: fix decoding of MOVBE and CRC32 in 16-bit mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "62895472068a5796893f364a13e7fc589fae2283", "submitter": { "id": 2701, "url": "http://patchwork.ozlabs.org/api/people/2701/?format=api", "name": "Paolo Bonzini", "email": "pbonzini@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260331065831.423094-1-pbonzini@redhat.com/mbox/", "series": [ { "id": 498128, "url": "http://patchwork.ozlabs.org/api/series/498128/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498128", "date": "2026-03-31T06:58:31", "name": "target/i386/tcg: fix decoding of MOVBE and CRC32 in 16-bit mode", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498128/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217962/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217962/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=Ckye4ylC;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=google header.b=aeKUya/t;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Both MOVBE and (for 0xF1) CRC32\ntake Gv, Ev or Mv operands. In 16-bit mode therefore the\noperand is of 16-bit size without prefix and 32-bit mode\nwith 0x66 (the data size override).\n\nFor example, with NASM you get:\n\n bits 16\n 67 0F 38 F0 02 movbe ax, [edx]\n 66 67 0F 38 F0 02 movbe eax, [edx]\n\n 67 F2 0F 38 F0 02 crc32 ax, word [edx]\n 66 67 F2 0F 38 F0 02 crc32 eax, dword [edx]\n\nversus\n\n bits 32\n 66 0F 38 F0 02 movbe ax, [edx]\n 0F 38 F0 02 movbe eax, [edx]\n\n 66 F2 0F 38 F1 02 crc32 eax, word [edx]\n F2 0F 38 F1 02 crc32 eax, dword [edx]\n\nThe instruction is listed correctly in the APX documentation\nas \"SCALABLE\" (which means it has v-size operands).\n\nCc: qemu-stable@nongnu.org\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>\n---\n target/i386/tcg/decode-new.c.inc | 16 ++++++++++------\n 1 file changed, 10 insertions(+), 6 deletions(-)", "diff": "diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc\nindex bc105aab9ea..c8b5bd6ad26 100644\n--- a/target/i386/tcg/decode-new.c.inc\n+++ b/target/i386/tcg/decode-new.c.inc\n@@ -875,19 +875,23 @@ static const X86OpEntry opcodes_0F38_00toEF[240] = {\n \n /* five rows for no prefix, 66, F3, F2, 66+F2 */\n static const X86OpEntry opcodes_0F38_F0toFF[16][5] = {\n+ /*\n+ * MOVBE and CRC32 are incorrectly listed as always doing 32-bit operation\n+ * without prefix and 16-bit operation with 0x66.\n+ */\n [0] = {\n- X86_OP_ENTRYwr(MOVBE, G,y, M,y, cpuid(MOVBE)),\n- X86_OP_ENTRYwr(MOVBE, G,w, M,w, cpuid(MOVBE)),\n+ X86_OP_ENTRYwr(MOVBE, G,v, M,v, cpuid(MOVBE)),\n+ X86_OP_ENTRYwr(MOVBE, G,v, M,v, cpuid(MOVBE)),\n {},\n X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)),\n X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)),\n },\n [1] = {\n- X86_OP_ENTRYwr(MOVBE, M,y, G,y, cpuid(MOVBE)),\n- X86_OP_ENTRYwr(MOVBE, M,w, G,w, cpuid(MOVBE)),\n+ X86_OP_ENTRYwr(MOVBE, M,v, G,v, cpuid(MOVBE)),\n+ X86_OP_ENTRYwr(MOVBE, M,v, G,v, cpuid(MOVBE)),\n {},\n- X86_OP_ENTRY2(CRC32, G,d, E,y, cpuid(SSE42)),\n- X86_OP_ENTRY2(CRC32, G,d, E,w, cpuid(SSE42)),\n+ X86_OP_ENTRY2(CRC32, G,d, E,v, cpuid(SSE42)),\n+ X86_OP_ENTRY2(CRC32, G,d, E,v, cpuid(SSE42)),\n },\n [2] = {\n X86_OP_ENTRY3(ANDN, G,y, B,y, E,y, vex13 cpuid(BMI1)),\n", "prefixes": [] }