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GET /api/patches/2217954/?format=api
{ "id": 2217954, "url": "http://patchwork.ozlabs.org/api/patches/2217954/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/patch/20260331055858.305207-2-dave.patel@riscstar.com/", "project": { "id": 67, "url": "http://patchwork.ozlabs.org/api/projects/67/?format=api", "name": "OpenSBI development", "link_name": "opensbi", "list_id": "opensbi.lists.infradead.org", "list_email": "opensbi@lists.infradead.org", "web_url": "https://github.com/riscv/opensbi", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "https://github.com/riscv/opensbi/commit/{}" }, "msgid": "<20260331055858.305207-2-dave.patel@riscstar.com>", "list_archive_url": null, "date": "2026-03-31T05:58:55", "name": "[v3,1/3] lib: sbi: Add RISC-V vector context save/restore support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "849807e0c1cade07e65b4095918e68e598555ffa", "submitter": { "id": 92617, "url": "http://patchwork.ozlabs.org/api/people/92617/?format=api", "name": "Dave Patel", "email": "dave.patel@riscstar.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/opensbi/patch/20260331055858.305207-2-dave.patel@riscstar.com/mbox/", "series": [ { "id": 498123, "url": "http://patchwork.ozlabs.org/api/series/498123/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/list/?series=498123", "date": "2026-03-31T05:58:55", "name": "Add eager FP and RISC-V vector context switching support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/498123/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217954/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217954/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=bSc+ObcG;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=riscstar-com.20230601.gappssmtp.com\n header.i=@riscstar-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=c1dSeiL/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: From: Dave Patel <dave.patel@riscstar.com> Eager context\n switch:\n Add support for saving and restoring RISC-V vector extension state in\n OpenSBI.\n This introduces a per-hart vector context structure and helper routines to\n perform full context sav [...]\n Content analysis details: (-1.9 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [2a00:1450:4864:20:0:0:0:436 listed in]\n [list.dnswl.org]\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]", "X-BeenThere": "opensbi@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<opensbi.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/opensbi/>", "List-Post": "<mailto:opensbi@lists.infradead.org>", "List-Help": "<mailto:opensbi-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"opensbi\" <opensbi-bounces@lists.infradead.org>", "Errors-To": "opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "From: Dave Patel <dave.patel@riscstar.com>\n\nEager context switch: Add support for saving and restoring RISC-V vector\nextension state in OpenSBI. This introduces a per-hart vector context\nstructure and helper routines to perform full context save and restore.\n\nThe vector context includes vl, vtype, vcsr CSRs along with storage for all\n32 vector registers. The register state is saved and restored using byte-wise\nvector load/store instructions (vse8.v/vle8.v), making the implementation\nindependent of current SEW/LMUL configuration.\n\nThe implementation follows an eager context switching model where the entire\nvector state is saved and restored on every context switch. This provides a\nsimple and deterministic mechanism without requiring lazy trap-based\nmanagement.\n\nNotes:\n- The SBI_MAX_VLENB is configured using CONFIG_SBI_MAX_VLENB.\n\nSigned-off-by: Dave Patel <dave.patel@riscstar.com>\n---\n include/sbi/sbi_vector.h | 30 ++++++\n lib/sbi/Kconfig | 4 +\n lib/sbi/objects.mk | 1 +\n lib/sbi/sbi_vector.c | 215 +++++++++++++++++++++++++++++++++++++++\n 4 files changed, 250 insertions(+)\n create mode 100644 include/sbi/sbi_vector.h\n create mode 100644 lib/sbi/sbi_vector.c\n\n--\n2.43.0", "diff": "diff --git a/include/sbi/sbi_vector.h b/include/sbi/sbi_vector.h\nnew file mode 100644\nindex 00000000..4ecfaa0b\n--- /dev/null\n+++ b/include/sbi/sbi_vector.h\n@@ -0,0 +1,30 @@\n+/* SPDX-License-Identifier: GPL-2.0\n+ *\n+ * Copyright (c) 2026 RISCstar Solutions.\n+ *\n+ * Authors:\n+ * Dave Patel <dave.patel@riscstar.com>\n+ */\n+\n+#ifndef __SBI_VECTOR_H__\n+#define __SBI_VECTOR_H__\n+\n+#include <sbi/sbi_types.h>\n+\n+#define SBI_MAX_VLENB CONFIG_SBI_MAX_VLENB\n+\n+struct sbi_vector_context {\n+\tunsigned long vl;\n+\tunsigned long vtype;\n+\tunsigned long vcsr;\n+\tunsigned long vstart;\n+\n+\t/* size depends on VLEN */\n+\tuint8_t vregs[32 * SBI_MAX_VLENB];\n+};\n+\n+void sbi_vector_save(struct sbi_vector_context *dst);\n+void sbi_vector_restore(const struct sbi_vector_context *src);\n+\n+#endif //__SBI_VECTOR_H__\n+\ndiff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig\nindex 8479f861..b2432150 100644\n--- a/lib/sbi/Kconfig\n+++ b/lib/sbi/Kconfig\n@@ -74,4 +74,8 @@ config SBI_ECALL_VIRQ\n \tbool \"VIRQ extension\"\n \tdefault y\n\n+config SBI_MAX_VLENB\n+\tint \"Vector VLENB size\"\n+\tdefault 256\n+\n endmenu\ndiff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk\nindex ea816e92..5c0caf39 100644\n--- a/lib/sbi/objects.mk\n+++ b/lib/sbi/objects.mk\n@@ -106,3 +106,4 @@ libsbi-objs-y += sbi_trap_v_ldst.o\n libsbi-objs-y += sbi_unpriv.o\n libsbi-objs-y += sbi_expected_trap.o\n libsbi-objs-y += sbi_cppc.o\n+libsbi-objs-y += sbi_vector.o\ndiff --git a/lib/sbi/sbi_vector.c b/lib/sbi/sbi_vector.c\nnew file mode 100644\nindex 00000000..497d7f94\n--- /dev/null\n+++ b/lib/sbi/sbi_vector.c\n@@ -0,0 +1,215 @@\n+/* SPDX-License-Identifier: GPL-2.0\n+ *\n+ * Copyright (c) 2026 RISCstar Solutions.\n+ *\n+ * Authors:\n+ *\t Dave Patel <dave.patel@riscstar.com>\n+ */\n+\n+#include <sbi/sbi_domain.h>\n+#include <sbi/riscv_encoding.h>\n+#include <sbi/riscv_asm.h>\n+#include <sbi/sbi_vector.h>\n+#include <sbi/sbi_types.h>\n+#include <sbi/sbi_hart.h>\n+\n+#ifdef OPENSBI_CC_SUPPORT_VECTOR\n+\n+static inline void vsetvl(ulong vl, ulong vtype)\n+{\n+ ulong tmp;\n+\n+ asm volatile(\n+\t\".option push\\n\\t\"\n+\t\".option arch, +v\\n\\t\"\n+\t\"vsetvl %0, %1, %2\\n\\t\"\n+\t\".option pop\\n\\t\"\n+\t: \"=r\"(tmp)\n+\t: \"r\"(vl), \"r\"(vtype)\n+\t: \"memory\");\n+}\n+\n+static inline unsigned long vector_vlenb(void)\n+{\n+\tunsigned long vlenb = 0;\n+\n+\tasm volatile (\n+\t\t\".option push\\n\\t\"\n+\t\t\".option arch, +v\\n\\t\"\n+\t\t\"csrr %0, vlenb\\n\\t\"\n+\t\t\".option pop\\n\\t\"\n+\t\t: \"=r\"(vlenb)\n+\t\t:\n+\t\t: \"memory\");\n+\n+\treturn vlenb;\n+}\n+\n+void sbi_vector_save(struct sbi_vector_context *dst)\n+{\n+\tif (!dst)\n+\t\treturn;\n+\n+#define READ_CSR(dst, csr) (\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\\\n+\t\tasm volatile(\t\t\t\t\\\n+\t\t\t\"\t.option push\\n\\t\"\t\\\n+\t\t\t\"\t.option arch, +v\\n\\t\"\t\\\n+\t\t\t\"\tcsrr %0, \" #csr \"\\n\\t\"\t\\\n+\t\t\t\"\t.option pop\\n\\t\"\t\\\n+\t\t\t:\t\"=r\"(dst)\t\t\\\n+\t\t\t:\t\t\t\t\\\n+\t\t\t:\t\"memory\");\t\t\\\n+\t} while (0))\n+\n+\t/* Step 1: Save CSRs */\n+\tREAD_CSR(dst->vtype, vtype);\n+\tREAD_CSR(dst->vl, vl);\n+\tREAD_CSR(dst->vcsr, vcsr);\n+\tREAD_CSR(dst->vstart, vstart);\n+\n+#undef READ_CSR\n+\n+\t/*\n+\t * Step 2: Set a known vector configuration before accessing registers.\n+\t * This ensures the hardware is in a consistent state for save.\n+\t */\n+\tvsetvl(dst->vl, dst->vtype);\n+\n+\tulong vlenb = vector_vlenb();\n+\tuint8_t *base = dst->vregs;\n+\n+\t/* Step 3: Save vector registers */\n+#define SAVE_VREG(i) (\t\t\t\t\t\t\\\n+\tasm volatile(\t\t\t\t\t\t\\\n+\t\t\"\t.option push\\n\\t\"\t\t\t\\\n+\t\t\"\t.option arch, +v\\n\\t\"\t\t\t\\\n+\t\t\"\tvse8.v v\" #i \", (%0)\\n\\t\"\t\t\\\n+\t\t\"\t.option pop\\n\\t\"\t\t\t\\\n+\t\t::\t\"r\"(base + (i) * vlenb)\t: \"memory\"))\n+\n+\tSAVE_VREG(0);\n+\tSAVE_VREG(1);\n+\tSAVE_VREG(2);\n+\tSAVE_VREG(3);\n+\tSAVE_VREG(4);\n+\tSAVE_VREG(5);\n+\tSAVE_VREG(6);\n+\tSAVE_VREG(7);\n+\tSAVE_VREG(8);\n+\tSAVE_VREG(9);\n+\tSAVE_VREG(10);\n+\tSAVE_VREG(11);\n+\tSAVE_VREG(12);\n+\tSAVE_VREG(13);\n+\tSAVE_VREG(14);\n+\tSAVE_VREG(15);\n+\tSAVE_VREG(16);\n+\tSAVE_VREG(17);\n+\tSAVE_VREG(18);\n+\tSAVE_VREG(19);\n+\tSAVE_VREG(20);\n+\tSAVE_VREG(21);\n+\tSAVE_VREG(22);\n+\tSAVE_VREG(23);\n+\tSAVE_VREG(24);\n+\tSAVE_VREG(25);\n+\tSAVE_VREG(26);\n+\tSAVE_VREG(27);\n+\tSAVE_VREG(28);\n+\tSAVE_VREG(29);\n+\tSAVE_VREG(30);\n+\tSAVE_VREG(31);\n+\n+#undef SAVE_VREG\n+}\n+\n+void sbi_vector_restore(const struct sbi_vector_context *src)\n+{\n+\tif (!src)\n+\t\treturn;\n+\n+\tconst uint8_t *base = src->vregs;\n+\tulong vlenb = vector_vlenb();\n+\n+\t/*\n+\t * Step 1: Set a known vector configuration BEFORE touching registers.\n+\t * This avoids clobbering the restored CSRs later.\n+\t */\n+\tvsetvl(src->vl, src->vtype);\n+\n+\t/* Step 2: Restore vector registers */\n+#define RESTORE_VREG(i) (\t\t\t\t\t\\\n+\tasm volatile(\t\t\t\t\t\t\\\n+\t\t\"\t.option push\\n\\t\"\t\t\t\\\n+\t\t\"\t.option arch, +v\\n\\t\"\t\t\t\\\n+\t\t\"\tvle8.v v\" #i \", (%0)\\n\\t\"\t\t\\\n+\t\t\"\t.option pop\\n\\t\"\t\t\t\\\n+\t\t::\t\"r\"(base + (i) * vlenb) : \"memory\"))\n+\n+\tRESTORE_VREG(0);\n+\tRESTORE_VREG(1);\n+\tRESTORE_VREG(2);\n+\tRESTORE_VREG(3);\n+\tRESTORE_VREG(4);\n+\tRESTORE_VREG(5);\n+\tRESTORE_VREG(6);\n+\tRESTORE_VREG(7);\n+\tRESTORE_VREG(8);\n+\tRESTORE_VREG(9);\n+\tRESTORE_VREG(10);\n+\tRESTORE_VREG(11);\n+\tRESTORE_VREG(12);\n+\tRESTORE_VREG(13);\n+\tRESTORE_VREG(14);\n+\tRESTORE_VREG(15);\n+\tRESTORE_VREG(16);\n+\tRESTORE_VREG(17);\n+\tRESTORE_VREG(18);\n+\tRESTORE_VREG(19);\n+\tRESTORE_VREG(20);\n+\tRESTORE_VREG(21);\n+\tRESTORE_VREG(22);\n+\tRESTORE_VREG(23);\n+\tRESTORE_VREG(24);\n+\tRESTORE_VREG(25);\n+\tRESTORE_VREG(26);\n+\tRESTORE_VREG(27);\n+\tRESTORE_VREG(28);\n+\tRESTORE_VREG(29);\n+\tRESTORE_VREG(30);\n+\tRESTORE_VREG(31);\n+#undef RESTORE_VREG\n+\n+\t/* Step 3: Restore CSR's last */\n+#define WRITE_CSR(csr, val) (\t\t\t\\\n+\tasm volatile(\t\t\t\t\\\n+\t\t\"\t.option push\\n\\t\"\t\\\n+\t\t\"\t.option arch, +v\\n\\t\"\t\\\n+\t\t\"\tcsrw \" #csr \", %0\\n\\t\"\t\\\n+\t\t\"\t.option pop\\n\\t\"\t\\\n+\t\t:\t\t\t\t\\\n+\t\t:\t\"r\"(val)\t\t\\\n+\t\t:\t\"memory\"))\n+\n+\t/* Restore CSRs first */\n+\tWRITE_CSR(vtype, src->vtype);\n+\tWRITE_CSR(vl, src->vl);\n+\tWRITE_CSR(vcsr, src->vcsr);\n+\tWRITE_CSR(vstart, src->vstart);\n+#undef WRITE_CSR\n+}\n+\n+#else\n+\n+void sbi_vector_save(struct sbi_vector_context *dst)\n+{\n+\treturn;\n+}\n+\n+void sbi_vector_restore(const struct sbi_vector_context *src)\n+{\n+\treturn;\n+}\n+\n+#endif /* OPENSBI_CC_SUPPORT_VECTOR */\n", "prefixes": [ "v3", "1/3" ] }