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GET /api/patches/2217941/?format=api
{ "id": 2217941, "url": "http://patchwork.ozlabs.org/api/patches/2217941/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260331-t264-pwm-v4-4-c041659677cf@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331-t264-pwm-v4-4-c041659677cf@nvidia.com>", "list_archive_url": null, "date": "2026-03-31T02:12:16", "name": "[v4,4/7] pwm: tegra: Parametrize enable register offset", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9f835a66c4f91a16c46f6baff746abe9ab9d76d0", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260331-t264-pwm-v4-4-c041659677cf@nvidia.com/mbox/", "series": [ { "id": 498119, "url": "http://patchwork.ozlabs.org/api/series/498119/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=498119", "date": "2026-03-31T02:12:15", "name": "Tegra264 PWM support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/498119/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217941/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217941/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13450-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=wde3v3hGQAO603CGMv1VLnFtEovKA+Cg4tknNxjKT54=;\n b=rx7tNFa/z/aPwvEoQQlNwWoveYbY7V548TOvnhH7wdtTFuwYi0+HrYFeM3lhcgKIwxC9atayoA6tJ1qVza+L9sKxClDlO8auRG2bwLezJAdHWhkwi1NOb8nOrL3U+Uj3VQ+NGVk3asTpLC6+P7vW1GwHtjDPK9qpuFmnJzf2D2I8IbEUd/YmtBXX9d/r19OX1W8nNx3Nwkjel3dZB0aUsTAsGGXQQgHMnZaaFclAJH7mJ4mse531NHlJ+BRBdv33/kUY9IhGtekqcbjY7T+o1PHe6Ik9W1uds/MJDLwTjPlkgkeO4Wxus1Yep2pl1gQFv1FXfHXFQ3deDC+cOlJDog==", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "Date": "Tue, 31 Mar 2026 11:12:16 +0900", "Subject": "[PATCH v4 4/7] pwm: tegra: Parametrize enable register offset", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260331-t264-pwm-v4-4-c041659677cf@nvidia.com>", "References": "<20260331-t264-pwm-v4-0-c041659677cf@nvidia.com>", "In-Reply-To": "<20260331-t264-pwm-v4-0-c041659677cf@nvidia.com>", "To": "Thierry Reding <thierry.reding@gmail.com>, =?utf-8?q?Uwe_Kleine-K=C3=B6n?=\n\t=?utf-8?q?ig?= <ukleinek@kernel.org>,\n Jonathan Hunter <jonathanh@nvidia.com>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n Yi-Wei Wang <yiweiw@nvidia.com>, Mikko Perttunen <mperttunen@nvidia.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": "TYCP286CA0374.JPNP286.PROD.OUTLOOK.COM\n (2603:1096:405:79::9) To LV3PR12MB9166.namprd12.prod.outlook.com\n (2603:10b6:408:19c::13)", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": 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"X-MS-Exchange-AntiSpam-MessageData-1": "tPeud1fxwaOnC5AxP26ZhTxjeRpkVnP5Pm4=", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n cd9cb4a0-f8b0-4f8f-1244-08de8ecaff22", "X-MS-Exchange-CrossTenant-AuthSource": "LV3PR12MB9166.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Mar 2026 02:12:46.7579\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n GiecMNfYdi3OgrPoB+CZqaLCSwzUfGVXEPdCj4U6Y1uGSmNzbja48j7hgzQVVwBvhYFhe4d/29DntqMMRcl4+w==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB8330" }, "content": "On Tegra264, the PWM enablement bit is not located at the base address\nof the PWM controller. Hence, introduce an enablement offset field in\nthe tegra_pwm_soc structure to describe the offset of the register.\n\nCo-developed-by: Yi-Wei Wang <yiweiw@nvidia.com>\nSigned-off-by: Yi-Wei Wang <yiweiw@nvidia.com>\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\n drivers/pwm/pwm-tegra.c | 17 ++++++++++++-----\n 1 file changed, 12 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c\nindex 358c81cea05b..b925ef914411 100644\n--- a/drivers/pwm/pwm-tegra.c\n+++ b/drivers/pwm/pwm-tegra.c\n@@ -61,6 +61,7 @@\n \n struct tegra_pwm_soc {\n \tunsigned int num_channels;\n+\tunsigned int enable_reg;\n };\n \n struct tegra_pwm_chip {\n@@ -197,8 +198,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \t\terr = pm_runtime_resume_and_get(pwmchip_parent(chip));\n \t\tif (err)\n \t\t\treturn err;\n-\t} else\n+\t} else if (pc->soc->enable_reg == PWM_CSR_0) {\n \t\tval |= PWM_ENABLE;\n+\t}\n \n \tpwm_writel(pwm, PWM_CSR_0, val);\n \n@@ -213,6 +215,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \n static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)\n {\n+\tstruct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);\n \tint rc = 0;\n \tu32 val;\n \n@@ -220,20 +223,22 @@ static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)\n \tif (rc)\n \t\treturn rc;\n \n-\tval = pwm_readl(pwm, PWM_CSR_0);\n+\n+\tval = pwm_readl(pwm, pc->soc->enable_reg);\n \tval |= PWM_ENABLE;\n-\tpwm_writel(pwm, PWM_CSR_0, val);\n+\tpwm_writel(pwm, pc->soc->enable_reg, val);\n \n \treturn 0;\n }\n \n static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)\n {\n+\tstruct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);\n \tu32 val;\n \n-\tval = pwm_readl(pwm, PWM_CSR_0);\n+\tval = pwm_readl(pwm, pc->soc->enable_reg);\n \tval &= ~PWM_ENABLE;\n-\tpwm_writel(pwm, PWM_CSR_0, val);\n+\tpwm_writel(pwm, pc->soc->enable_reg, val);\n \n \tpm_runtime_put_sync(pwmchip_parent(chip));\n }\n@@ -398,10 +403,12 @@ static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)\n \n static const struct tegra_pwm_soc tegra20_pwm_soc = {\n \t.num_channels = 4,\n+\t.enable_reg = PWM_CSR_0,\n };\n \n static const struct tegra_pwm_soc tegra186_pwm_soc = {\n \t.num_channels = 1,\n+\t.enable_reg = PWM_CSR_0,\n };\n \n static const struct of_device_id tegra_pwm_of_match[] = {\n", "prefixes": [ "v4", "4/7" ] }