Patch Detail
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Show a patch.
patch:
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Update a patch.
GET /api/patches/2217940/?format=api
{ "id": 2217940, "url": "http://patchwork.ozlabs.org/api/patches/2217940/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260331-t264-pwm-v4-3-c041659677cf@nvidia.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331-t264-pwm-v4-3-c041659677cf@nvidia.com>", "list_archive_url": null, "date": "2026-03-31T02:12:15", "name": "[v4,3/7] pwm: tegra: Modify read/write accessors for multi-register channel", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f23f6ba356c950af779d63966c05db4b1be2106d", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260331-t264-pwm-v4-3-c041659677cf@nvidia.com/mbox/", "series": [ { "id": 498118, "url": "http://patchwork.ozlabs.org/api/series/498118/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=498118", "date": "2026-03-31T02:12:12", "name": "Tegra264 PWM support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/498118/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217940/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217940/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pwm+bounces-8432-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass 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header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=VPImkE1GWdV8WeYRws8lAyp6pPI8gFA2YVMajzjzaxo=;\n b=VcdpV59NkZWdE3gQnm4dsLx+3FYAr1ZHstV5F+iVesFTNGbrY+//ZR6tGZOnS0Nb2/P7CJj6FrRZ7U5LaPm6NeF6N3ZIPIPKo3ru9ZnsKp4SQxyz2yH8MEhBFkwrQCePeEc7vaE5pIW1h161wmMLdPc816k5aJ758WWA+iTi76sPb9iCxUSRIfQlRpg0hkk5hXmnp7rnYpnTwsXRqRTYCE7D8+/i5OkQ70yLypQi7qKFzmqFCUt3atP61jinobzelQ7D369eQrjGLRpdbYUc3nAIimk3/lBrspiaeNELlcWudngN91TFVvREBn/I+4eFJ2acsDY958hFLT0Zp0gjpA==", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "Date": "Tue, 31 Mar 2026 11:12:15 +0900", "Subject": "[PATCH v4 3/7] pwm: tegra: Modify read/write accessors for\n multi-register channel", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260331-t264-pwm-v4-3-c041659677cf@nvidia.com>", "References": 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"X-MS-Exchange-AntiSpam-MessageData-1": "iVIhX0Yf0tc1dlr233QgMB/+zjjO4zSvyJU=", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9387fae2-b7b3-47a4-83f5-08de8ecafc75", "X-MS-Exchange-CrossTenant-AuthSource": "SJ2PR12MB9161.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Mar 2026 02:12:40.5143\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n VpFnwxBb4xmCztSwLrGew4N80iK324bAXVA8Q1UtAQAF6uJC9rirShvBrrP9g6hytEK7jux1B58TKtKFV6MJQA==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB8330" }, "content": "On Tegra264, each PWM instance has two registers (per channel, of which\nthere is one). Update the pwm_readl/pwm_writel helper functions to\ntake channel (as struct pwm_device *) and offset separately.\n\nReviewed-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\n drivers/pwm/pwm-tegra.c | 26 +++++++++++++++-----------\n 1 file changed, 15 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c\nindex 8a330169d531..358c81cea05b 100644\n--- a/drivers/pwm/pwm-tegra.c\n+++ b/drivers/pwm/pwm-tegra.c\n@@ -57,6 +57,8 @@\n #define PWM_SCALE_WIDTH\t13\n #define PWM_SCALE_SHIFT\t0\n \n+#define PWM_CSR_0\t0\n+\n struct tegra_pwm_soc {\n \tunsigned int num_channels;\n };\n@@ -78,14 +80,18 @@ static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)\n \treturn pwmchip_get_drvdata(chip);\n }\n \n-static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset)\n+static inline u32 pwm_readl(struct pwm_device *dev, unsigned int offset)\n {\n-\treturn readl(pc->regs + (offset << 4));\n+\tstruct tegra_pwm_chip *chip = to_tegra_pwm_chip(dev->chip);\n+\n+\treturn readl(chip->regs + (dev->hwpwm * 16) + offset);\n }\n \n-static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value)\n+static inline void pwm_writel(struct pwm_device *dev, unsigned int offset, u32 value)\n {\n-\twritel(value, pc->regs + (offset << 4));\n+\tstruct tegra_pwm_chip *chip = to_tegra_pwm_chip(dev->chip);\n+\n+\twritel(value, chip->regs + (dev->hwpwm * 16) + offset);\n }\n \n static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n@@ -194,7 +200,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \t} else\n \t\tval |= PWM_ENABLE;\n \n-\tpwm_writel(pc, pwm->hwpwm, val);\n+\tpwm_writel(pwm, PWM_CSR_0, val);\n \n \t/*\n \t * If the PWM is not enabled, turn the clock off again to save power.\n@@ -207,7 +213,6 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \n static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)\n {\n-\tstruct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);\n \tint rc = 0;\n \tu32 val;\n \n@@ -215,21 +220,20 @@ static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)\n \tif (rc)\n \t\treturn rc;\n \n-\tval = pwm_readl(pc, pwm->hwpwm);\n+\tval = pwm_readl(pwm, PWM_CSR_0);\n \tval |= PWM_ENABLE;\n-\tpwm_writel(pc, pwm->hwpwm, val);\n+\tpwm_writel(pwm, PWM_CSR_0, val);\n \n \treturn 0;\n }\n \n static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)\n {\n-\tstruct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);\n \tu32 val;\n \n-\tval = pwm_readl(pc, pwm->hwpwm);\n+\tval = pwm_readl(pwm, PWM_CSR_0);\n \tval &= ~PWM_ENABLE;\n-\tpwm_writel(pc, pwm->hwpwm, val);\n+\tpwm_writel(pwm, PWM_CSR_0, val);\n \n \tpm_runtime_put_sync(pwmchip_parent(chip));\n }\n", "prefixes": [ "v4", "3/7" ] }