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GET /api/patches/2217938/?format=api
{ "id": 2217938, "url": "http://patchwork.ozlabs.org/api/patches/2217938/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260331-t264-pwm-v4-2-c041659677cf@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331-t264-pwm-v4-2-c041659677cf@nvidia.com>", "list_archive_url": null, "date": "2026-03-31T02:12:14", "name": "[v4,2/7] pwm: tegra: Avoid hard-coded max clock frequency", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "37b5e982082bf047e2f1d172bc2ca22ba1ec2c71", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260331-t264-pwm-v4-2-c041659677cf@nvidia.com/mbox/", "series": [ { "id": 498119, "url": "http://patchwork.ozlabs.org/api/series/498119/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=498119", "date": "2026-03-31T02:12:15", "name": "Tegra264 PWM support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/498119/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217938/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217938/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13448-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=s2c/BzWy3S3JVMDhunFNtRx0qBS5klsK1w9bsQu0VlU=;\n b=V0+9elzFuEuj+QYBRYhk/f7ASO8/Q1wMvWdStzw6Nn5yuvuyvpvtBfDxAP6PUk7BXHHvlHxVmukYrgE4uZSiUooeTBpA7fpSYVYENCFEwKx7sIdUfFgGc/1eoJr0airRd8xMD2yVoEJAuTbXqB6o3qhINYRSEsIQDJ8MCPVytfe/ecXFaPb2c2x/G+dZdEIyTk/1xXAM1nmI+UmxbvnE9NluASjpfdTL0UY8pePNPtQDuks0uUJELNJtulrEbJhmFeUeNjaGUzxP7m/3evYLVmn+j/8Cjg5VV9E2EFMf30YlZQS73DbdxkEfDZfMfWVSGtVc3kiN79p0sR0KrfUW/Q==", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "Date": "Tue, 31 Mar 2026 11:12:14 +0900", "Subject": "[PATCH v4 2/7] pwm: tegra: Avoid hard-coded max clock frequency", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260331-t264-pwm-v4-2-c041659677cf@nvidia.com>", "References": "<20260331-t264-pwm-v4-0-c041659677cf@nvidia.com>", "In-Reply-To": "<20260331-t264-pwm-v4-0-c041659677cf@nvidia.com>", "To": "Thierry Reding <thierry.reding@gmail.com>, =?utf-8?q?Uwe_Kleine-K=C3=B6n?=\n\t=?utf-8?q?ig?= <ukleinek@kernel.org>,\n Jonathan Hunter <jonathanh@nvidia.com>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n Yi-Wei Wang <yiweiw@nvidia.com>, Mikko Perttunen <mperttunen@nvidia.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": "TY4P286CA0043.JPNP286.PROD.OUTLOOK.COM\n (2603:1096:405:36e::10) To SJ2PR12MB9161.namprd12.prod.outlook.com\n (2603:10b6:a03:566::20)", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": 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"=?utf-8?q?3msOIeQ0W/ewSc60jcp0YyQ2FRdJ?=\n\t=?utf-8?q?AgsxgnFw8kGktVJvz+BJgmeQURdunrZwanMNlfvHDBp1R4aO2VBG8JN8Jm9DUrJoz?=\n\t=?utf-8?q?WT5dgEEY7Wcmz9KQlCQh9/p+HF0zxeNVxrN8SWjECmUZ70sFd9rc28aVoi0q8T8j4?=\n\t=?utf-8?q?0/LsBpvtV14tBO2WbPTeQ6JpiR0ych8Pf6u6IGtp2eSa20X0/NsAiC4A/ezTOHCJQ?=\n\t=?utf-8?q?Fdro0gnX077NYJSQ3O6LNqWyNX2NBYjh1G7VXKXsPuxGTY7kIOPsDTmPTscvPQd1Q?=\n\t=?utf-8?q?vgwCHYVVABrBhnbm5DDi5Lgfh2M3W74WqxtwYl8ut0YCiSzsAgjafxs9k4S3bit7w?=\n\t=?utf-8?q?81lKlCdVS20/XaKlZYJk8+RHX+U1PksMytO9ykqIJQTF3uI/RBsIexEWF9yjmY2mG?=\n\t=?utf-8?q?iOx42EB0OI+dbqe8OnLhYqAylizGsj1qTox1xQEJj61xE0zIidlgJuwvIgP4/5hCr?=\n\t=?utf-8?q?CXq3qmEQbw/1ivHzwRSoJEpLcRiyhE3s1iQWvDzNmqeQEUthlj6ggyOrEhy/STAXD?=\n\t=?utf-8?q?aMxeq6eqnxgpK+UH3OMSVYYooa1QTdgOq7+G8E/pOJOen0SgRPbTfh+dIKIw2b8mw?=\n\t=?utf-8?q?atT72qUZl/xWdj2b+ukTOorBlv16GUX6WoLp1P2TiWgzLPd6pkAzMhfn0H43gOANt?=\n\t=?utf-8?q?qXQTR3YTRsEyw6U21wxmu5nOsAz22l7GXJpa4ApEO+Z+T0cC4Idh7F9TBfA2/xvdm?=\n\t=?utf-8?q?YfmmfGccTPmTUYT7mVM+p/qeqmer6WpDne5UG8mHouL3aTrIa3m+OjmiIUCQFqkgn?=\n\t=?utf-8?q?YV5JkomadiYVEhx+mZyw7jTh4vTHQ+dT6J6gbIY+4I67XOBE+PRZGEKmv4RDL02BS?=\n\t=?utf-8?q?+aaTPFGFXqrCSO0Jk/s0/8xt8pml/2FD+LaHoEZsmXVulkmwlIQMk/UCmE8+cB5/S?=\n\t=?utf-8?q?9xKS3T8UVUJ5+d4+N/8Tf1GtgA3o6nAR85ttM7Kg/aApWg0GPk2Iw1dKWvqEJqAcF?=\n\t=?utf-8?q?7xoZqk2uPN3nHoU+8Nk01nC9ubCnpMfPCOkMsnZkdEV9WajXSFmNe9Y5fKILwC3Yg?=\n\t=?utf-8?q?1g96cvJqyAty2a+XeXhtOtJZuOSZmw1bOk3T+Y5hnn8Khh94pr98Z/rOK7GJukrq3?=\n\t=?utf-8?q?o8oMD3OQbD/fRqzvw+xXRjgmz+bL7+tph3sepW1UwByVxgbgn0jZXnb+00jTsHTu2?=\n\t=?utf-8?q?olqFEILvh7ldati5xKVRtzkpAKdvBv6Znu3VXd12vp7lQRX4xlKYdw+hGtwCWoa/u?=\n\t=?utf-8?q?TpwwfgBqoecN3fuHbb4jhcVG/ShOV9NVJmtUeUjZ9J+hAPbOl6Hf8SScBReGt9wrt?=\n\t=?utf-8?q?vt7LfztupS3pLIBUOmzecdQaFoQuildqxlHsfdbLyB54Bvsblf0WCkXK/DBGIQART?=\n\t=?utf-8?q?NtB4rollQ+dgF6JmRU1Qs/sF1OKK6/5LuX0rqAnT8JwkCgYoZqviGFXkWYgwprG2H?=\n\t=?utf-8?q?pfSnu1zcMn9QQ05EvVdDANRX5O7w+wFXWFOqfG97HA5WIoJSdefcRFZLDSADMqvIl?=\n\t=?utf-8?q?rdspUz7/wYkeuJlTuEnCyemIhQbyvwevXSZHEHVyoUcchIdmnHQw0pTK5KUQFOhqr?=\n\t=?utf-8?q?QziB2x285HBuowJk55ddO+foNbSNVWBW//mevTWZSexto3skhBy8LBtUkzkIGbscW?=\n\t=?utf-8?q?lfCPfihPGw7pZKEP3LUYxCcgOYnelW0UPZk/Aju/qmbi0nyX7k7AJB//HPOvkofMN?=\n\t=?utf-8?q?JCMLFDLj2BntQAHalhaDQzKDbw4fhENA4mGZ9v7mMc/bVcnetaNRM0zthIGS6Hyo5?=\n\t=?utf-8?q?LVdIlwZUf8Z3MvTgt?=", "X-MS-Exchange-AntiSpam-MessageData-1": "z9GbsvjH7meK5waZzB4F8/UCrJ4/Y/eIulk=", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7c3aa5d6-3e55-42ac-11d4-08de8ecafa15", "X-MS-Exchange-CrossTenant-AuthSource": "SJ2PR12MB9161.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Mar 2026 02:12:36.4549\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n HPm3XCvndQeCxJgopkIYjg+/LRm08pvfCkufvdRGI2EIy8V8q6Aa+BDFEvco2waEdrC7CbyPORIbq+qU0NcOFQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB8330" }, "content": "From: Yi-Wei Wang <yiweiw@nvidia.com>\n\nThe clock driving the Tegra PWM IP can be sourced from different parent\nclocks. Hence, let dev_pm_opp_set_rate() set the max clock rate based\nupon the current parent clock that can be specified via device-tree.\n\nAfter this, the Tegra194 SoC data becomes redundant, so get rid of it.\n\nSigned-off-by: Yi-Wei Wang <yiweiw@nvidia.com>\nCo-developed-by: Mikko Perttunen <mperttunen@nvidia.com>\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\n drivers/pwm/pwm-tegra.c | 16 +++-------------\n 1 file changed, 3 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c\nindex 172063b51d44..8a330169d531 100644\n--- a/drivers/pwm/pwm-tegra.c\n+++ b/drivers/pwm/pwm-tegra.c\n@@ -59,9 +59,6 @@\n \n struct tegra_pwm_soc {\n \tunsigned int num_channels;\n-\n-\t/* Maximum IP frequency for given SoCs */\n-\tunsigned long max_frequency;\n };\n \n struct tegra_pwm_chip {\n@@ -303,7 +300,7 @@ static int tegra_pwm_probe(struct platform_device *pdev)\n \t\treturn ret;\n \n \t/* Set maximum frequency of the IP */\n-\tret = dev_pm_opp_set_rate(&pdev->dev, pc->soc->max_frequency);\n+\tret = dev_pm_opp_set_rate(&pdev->dev, ULONG_MAX);\n \tif (ret < 0) {\n \t\tdev_err(&pdev->dev, \"Failed to set max frequency: %d\\n\", ret);\n \t\tgoto put_pm;\n@@ -318,7 +315,7 @@ static int tegra_pwm_probe(struct platform_device *pdev)\n \n \t/* Set minimum limit of PWM period for the IP */\n \tpc->min_period_ns =\n-\t (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;\n+\t (NSEC_PER_SEC / (pc->clk_rate >> PWM_DUTY_WIDTH)) + 1;\n \n \tpc->rst = devm_reset_control_get_exclusive(&pdev->dev, \"pwm\");\n \tif (IS_ERR(pc->rst)) {\n@@ -397,23 +394,16 @@ static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)\n \n static const struct tegra_pwm_soc tegra20_pwm_soc = {\n \t.num_channels = 4,\n-\t.max_frequency = 48000000UL,\n };\n \n static const struct tegra_pwm_soc tegra186_pwm_soc = {\n \t.num_channels = 1,\n-\t.max_frequency = 102000000UL,\n-};\n-\n-static const struct tegra_pwm_soc tegra194_pwm_soc = {\n-\t.num_channels = 1,\n-\t.max_frequency = 408000000UL,\n };\n \n static const struct of_device_id tegra_pwm_of_match[] = {\n \t{ .compatible = \"nvidia,tegra20-pwm\", .data = &tegra20_pwm_soc },\n \t{ .compatible = \"nvidia,tegra186-pwm\", .data = &tegra186_pwm_soc },\n-\t{ .compatible = \"nvidia,tegra194-pwm\", .data = &tegra194_pwm_soc },\n+\t{ .compatible = \"nvidia,tegra194-pwm\", .data = &tegra186_pwm_soc },\n \t{ }\n };\n MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);\n", "prefixes": [ "v4", "2/7" ] }