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GET /api/patches/2217933/?format=api
{ "id": 2217933, "url": "http://patchwork.ozlabs.org/api/patches/2217933/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260331-t264-pwm-v4-7-c041659677cf@nvidia.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331-t264-pwm-v4-7-c041659677cf@nvidia.com>", "list_archive_url": null, "date": "2026-03-31T02:12:19", "name": "[v4,7/7] arm64: tegra: Add PWM controllers on Tegra264", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "693c4a9359127c4ba47e096aa76a1e41da82f3a9", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260331-t264-pwm-v4-7-c041659677cf@nvidia.com/mbox/", "series": [ { "id": 498118, "url": "http://patchwork.ozlabs.org/api/series/498118/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=498118", "date": "2026-03-31T02:12:12", "name": "Tegra264 PWM support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/498118/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217933/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217933/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pwm+bounces-8436-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n 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header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=V4e3T8/wHGH1MGCYChzTeTntjX5tt56SeqPBDudJ3NY=;\n b=TiWsSAKB2qycNJfLJRBQvfWLNA1E1w2WLG1DGRMH9YnaT3/xzOksC4AE2ZFW2ZV+LMMqK11FR9WulOHjqrdH+TMK+zcOoPE7DfKIk+vL1MxnofTsVHmbhnvhD1U0bIhakIdPXa39tAgPSRzy+roDYWfZW3XBFh+zLDuxjjZNHSCnxehOqk0s0Dr1w4xXEbB4fAMciZEKfTNKvRSgOToWQnKwRUZS0/0Na9i50Ifek/2mMkHtI9PJGbWkH6k9/iwgLgzgnxu77MdBE0cDaevoUgHQi76RPlX1jzU1bXMC/+LKs6Pw34xv4LbYaI6l8LhoB4CRhApyVPWjlngRbcd6Pw==", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "Date": "Tue, 31 Mar 2026 11:12:19 +0900", "Subject": "[PATCH v4 7/7] arm64: tegra: Add PWM controllers on Tegra264", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260331-t264-pwm-v4-7-c041659677cf@nvidia.com>", "References": "<20260331-t264-pwm-v4-0-c041659677cf@nvidia.com>", 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"X-MS-Exchange-AntiSpam-MessageData-1": "fnQ5WvHoko0VgV3PhPIjKWvbORe2s6mmHXU=", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0a5af6af-ce54-41e1-c6b5-08de8ecb0975", "X-MS-Exchange-CrossTenant-AuthSource": "SJ2PR12MB9161.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Mar 2026 02:13:02.3478\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n y0E1ytClEqtNHdMXXAAyTAxR11w5mGXFxod9Qp5cUzci2yr5AhrC4dRNEhnhbGOaMM520SpDf29dn/S3vaOAxw==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB8330" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nTegra264 has a number of PWM controllers that are similar but\nincompatible with those found on earlier chips.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n[mperttunen: Adjust commit message]\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\n arch/arm64/boot/dts/nvidia/tegra264.dtsi | 72 ++++++++++++++++++++++++++++++++\n 1 file changed, 72 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi\nindex 7644a41d5f72..13fd04068016 100644\n--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi\n+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi\n@@ -3336,6 +3336,18 @@ i2c3: i2c@c610000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tpwm4: pwm@c6a0000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc6a0000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM4>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM4>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n \t\tpmc: pmc@c800000 {\n \t\t\tcompatible = \"nvidia,tegra264-pmc\";\n \t\t\treg = <0x0 0x0c800000 0x0 0x100000>,\n@@ -3538,6 +3550,66 @@ i2c16: i2c@c430000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tpwm2: pwm@c5e0000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc5e0000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM2>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM2>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n+\t\tpwm3: pwm@c5f0000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc5f0000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM3>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM3>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n+\t\tpwm5: pwm@c600000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc600000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM5>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM5>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n+\t\tpwm9: pwm@c610000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc610000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM9>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM9>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n+\t\tpwm10: pwm@c620000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc620000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM10>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM10>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n \t\ti2c0: i2c@c630000 {\n \t\t\tcompatible = \"nvidia,tegra264-i2c\";\n \t\t\treg = <0x00 0x0c630000 0x0 0x10000>;\n", "prefixes": [ "v4", "7/7" ] }