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GET /api/patches/2217912/?format=api
{ "id": 2217912, "url": "http://patchwork.ozlabs.org/api/patches/2217912/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260330222900.982404-1-alex.bennee@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330222900.982404-1-alex.bennee@linaro.org>", "list_archive_url": null, "date": "2026-03-30T22:28:59", "name": "[RFC] hw/display: modernise the vga debug code (!!GenAI!!)", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7626f2625c75a9e79320317c1493b93581847ecf", "submitter": { "id": 39532, "url": "http://patchwork.ozlabs.org/api/people/39532/?format=api", "name": "Alex Bennée", "email": "alex.bennee@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260330222900.982404-1-alex.bennee@linaro.org/mbox/", "series": [ { "id": 498106, "url": "http://patchwork.ozlabs.org/api/series/498106/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498106", "date": "2026-03-30T22:28:59", "name": "[RFC] hw/display: modernise the vga debug code (!!GenAI!!)", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498106/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217912/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217912/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=KB/FwhwX;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::535;\n envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x535.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Remove dead code, replace debug prints with trace points.\n\nLink: https://patchew.org/QEMU/20260330140656.46FE55969F2@zero.eik.bme.hu/\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n\n---\nAs an experiment I prompted Gemini with the thread contents and asked\nit to make the changes. It cost about 9p in inference and I would\nargue this barely counts as copyrightable as it is a simple\ntransformation of existing patterns.\n---\n hw/display/vga.c | 89 ++++++++---------------------------------\n hw/display/trace-events | 11 +++++\n 2 files changed, 27 insertions(+), 73 deletions(-)", "diff": "diff --git a/hw/display/vga.c b/hw/display/vga.c\nindex ee7d97b5c21..081a3b2576c 100644\n--- a/hw/display/vga.c\n+++ b/hw/display/vga.c\n@@ -40,9 +40,6 @@\n #include \"migration/vmstate.h\"\n #include \"trace.h\"\n \n-//#define DEBUG_VGA_MEM\n-//#define DEBUG_VGA_REG\n-\n bool have_vga = true;\n \n /* 16 state changes per vertical frame @60 Hz */\n@@ -201,9 +198,6 @@ static void vga_precise_update_retrace_info(VGACommonState *s)\n int vretr_end_line;\n \n int dots;\n-#if 0\n- int div2, sldiv2;\n-#endif\n int clocking_mode;\n int clock_sel;\n const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};\n@@ -245,40 +239,9 @@ static void vga_precise_update_retrace_info(VGACommonState *s)\n r->hend = r->hstart + hretr_end_char + 1;\n r->htotal = htotal_chars;\n \n-#if 0\n- div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;\n- sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;\n- printf (\n- \"hz=%f\\n\"\n- \"htotal = %d\\n\"\n- \"hretr_start = %d\\n\"\n- \"hretr_skew = %d\\n\"\n- \"hretr_end = %d\\n\"\n- \"vtotal = %d\\n\"\n- \"vretr_start = %d\\n\"\n- \"vretr_end = %d\\n\"\n- \"div2 = %d sldiv2 = %d\\n\"\n- \"clocking_mode = %d\\n\"\n- \"clock_sel = %d %d\\n\"\n- \"dots = %d\\n\"\n- \"ticks/char = %\" PRId64 \"\\n\"\n- \"\\n\",\n- (double) NANOSECONDS_PER_SECOND / (r->ticks_per_char * r->total_chars),\n- htotal_chars,\n- hretr_start_char,\n- hretr_skew_chars,\n- hretr_end_char,\n- vtotal_lines,\n- vretr_start_line,\n- vretr_end_line,\n- div2, sldiv2,\n- clocking_mode,\n- clock_sel,\n- clk_hz[clock_sel],\n- dots,\n- r->ticks_per_char\n- );\n-#endif\n+ trace_vga_update_retrace_info(htotal_chars, vtotal_lines,\n+ vretr_start_line, vretr_end_line,\n+ dots, r->ticks_per_char);\n }\n \n static uint8_t vga_precise_retrace(VGACommonState *s)\n@@ -358,9 +321,7 @@ uint32_t vga_ioport_read(void *opaque, uint32_t addr)\n break;\n case VGA_SEQ_D:\n val = s->sr[s->sr_index];\n-#ifdef DEBUG_VGA_REG\n- printf(\"vga: read SR%x = 0x%02x\\n\", s->sr_index, val);\n-#endif\n+ trace_vga_read_sr(s->sr_index, val);\n break;\n case VGA_PEL_IR:\n val = s->dac_state;\n@@ -386,9 +347,7 @@ uint32_t vga_ioport_read(void *opaque, uint32_t addr)\n break;\n case VGA_GFX_D:\n val = s->gr[s->gr_index];\n-#ifdef DEBUG_VGA_REG\n- printf(\"vga: read GR%x = 0x%02x\\n\", s->gr_index, val);\n-#endif\n+ trace_vga_read_gr(s->gr_index, val);\n break;\n case VGA_CRT_IM:\n case VGA_CRT_IC:\n@@ -397,9 +356,7 @@ uint32_t vga_ioport_read(void *opaque, uint32_t addr)\n case VGA_CRT_DM:\n case VGA_CRT_DC:\n val = s->cr[s->cr_index];\n-#ifdef DEBUG_VGA_REG\n- printf(\"vga: read CR%x = 0x%02x\\n\", s->cr_index, val);\n-#endif\n+ trace_vga_read_cr(s->cr_index, val);\n break;\n case VGA_IS1_RM:\n case VGA_IS1_RC:\n@@ -467,9 +424,7 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)\n s->sr_index = val & 7;\n break;\n case VGA_SEQ_D:\n-#ifdef DEBUG_VGA_REG\n- printf(\"vga: write SR%x = 0x%02x\\n\", s->sr_index, val);\n-#endif\n+ trace_vga_write_sr(s->sr_index, val);\n s->sr[s->sr_index] = val & sr_mask[s->sr_index];\n if (s->sr_index == VGA_SEQ_CLOCK_MODE) {\n s->update_retrace_info(s);\n@@ -498,9 +453,7 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)\n s->gr_index = val & 0x0f;\n break;\n case VGA_GFX_D:\n-#ifdef DEBUG_VGA_REG\n- printf(\"vga: write GR%x = 0x%02x\\n\", s->gr_index, val);\n-#endif\n+ trace_vga_write_gr(s->gr_index, val);\n s->gr[s->gr_index] = val & gr_mask[s->gr_index];\n vbe_update_vgaregs(s);\n vga_update_memory_access(s);\n@@ -511,9 +464,7 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)\n break;\n case VGA_CRT_DM:\n case VGA_CRT_DC:\n-#ifdef DEBUG_VGA_REG\n- printf(\"vga: write CR%x = 0x%02x\\n\", s->cr_index, val);\n-#endif\n+ trace_vga_write_cr(s->cr_index, val);\n /* handle CR0-7 protection */\n if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&\n s->cr_index <= VGA_CRTC_OVERFLOW) {\n@@ -873,9 +824,7 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)\n uint32_t write_mask, bit_mask, set_mask;\n int plane = 0;\n \n-#ifdef DEBUG_VGA_MEM\n- printf(\"vga: [0x\" HWADDR_FMT_plx \"] = 0x%02x\\n\", addr, val);\n-#endif\n+ trace_vga_vram_write(addr, val);\n /* convert to VGA memory offset */\n memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;\n addr &= 0x1ffff;\n@@ -945,9 +894,7 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)\n if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {\n if (mask) {\n s->vram_ptr[(addr << 2) | plane] = val;\n-#ifdef DEBUG_VGA_MEM\n- printf(\"vga: chain4: [0x\" HWADDR_FMT_plx \"]\\n\", addr);\n-#endif\n+ trace_vga_vram_write((addr << 2) | plane, val);\n s->plane_updated |= mask; /* only used to detect font change */\n memory_region_set_dirty(&s->vram, addr, 1);\n }\n@@ -1021,10 +968,7 @@ do_write:\n ((uint32_t *)s->vram_ptr)[addr] =\n (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |\n (val & write_mask);\n-#ifdef DEBUG_VGA_MEM\n- printf(\"vga: latch: [0x\" HWADDR_FMT_plx \"] mask=0x%08x val=0x%08x\\n\",\n- addr * 4, write_mask, val);\n-#endif\n+ trace_vga_vram_latch_write(addr << 2, write_mask, val);\n memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));\n }\n \n@@ -1660,11 +1604,10 @@ static void vga_draw_graphic(VGACommonState *s, int full_update)\n s->cursor_invalidate(s);\n }\n \n-#if 0\n- printf(\"w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\\n\",\n- width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],\n- s->params.line_compare, sr(s, VGA_SEQ_CLOCK_MODE));\n-#endif\n+ trace_vga_draw_graphic(width, height, v, s->params.line_offset,\n+ s->cr[9], s->cr[VGA_CRTC_MODE],\n+ s->params.line_compare, sr(s, VGA_SEQ_CLOCK_MODE));\n+\n addr1 = (s->params.start_addr * 4);\n y_start = -1;\n d = surface_data(surface);\ndiff --git a/hw/display/trace-events b/hw/display/trace-events\nindex 4bfc457fbac..c6591c90ca8 100644\n--- a/hw/display/trace-events\n+++ b/hw/display/trace-events\n@@ -130,6 +130,17 @@ vga_std_read_io(uint32_t addr, uint32_t val) \"addr 0x%x, val 0x%x\"\n vga_std_write_io(uint32_t addr, uint32_t val) \"addr 0x%x, val 0x%x\"\n vga_vbe_read(uint32_t index, uint32_t val) \"index 0x%x, val 0x%x\"\n vga_vbe_write(uint32_t index, uint32_t val) \"index 0x%x, val 0x%x\"\n+vga_vram_read(uint64_t addr, uint32_t val) \"addr 0x%\"PRIx64\" val 0x%x\"\n+vga_vram_write(uint64_t addr, uint32_t val) \"addr 0x%\"PRIx64\" val 0x%x\"\n+vga_vram_latch_write(uint64_t addr, uint32_t mask, uint32_t val) \"addr 0x%\"PRIx64\" mask 0x%08x val 0x%08x\"\n+vga_read_sr(uint32_t index, uint32_t val) \"index 0x%x, val 0x%x\"\n+vga_write_sr(uint32_t index, uint32_t val) \"index 0x%x, val 0x%x\"\n+vga_read_gr(uint32_t index, uint32_t val) \"index 0x%x, val 0x%x\"\n+vga_write_gr(uint32_t index, uint32_t val) \"index 0x%x, val 0x%x\"\n+vga_read_cr(uint32_t index, uint32_t val) \"index 0x%x, val 0x%x\"\n+vga_write_cr(uint32_t index, uint32_t val) \"index 0x%x, val 0x%x\"\n+vga_draw_graphic(uint32_t w, uint32_t h, uint32_t v, uint32_t line_offset, uint32_t cr09, uint32_t cr17, uint32_t linecmp, uint32_t sr01) \"w=%u h=%u v=%u line_offset=%u cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%u sr[0x01]=0x%02x\"\n+vga_update_retrace_info(uint32_t htotal, uint32_t vtotal, uint32_t vretr_start, uint32_t vretr_end, uint32_t dots, uint64_t ticks_per_char) \"htotal %u, vtotal %u, vretr_start %u, vretr_end %u, dots %u, ticks/char %\"PRIu64\n \n # cirrus_vga.c\n vga_cirrus_read_io(uint32_t addr, uint32_t val) \"addr 0x%x, val 0x%x\"\n", "prefixes": [ "RFC" ] }