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GET /api/patches/2217881/?format=api
{ "id": 2217881, "url": "http://patchwork.ozlabs.org/api/patches/2217881/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260330-mtk-genio-720-ufs-v1-4-3bad8362ed70@baylibre.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330-mtk-genio-720-ufs-v1-4-3bad8362ed70@baylibre.com>", "list_archive_url": null, "date": "2026-03-30T20:42:16", "name": "[4/6] arm: dts: mt8189: add UFS nodes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ad1b0696ece5a53273049850c3942f49df98a25c", "submitter": { "id": 87228, "url": "http://patchwork.ozlabs.org/api/people/87228/?format=api", "name": "David Lechner", "email": "dlechner@baylibre.com" }, "delegate": { "id": 161331, "url": "http://patchwork.ozlabs.org/api/users/161331/?format=api", "username": "dlech", "first_name": "David", "last_name": "Lechner", "email": "dlechner@baylibre.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260330-mtk-genio-720-ufs-v1-4-3bad8362ed70@baylibre.com/mbox/", "series": [ { "id": 498092, "url": "http://patchwork.ozlabs.org/api/series/498092/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=498092", "date": "2026-03-30T20:42:12", "name": "arm: mediatek: add UFS support for Genio 520/720 EVKs", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498092/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217881/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217881/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", 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GdXwp2WBLx1jg5YofWfZ1ft0TNrDrn", "X-Received": "by 2002:a05:6830:828b:b0:7d9:b189:d938 with SMTP id\n 46e09a7af769-7d9faddcfecmr8292516a34.10.1774903390206;\n Mon, 30 Mar 2026 13:43:10 -0700 (PDT)", "From": "David Lechner <dlechner@baylibre.com>", "Date": "Mon, 30 Mar 2026 15:42:16 -0500", "Subject": "[PATCH 4/6] arm: dts: mt8189: add UFS nodes", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260330-mtk-genio-720-ufs-v1-4-3bad8362ed70@baylibre.com>", "References": "<20260330-mtk-genio-720-ufs-v1-0-3bad8362ed70@baylibre.com>", "In-Reply-To": "<20260330-mtk-genio-720-ufs-v1-0-3bad8362ed70@baylibre.com>", "To": "Neil Armstrong <neil.armstrong@linaro.org>,\n Bhupesh Sharma <bhupesh.linux@gmail.com>,\n Neha Malcom Francis <n-francis@ti.com>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,\n Tom Rini <trini@konsulko.com>, Lukasz Majewski <lukma@denx.de>", "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>", "X-Mailer": "b4 0.16-dev", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=4233; i=dlechner@baylibre.com;\n h=from:subject:message-id;\n bh=YRukyZS+0FRf8nrT1/GZGMvVv9wyXCshQvpCFxYGO7I=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpyuBFpKieOEGDJ2cv6r0MlclK8ez+BYQjpOcZh\n zRB5b8atymJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCacrgRRYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/ArRkH/08RprhGGdptwH3SYqGkAXZktjtU6Sftd4ZqjAS\n 3aRi5tHkV4NxloqTurvgUJlVrUcqcoYt4CCR+xlSCTlGUtQSrExZbakE08co5BQngHLUWFe1Tf3\n 5pe5/9ahUcDNVSR+aK7d4ZYo4tqsZkRsSmykmkQAtn2p9FRj6EOQ3gXDaUliZ1bdPv0ttmk1vzg\n DcjgSt869SDqWH9b0usG+b9/TZS5dgS1y1/4761nW1LDPY0TCdUDSk4AS3rkNelJL8oYM8mRJBo\n O6Hd6ZHH2JYYvayx1ni5e03bguSIwOweF/QuU8vxXSH+l9snV9BIVSmZQ9tjz4m8ZZn8qq7I24T\n SCu4=", "X-Developer-Key": "i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add UFS nodes to mt8189.dtsi.\n\nThis is copied from the proposed upstream patch [1].\n\nLink: https://lore.kernel.org/linux-mediatek/20251111070031.305281-10-jh.hsu@mediatek.com/ [1]\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n arch/arm/dts/mt8189.dtsi | 115 +++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 115 insertions(+)", "diff": "diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi\nindex d246be63293..e9fd21ea095 100644\n--- a/arch/arm/dts/mt8189.dtsi\n+++ b/arch/arm/dts/mt8189.dtsi\n@@ -7,6 +7,7 @@\n #include <dt-bindings/clock/mediatek,mt8189-clk.h>\n #include <dt-bindings/interrupt-controller/irq.h>\n #include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/reset/ti-syscon.h>\n \n / {\n \tcompatible = \"mediatek,mt8189\";\n@@ -286,6 +287,120 @@\n \t\t\t#interrupt-cells = <2>;\n \t\t};\n \n+\t\tufshci: ufshci@112b0000 {\n+\t\t\tcompatible = \"mediatek,mt8183-ufshci\";\n+\t\t\treg = <0 0x112b0000 0 0x2300>;\n+\t\t\tinterrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;\n+\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_U_SEL>,\n+\t\t\t\t <&clk26m>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_MSDCPLL_D2>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_AES_UFSFDE_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_U_MBIST_SEL>,\n+\t\t\t\t <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM>,\n+\t\t\t\t <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0>,\n+\t\t\t\t <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1>,\n+\t\t\t\t <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_SYS>,\n+\t\t\t\t <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_U_SAP_CFG>,\n+\t\t\t\t <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS>,\n+\t\t\t\t <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_UFS>,\n+\t\t\t\t <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_AES>,\n+\t\t\t\t <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_U_AHB>,\n+\t\t\t\t <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_U_AXI>;\n+\n+\t\t\tclock-names = \"ufs_sel\",\n+\t\t\t\t \"ufs_sel_min_src\",\n+\t\t\t\t \"ufs_sel_max_src\",\n+\t\t\t\t \"ufs_fde\",\n+\t\t\t\t \"ufs_mbist\",\n+\t\t\t\t \"unipro_tx_sym\",\n+\t\t\t\t \"unipro_rx_sym0\",\n+\t\t\t\t \"unipro_rx_sym1\",\n+\t\t\t\t \"unipro_sys\",\n+\t\t\t\t \"unipro_phy_sap\",\n+\t\t\t\t \"phy_top_ahb_s_bus\",\n+\t\t\t\t \"ufshci_ufs\",\n+\t\t\t\t \"ufshci_aes\",\n+\t\t\t\t \"ufshci_ufs_ahb\",\n+\t\t\t\t \"ufshci_aes_axi\";\n+\n+\t\t\tfreq-table-hz = <26000000 208000000>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>;\n+\n+\t\t\tvcc-supply = <&mt6359_vemc_1_ldo_reg>;\n+\t\t\tvccq-supply = <&mt6359_vio18_ldo_reg>;\n+\t\t\tvccq2-supply = <&mt6359_vufs_ldo_reg>;\n+\n+\t\t\tresets = <&ufscfgpdn_rst 0>,\n+\t\t\t\t <&ufscfgpdn_rst 1>,\n+\t\t\t\t <&ufscfgpdn_rst 2>;\n+\n+\t\t\treset-names = \"unipro_rst\",\n+\t\t\t\t \"crypto_rst\",\n+\t\t\t\t \"hci_rst\";\n+\n+\t\t\tmediatek,ufs-disable-mcq;\n+\t\t\tmediatek,ufs-rtff-mtcmos;\n+\t\t\tmediatek,ufs-broken-vcc;\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tufscfg_ao_reg_clk: syscon@112b8000 {\n+\t\t\tcompatible = \"mediatek,mt8189-ufscfg-ao\", \"syscon\", \"simple-mfd\";\n+\t\t\treg = <0 0x112b8000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\n+\t\t\tufscfgao_rst: reset-controller {\n+\t\t\t\tcompatible = \"ti,syscon-reset\";\n+\t\t\t\t#reset-cells = <1>;\n+\n+\t\t\t\tti,reset-bits = <\n+\t\t\t\t\t/* ufs mphy reset */\n+\t\t\t\t\t/* 8: mphy */\n+\t\t\t\t\t0x48 8 0x4c 8 0 0\n+\t\t\t\t\t(ASSERT_SET | DEASSERT_SET | STATUS_NONE)\n+\t\t\t\t>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tufscfg_pdn_reg_clk: syscon@112bb000 {\n+\t\t\tcompatible = \"mediatek,mt8189-ufscfg-pdn\", \"syscon\", \"simple-mfd\";\n+\t\t\treg = <0 0x112bb000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\n+\t\t\tufscfgpdn_rst: reset-controller {\n+\t\t\t\tcompatible = \"ti,syscon-reset\";\n+\t\t\t\t#reset-cells = <1>;\n+\n+\t\t\t\tti,reset-bits = <\n+\t\t\t\t\t/* ufs ufschi/crypto/unipro reset */\n+\t\t\t\t\t/* 0: unipro */\n+\t\t\t\t\t0x48 0 0x4c 0 0 0\n+\t\t\t\t\t(ASSERT_SET | DEASSERT_SET | STATUS_NONE)\n+\t\t\t\t\t/* 1: ufs-crypto */\n+\t\t\t\t\t0x48 1 0x4c 1 0 0\n+\t\t\t\t\t(ASSERT_SET | DEASSERT_SET | STATUS_NONE)\n+\t\t\t\t\t/* 2: ufshci */\n+\t\t\t\t\t0x48 2 0x4c 2 0 0\n+\t\t\t\t\t(ASSERT_SET | DEASSERT_SET | STATUS_NONE)\n+\t\t\t\t>;\n+\t\t\t};\n+\t\t};\n+\n \t\tpwrap: pwrap@1cc04000 {\n \t\t\tcompatible = \"mediatek,mt8189-pwrap\", \"mediatek,mt8195-pwrap\", \"syscon\";\n \t\t\treg = <0 0x1cc04000 0 0x1000>;\n", "prefixes": [ "4/6" ] }