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GET /api/patches/2217880/?format=api
{ "id": 2217880, "url": "http://patchwork.ozlabs.org/api/patches/2217880/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260330-mtk-genio-720-ufs-v1-3-3bad8362ed70@baylibre.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330-mtk-genio-720-ufs-v1-3-3bad8362ed70@baylibre.com>", "list_archive_url": null, "date": "2026-03-30T20:42:15", "name": "[3/6] clk: mediatek: mt8189: add UFS clocks", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5bb0ee284e1d8f4d0ed9f17d5bb7981b52c9f312", "submitter": { "id": 87228, "url": "http://patchwork.ozlabs.org/api/people/87228/?format=api", "name": "David Lechner", "email": "dlechner@baylibre.com" }, "delegate": { "id": 161331, "url": "http://patchwork.ozlabs.org/api/users/161331/?format=api", "username": "dlech", "first_name": "David", "last_name": "Lechner", "email": "dlechner@baylibre.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260330-mtk-genio-720-ufs-v1-3-3bad8362ed70@baylibre.com/mbox/", "series": [ { "id": 498092, "url": "http://patchwork.ozlabs.org/api/series/498092/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=498092", "date": "2026-03-30T20:42:12", "name": "arm: mediatek: add UFS support for Genio 520/720 EVKs", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498092/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217880/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217880/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=B2Qs4TH4;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260330-mtk-genio-720-ufs-v1-3-3bad8362ed70@baylibre.com>", "References": "<20260330-mtk-genio-720-ufs-v1-0-3bad8362ed70@baylibre.com>", "In-Reply-To": "<20260330-mtk-genio-720-ufs-v1-0-3bad8362ed70@baylibre.com>", "To": "Neil Armstrong <neil.armstrong@linaro.org>,\n Bhupesh Sharma <bhupesh.linux@gmail.com>,\n Neha Malcom Francis <n-francis@ti.com>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,\n Tom Rini <trini@konsulko.com>, Lukasz Majewski <lukma@denx.de>", "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>", "X-Mailer": "b4 0.16-dev", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=3327; i=dlechner@baylibre.com;\n h=from:subject:message-id;\n bh=B/ABSxkbFpRwOSriHM19ZOZE83XdVIum2jPd1Rhapko=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpyuA+D8/K+Owu7Eg0oQkvMj5/eDFTXU5VI4sFJ\n mzanodg6oqJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCacrgPhYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/AELAH/0LqoLvMxjriJT2FhjUVHWa429tSDa84t2N4M+t\n n2QaVlnBUPu2jeRbg99/CguQtiKfhh/lkG/HN+M/2nrBhBEvUcAVk2mu5DXcJJA572Hkjv4Qln2\n wO2aUoxsicyGMezEX27GG5ddqAZ1YCeNFJ0t+V1ex48tgNtv7miTPhpSh2XVGhsr7XNLpVnsiDG\n EUCQpL8lC3+MeeuZSs3KxTbXL2TIi09XzU0R/jeo2LEEnPWZTqwfVkF68e3dh34guaebW5MGW57\n yZvAnmNz2oX8De6rgOhsHvEzx4pcSL1SejkNAAqoeFhMHjnl1a7KzsK8W501SM0OUPxSgGS4A/o\n iedg=", "X-Developer-Key": "i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add some clocks required for UFS on MT8189 targets.\n\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n drivers/clk/mediatek/clk-mt8189.c | 44 +++++++++++++++++++++++++++++++++++++++\n 1 file changed, 44 insertions(+)", "diff": "diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c\nindex 9e640059f11..d11947ee461 100644\n--- a/drivers/clk/mediatek/clk-mt8189.c\n+++ b/drivers/clk/mediatek/clk-mt8189.c\n@@ -1641,6 +1641,46 @@ static const struct mtk_gate mminfra_config_clks[] = {\n \tGATE_MMINFRA_CONFIG1(CLK_MMINFRA_GCE_26M, CLK_TOP_MMINFRA_SEL, 17),\n };\n \n+static const struct mtk_gate_regs ufscfg_ao_reg_cg_regs = {\n+\t.set_ofs = 0x8,\n+\t.clr_ofs = 0xc,\n+\t.sta_ofs = 0x4,\n+};\n+\n+#define GATE_UFSCFG_AO_REG_EXT(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &ufscfg_ao_reg_cg_regs, _shift, \\\n+\t\t CLK_GATE_SETCLR | CLK_PARENT_EXT)\n+\n+#define GATE_UFSCFG_AO_REG_TOP(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &ufscfg_ao_reg_cg_regs, _shift, \\\n+\t\t CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)\n+\n+static const struct mtk_gate ufs_config_ao_clks[] = {\n+\tGATE_UFSCFG_AO_REG_EXT(CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM, CLK_PAD_CLK26M, 1),\n+\tGATE_UFSCFG_AO_REG_EXT(CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0, CLK_PAD_CLK26M, 2),\n+\tGATE_UFSCFG_AO_REG_EXT(CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1, CLK_PAD_CLK26M, 3),\n+\tGATE_UFSCFG_AO_REG_TOP(CLK_UFSCFG_AO_REG_UNIPRO_SYS, CLK_TOP_U_SEL, 4),\n+\tGATE_UFSCFG_AO_REG_EXT(CLK_UFSCFG_AO_REG_U_SAP_CFG, CLK_PAD_CLK26M, 5),\n+\tGATE_UFSCFG_AO_REG_TOP(CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS, CLK_TOP_AXI_U_SEL, 6),\n+};\n+\n+static const struct mtk_gate_regs ufscfg_pdn_reg_cg_regs = {\n+\t.set_ofs = 0x8,\n+\t.clr_ofs = 0xc,\n+\t.sta_ofs = 0x4,\n+};\n+\n+#define GATE_UFSCFG_PDN_REG(_id, _parent, _shift) \\\n+\tGATE_FLAGS(_id, _parent, &ufscfg_pdn_reg_cg_regs, _shift, \\\n+\t\t CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)\n+\n+static const struct mtk_gate ufs_config_pdn_clks[] = {\n+\tGATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_UFS, CLK_TOP_U_SEL, 0),\n+\tGATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_AES, CLK_TOP_AES_UFSFDE_SEL, 1),\n+\tGATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_U_AHB, CLK_TOP_AXI_U_SEL, 3),\n+\tGATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_U_AXI, CLK_TOP_MEM_SUB_U_SEL, 5),\n+};\n+\n static const struct mtk_parent vlp_26m_oscd10_parents[] = {\n \tEXT_PARENT(CLK_PAD_CLK26M),\n \tTOP_PARENT(CLK_TOP_OSC_D10),\n@@ -1955,6 +1995,8 @@ GATE_CLK_DATA(perao_clks);\n GATE_CLK_DATA(imp_clks);\n GATE_CLK_DATA(mm_clks);\n GATE_CLK_DATA(mminfra_config_clks);\n+GATE_CLK_DATA(ufs_config_ao_clks);\n+GATE_CLK_DATA(ufs_config_pdn_clks);\n GATE_CLK_DATA(vlpcfg_ao_clks);\n \n static const struct udevice_id of_match_mt8189_clk_gate[] = {\n@@ -1962,6 +2004,8 @@ static const struct udevice_id of_match_mt8189_clk_gate[] = {\n \t{ .compatible = \"mediatek,mt8189-iic-wrap\", .data = (ulong)&imp_clks_data },\n \t{ .compatible = \"mediatek,mt8189-dispsys\", .data = (ulong)&mm_clks_data },\n \t{ .compatible = \"mediatek,mt8189-mm-infra\", .data = (ulong)&mminfra_config_clks_data },\n+\t{ .compatible = \"mediatek,mt8189-ufscfg-ao\", .data = (ulong)&ufs_config_ao_clks_data },\n+\t{ .compatible = \"mediatek,mt8189-ufscfg-pdn\", .data = (ulong)&ufs_config_pdn_clks_data },\n \t{ .compatible = \"mediatek,mt8189-vlpcfg-ao\", .data = (ulong)&vlpcfg_ao_clks_data },\n \t{ }\n };\n", "prefixes": [ "3/6" ] }