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GET /api/patches/2217851/?format=api
{ "id": 2217851, "url": "http://patchwork.ozlabs.org/api/patches/2217851/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260330185236.1905636-2-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330185236.1905636-2-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-30T18:52:32", "name": "[PULL,1/5] target/arm: Don't skip access flag fault for AccessType_AT", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "9a2324ce67b7e1f4ef10ec3692d80424c6639f25", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260330185236.1905636-2-peter.maydell@linaro.org/mbox/", "series": [ { "id": 498079, "url": "http://patchwork.ozlabs.org/api/series/498079/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498079", "date": "2026-03-30T18:52:33", "name": "[PULL,1/5] target/arm: Don't skip access flag fault for AccessType_AT", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498079/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217851/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217851/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=OUgWogsH;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fl0ks4GV2z1xtJ\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 31 Mar 2026 05:53:25 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w7HjM-0007i2-VQ; Mon, 30 Mar 2026 14:53:02 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w7HjB-0007h4-Nb\n for qemu-devel@nongnu.org; Mon, 30 Mar 2026 14:52:45 -0400", "from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w7Hj9-00038d-7Y\n for qemu-devel@nongnu.org; Mon, 30 Mar 2026 14:52:45 -0400", "by mail-wm1-x32e.google.com with SMTP id\n 5b1f17b1804b1-48374014a77so58652145e9.3\n for <qemu-devel@nongnu.org>; Mon, 30 Mar 2026 11:52:41 -0700 (PDT)", "from lanath.. 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helo=mail-wm1-x32e.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Zenghui Yu <zenghui.yu@linux.dev>\n\nAs per the pseudo code from DDI0487 M.a.a (on J1-16021) AArch64.S1Walk():\n\n // Check descriptor AF bit\n elsif (descriptor<10> == '0' && walkparams.ha == '0' &&\n (!accdesc.acctype IN {AccessType_DC, AccessType_IC} ||\n boolean IMPLEMENTATION_DEFINED \"Generate access flag fault on IC/DC operations\")) then\n fault.statuscode = Fault_AccessFlag;\n\nan access flag fault should be generated for AccessType_AT, if the AF bit\nis 0 and !param.ha.\n\nBesides, we should continue to not raise the access flag fault for\nin_debug = true which is what we've been doing previously (before commit\nefebeec13d07) for LPAE and is what intention of the debugger access\ncodepath is.\n\nCc: qemu-stable@nongnu.org\nFixes: efebeec13d07 (\"target/arm: Skip AF and DB updates for AccessType_AT\")\nSigned-off-by: Zenghui Yu <zenghui.yu@linux.dev>\nMessage-id: 20260324160321.96347-1-zenghui.yu@linux.dev\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/ptw.c | 18 ++++++++++--------\n 1 file changed, 10 insertions(+), 8 deletions(-)", "diff": "diff --git a/target/arm/ptw.c b/target/arm/ptw.c\nindex e289f88124..08a76bd3f1 100644\n--- a/target/arm/ptw.c\n+++ b/target/arm/ptw.c\n@@ -2118,6 +2118,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,\n descaddr &= ~(hwaddr)(page_size - 1);\n descaddr |= (address & (page_size - 1));\n \n+ if (likely(!ptw->in_debug)) {\n+ /* Check descriptor AF bit */\n+ if (!(descriptor & (1 << 10)) && !param.ha) {\n+ fi->type = ARMFault_AccessFlag;\n+ goto do_fault;\n+ }\n+ }\n+\n /*\n * For AccessType_AT, DB is not updated (AArch64.SetDirtyFlag),\n * and it is IMPLEMENTATION DEFINED whether AF is updated\n@@ -2127,15 +2135,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,\n /*\n * Access flag.\n * If HA is enabled, prepare to update the descriptor below.\n- * Otherwise, pass the access fault on to software.\n */\n- if (!(descriptor & (1 << 10))) {\n- if (param.ha) {\n- new_descriptor |= 1 << 10; /* AF */\n- } else {\n- fi->type = ARMFault_AccessFlag;\n- goto do_fault;\n- }\n+ if (!(descriptor & (1 << 10)) && param.ha) {\n+ new_descriptor |= 1 << 10; /* AF */\n }\n \n /*\n", "prefixes": [ "PULL", "1/5" ] }