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GET /api/patches/2217830/?format=api
{ "id": 2217830, "url": "http://patchwork.ozlabs.org/api/patches/2217830/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260330171419.1117817-7-aswin.murugan@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330171419.1117817-7-aswin.murugan@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-03-30T17:14:18", "name": "[v3,6/7] test: dm: add comprehensive tests for NVMEM bit field operations", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ead137e9c59e81cbe08157a3713ff193bad28715", "submitter": { "id": 90811, "url": "http://patchwork.ozlabs.org/api/people/90811/?format=api", "name": "Aswin Murugan", "email": "aswin.murugan@oss.qualcomm.com" }, "delegate": { "id": 151538, "url": "http://patchwork.ozlabs.org/api/users/151538/?format=api", "username": "kcxt", "first_name": "Casey", "last_name": "Connolly", "email": "casey.connolly@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260330171419.1117817-7-aswin.murugan@oss.qualcomm.com/mbox/", "series": [ { "id": 498069, "url": "http://patchwork.ozlabs.org/api/series/498069/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=498069", "date": "2026-03-30T17:14:12", "name": "qcom: Add NVMEM bitfield support and reboot���mode integration", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/498069/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217830/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217830/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=nRhuzrCk;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=fCPv+mw2;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"nRhuzrCk\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"fCPv+mw2\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fkyZJ677mz1yG7\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 31 Mar 2026 04:15:52 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id AD3FC8409B;\n\tMon, 30 Mar 2026 19:15:34 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 8125A84099; Mon, 30 Mar 2026 19:15:33 +0200 (CEST)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 1C2B684035\n for <u-boot@lists.denx.de>; Mon, 30 Mar 2026 19:15:30 +0200 (CEST)", "from pps.filterd (m0279872.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 62UF20Wg3722902\n for <u-boot@lists.denx.de>; Mon, 30 Mar 2026 17:15:29 GMT", "from mail-pf1-f197.google.com (mail-pf1-f197.google.com\n [209.85.210.197])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d7pvmssjd-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Mon, 30 Mar 2026 17:15:29 +0000 (GMT)", "by mail-pf1-f197.google.com with SMTP id\n d2e1a72fcca58-82c73627355so2906333b3a.2\n for <u-boot@lists.denx.de>; Mon, 30 Mar 2026 10:15:29 -0700 (PDT)", "from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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aswin.murugan@oss.qualcomm.com,\n casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, sjg@chromium.org, seanga2@gmail.com,\n sughosh.ganu@arm.com, ilias.apalodimas@linaro.org, gchan9527@gmail.com,\n mkorpershoek@kernel.org, hs@nabladev.com,\n marek.vasut+renesas@mailbox.org, msp@baylibre.com,\n dinesh.maniyam@altera.com, peng.fan@nxp.com, quentin.schulz@cherry.de,\n kever.yang@rock-chips.com, jamie.gibbons@microchip.com,\n justin@tidylabs.net, xypron.glpk@gmx.de, n-francis@ti.com, h-vm@ti.com,\n ycliang@andestech.com, u-boot@lists.denx.de, u-boot-qcom@groups.io", "Subject": "[PATCH v3 6/7] test: dm: add comprehensive tests for NVMEM bit field\n operations", "Date": "Mon, 30 Mar 2026 22:44:18 +0530", "Message-Id": "<20260330171419.1117817-7-aswin.murugan@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260330171419.1117817-1-aswin.murugan@oss.qualcomm.com>", "References": "<20260330171419.1117817-1-aswin.murugan@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-GUID": "SoYtsQYBhNw0HDYB7zeis2GY7Fmoj4bn", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMzMwMDE0MSBTYWx0ZWRfX/kRKVL+tu17b\n iWi2n4TkkZJ4orR3DdTHsBiw6PTpZCbl8BJ1k9qXOPAvvqmj9CPkkddkjm+EI7pG5nnhU4A0DbG\n WwflkS4V2UrRshYU45vDhSIFUqzI7OG0/0XF+ymfL7iJcVaMcuPUs3XyIsLEWYVPgB8C5hGquSr\n n8qk3IhBsUTYwZTRfmDau4JfacBigphww41p8sBzVsfBmdYG0lbN5UAfq5SxkOUdBm5Zs7y+do/\n Ly0/w77twxSTub1zbVauQ+HP8g5yAhmDIfkQf94Oa7uJM4ZJjWxwLTRESXOpTvgMzyP7OjZEdkR\n 7eQ6IM2gpNIW/f5t64Yxop7cYwtLxY1LoUxEIMk0ij3wEkp9uNMx0t0tCD0orwAKYvAyW8H5vMc\n prSFmS4Iwaq3Usak/yPzc+sdcsbwt9BRp9Dgqe/+m+QDp1jL9arPthnTjjsiZGdVAz4AoPooaco\n 9yn4PpZqvPFlkMbbj2Q==", "X-Proofpoint-ORIG-GUID": "SoYtsQYBhNw0HDYB7zeis2GY7Fmoj4bn", "X-Authority-Analysis": "v=2.4 cv=S9rUAYsP c=1 sm=1 tr=0 ts=69caafb1 cx=c_pps\n a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8\n a=2eTTHJJ0khsgQslqM3AA:9 a=2VI0MkxyNR6bbpdq8BZq:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-03-29_05,2026-03-28_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n malwarescore=0 bulkscore=0 clxscore=1015 adultscore=0 spamscore=0\n suspectscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501\n impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001\n definitions=main-2603300141", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add a mock I2C EEPROM device (nvmem-test@50) to the sandbox device tree\nto support NVMEM bit field operation testing.\n\nAdd test coverage for NVMEM bit field read and write operations to\nvalidate the new bit field support in the NVMEM subsystem.\n\nTest cases include:\n- 1-byte cell with 7-bit field\n- 2-byte cell with 12-bit field spanning a byte boundary\n- 4-byte cell without a bit field (legacy byte-level access)\n- 4-byte cell with a 16-bit field in the upper 2 bytes\n\nError validation tests cover:\n- Bit field exceeding the cell size\n- Bit field exceeding the 32-bit maximum\n- Invalid bit_offset and nbits combinations\n- Buffer size mismatch in non-bit-field mode\n\nThe tests verify:\n- Correct bit extraction during read operations\n- Read-modify-write behavior preserving unrelated bits\n- Proper error handling for invalid configurations\n\nSigned-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>\n---\n arch/sandbox/dts/test.dts | 12 ++++\n test/dm/reboot-mode.c | 137 ++++++++++++++++++++++++++++++++++++++\n 2 files changed, 149 insertions(+)", "diff": "diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts\nindex 762c1d9bbe2..4fb4d0a8ef5 100644\n--- a/arch/sandbox/dts/test.dts\n+++ b/arch/sandbox/dts/test.dts\n@@ -959,6 +959,11 @@\n \t\t\t\tsandbox,filename = \"i2c.bin\";\n \t\t\t\tsandbox,size = <256>;\n \t\t\t};\n+\t\t\temul_nvmem_test: emul-nvmem-test {\n+\t\t\t\tcompatible = \"sandbox,i2c-eeprom\";\n+\t\t\t\tsandbox,filename = \"nvmem-test.bin\";\n+\t\t\t\tsandbox,size = <256>;\n+\t\t\t};\n \t\t\temul0: emul0 {\n \t\t\t\tcompatible = \"sandbox,i2c-rtc-emul\";\n \t\t\t};\n@@ -976,6 +981,13 @@\n \t\t\treg = <0x41>;\n \t\t\tsandbox,emul = <&emul_pmic1>;\n \t\t};\n+\n+\t\t/* Mock NVMEM device for bit field testing */\n+\t\tnvmem-test@50 {\n+\t\t\treg = <0x50>;\n+\t\t\tcompatible = \"i2c-eeprom\";\n+\t\t\tsandbox,emul = <&emul_nvmem_test>;\n+\t\t};\n \t};\n \n \ti3c0 {\ndiff --git a/test/dm/reboot-mode.c b/test/dm/reboot-mode.c\nindex 9a3b2bf0a43..8e6634339a8 100644\n--- a/test/dm/reboot-mode.c\n+++ b/test/dm/reboot-mode.c\n@@ -15,6 +15,8 @@\n #include <test/ut.h>\n #include <rtc.h>\n #include <linux/byteorder/generic.h>\n+#include <nvmem.h>\n+#include <misc.h>\n \n static int dm_test_reboot_mode_gpio(struct unit_test_state *uts)\n {\n@@ -66,3 +68,138 @@ static int dm_test_reboot_mode_rtc(struct unit_test_state *uts)\n }\n DM_TEST(dm_test_reboot_mode_rtc,\n \tUTF_PROBE_TEST | UTF_SCAN_FDT | UTF_FLAT_TREE);\n+\n+static int nvmem_test_write_raw(struct udevice *dev, uint offset,\n+\t\t\t\tconst void *buf, uint size)\n+{\n+\treturn misc_write(dev, offset, buf, size);\n+}\n+\n+static int nvmem_test_read_raw(struct udevice *dev, uint offset,\n+\t\t\t void *buf, uint size)\n+{\n+\treturn misc_read(dev, offset, buf, size);\n+}\n+\n+/* Test NVMEM bit field operations */\n+static int dm_test_nvmem_bitfield(struct unit_test_state *uts)\n+{\n+\tstruct udevice *nvmem_dev;\n+\tstruct nvmem_cell cell;\n+\tu32 value;\n+\tu8 hw_value_u8;\n+\tu16 hw_value_u16;\n+\tu32 hw_value_u32;\n+\n+\tut_assertok(uclass_get_device_by_name(UCLASS_I2C_EEPROM,\n+\t\t\t\t\t \"nvmem-test@50\", &nvmem_dev));\n+\n+\tcell.nvmem = nvmem_dev;\n+\n+\t/* Test reg = <0x0 0x1>; bits = <1 7>: */\n+\tcell.offset = 0x0;\n+\tcell.size = 1;\n+\tcell.bit_offset = 1;\n+\tcell.nbits = 7;\n+\thw_value_u8 = 0x01;\n+\tut_assertok(nvmem_test_write_raw(nvmem_dev, cell.offset, &hw_value_u8, 1));\n+\tvalue = 0x7F;\n+\tut_assertok(nvmem_cell_write(&cell, &value, sizeof(value)));\n+\tvalue = 0;\n+\tut_assertok(nvmem_cell_read(&cell, &value, sizeof(value)));\n+\tut_asserteq(0x7F, value);\n+\tut_assertok(nvmem_test_read_raw(nvmem_dev, cell.offset, &hw_value_u8, 1));\n+\tut_asserteq(0xFF, hw_value_u8);\n+\n+\t/* Test reg = <0x18 0x4>; bits = <4 12>: Spanning byte boundary */\n+\tcell.offset = 0x18;\n+\tcell.size = 4;\n+\tcell.bit_offset = 4;\n+\tcell.nbits = 12;\n+\thw_value_u16 = 0x000F;\n+\tut_assertok(nvmem_test_write_raw(nvmem_dev, cell.offset, (u8 *)&hw_value_u16, 2));\n+\tvalue = 0xFFF;\n+\tut_assertok(nvmem_cell_write(&cell, &value, sizeof(value)));\n+\tut_assertok(nvmem_test_read_raw(nvmem_dev, cell.offset, (u8 *)&hw_value_u16, 2));\n+\tut_asserteq(0xFFFF, hw_value_u16);\n+\n+\t/* Test reg = <0x9 0x4>: Full 4-byte access without bit field */\n+\tcell.offset = 0x9;\n+\tcell.bit_offset = 0;\n+\tcell.nbits = 0;\n+\tvalue = 0x12345678;\n+\tut_assertok(nvmem_cell_write(&cell, &value, sizeof(value)));\n+\tvalue = 0;\n+\tut_assertok(nvmem_cell_read(&cell, &value, sizeof(value)));\n+\tut_asserteq(0x12345678, value);\n+\n+\t/* Test reg = <0xc 0x4>; bits = <16 16>: Upper 2 bytes */\n+\tcell.offset = 0xc;\n+\tcell.bit_offset = 16;\n+\tcell.nbits = 16;\n+\thw_value_u32 = 0x0000FFFF;\n+\tut_assertok(nvmem_test_write_raw(nvmem_dev, cell.offset, (u8 *)&hw_value_u32, 4));\n+\tvalue = 0xFFFF;\n+\tut_assertok(nvmem_cell_write(&cell, &value, sizeof(value)));\n+\tut_assertok(nvmem_test_read_raw(nvmem_dev, cell.offset, (u8 *)&hw_value_u32, 4));\n+\tut_asserteq(0xFFFFFFFF, hw_value_u32);\n+\n+\treturn 0;\n+}\n+DM_TEST(dm_test_nvmem_bitfield,\n+\tUTF_PROBE_TEST | UTF_SCAN_FDT | UTF_FLAT_TREE);\n+\n+/* Test NVMEM error handling for invalid configurations */\n+static int dm_test_nvmem_bitfield_errors(struct unit_test_state *uts)\n+{\n+\tstruct udevice *nvmem_dev;\n+\tstruct nvmem_cell cell;\n+\tu32 value;\n+\tint ret;\n+\n+\tut_assertok(uclass_get_device_by_name(UCLASS_I2C_EEPROM,\n+\t\t\t\t\t \"nvmem-test@50\", &nvmem_dev));\n+\n+\t/* Test bit field exceeding cell size */\n+\tcell.nvmem = nvmem_dev;\n+\tcell.offset = 0xd;\n+\tcell.size = 1;\n+\tcell.bit_offset = 0;\n+\tcell.nbits = 9;\n+\n+\tvalue = 0xFF;\n+\tret = nvmem_cell_write(&cell, &value, sizeof(value));\n+\tut_assert(ret < 0);\n+\n+\t/* Test bit field exceeding 32 bits */\n+\tcell.size = 4;\n+\tcell.bit_offset = 0;\n+\tcell.nbits = 33;\n+\n+\tret = nvmem_cell_write(&cell, &value, sizeof(value));\n+\tut_assert(ret < 0);\n+\n+\t/* Test invalid bit_offset + nbits */\n+\tcell.size = 1;\n+\tcell.bit_offset = 7;\n+\tcell.nbits = 2;\n+\n+\tret = nvmem_cell_write(&cell, &value, sizeof(value));\n+\tut_assert(ret < 0);\n+\n+\t/* Test nbits=0 requires buffer size == cell size */\n+\tcell.size = 1;\n+\tcell.bit_offset = 0;\n+\tcell.nbits = 0;\n+\n+\tvalue = 0xFF;\n+\tret = nvmem_cell_write(&cell, &value, sizeof(value));\n+\tut_assert(ret < 0);\n+\n+\tret = nvmem_cell_read(&cell, &value, sizeof(value));\n+\tut_assert(ret < 0);\n+\n+\treturn 0;\n+}\n+DM_TEST(dm_test_nvmem_bitfield_errors,\n+\tUTF_PROBE_TEST | UTF_SCAN_FDT | UTF_FLAT_TREE);\n", "prefixes": [ "v3", "6/7" ] }