Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2217826/?format=api
{ "id": 2217826, "url": "http://patchwork.ozlabs.org/api/patches/2217826/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260330171419.1117817-3-aswin.murugan@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330171419.1117817-3-aswin.murugan@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-03-30T17:14:14", "name": "[v3,2/7] misc: qcom: Add Qualcomm SPMI SDAM NVMEM driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f9f7c573e1ca8e41c18ead8f29f7da5395a80bea", "submitter": { "id": 90811, "url": "http://patchwork.ozlabs.org/api/people/90811/?format=api", "name": "Aswin Murugan", "email": "aswin.murugan@oss.qualcomm.com" }, "delegate": { "id": 151538, "url": "http://patchwork.ozlabs.org/api/users/151538/?format=api", "username": "kcxt", "first_name": "Casey", "last_name": "Connolly", "email": "casey.connolly@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260330171419.1117817-3-aswin.murugan@oss.qualcomm.com/mbox/", "series": [ { "id": 498069, "url": "http://patchwork.ozlabs.org/api/series/498069/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=498069", "date": "2026-03-30T17:14:12", "name": "qcom: Add NVMEM bitfield support and reboot���mode integration", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/498069/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217826/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217826/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=izMOBW61;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=ckvVZ9J7;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"izMOBW61\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"ckvVZ9J7\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fkyYV1ZJ9z1yG7\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 31 Mar 2026 04:15:10 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 3EE0784035;\n\tMon, 30 Mar 2026 19:15:07 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id C92078403D; Mon, 30 Mar 2026 19:15:03 +0200 (CEST)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 400C483DBF\n for <u-boot@lists.denx.de>; Mon, 30 Mar 2026 19:15:00 +0200 (CEST)", "from pps.filterd (m0279868.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 62UGNrQb1402844\n for <u-boot@lists.denx.de>; Mon, 30 Mar 2026 17:14:58 GMT", "from mail-pf1-f198.google.com (mail-pf1-f198.google.com\n [209.85.210.198])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d7r4h9kcu-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Mon, 30 Mar 2026 17:14:58 +0000 (GMT)", "by mail-pf1-f198.google.com with SMTP id\n d2e1a72fcca58-82c699d8caaso8756261b3a.1\n for <u-boot@lists.denx.de>; Mon, 30 Mar 2026 10:14:58 -0700 (PDT)", "from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19])\n by smtp.gmail.com with ESMTPSA id\n d2e1a72fcca58-82ca8626518sm7349777b3a.52.2026.03.30.10.14.49\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 30 Mar 2026 10:14:56 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2", "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n content-transfer-encoding:date:from:in-reply-to:message-id\n :mime-version:references:subject:to; s=qcppdkim1; bh=iy80Js7bnV+\n SnqQqkACVhIrdRYyTidBddHsEI8ZZoTE=; b=izMOBW61mRcY2TIrmZgmhewwgFs\n pz2QXwgyX28AkMDmrBAaRd0lT66OaGcJ+OqbMxXhaeqpDIFVP7lLQP4aMOKY6Wuw\n E/GVRZlSasok7vvqhwEhoZVFuZgZmRpMTDpT42260CWz+HEy7wVGurIyKMBTx4jo\n YReoUoHIqGXjefneTXwhjxz5dStMn7zdP7RKOee4GccwLK/xRzLbllICOeKi1xHy\n /704ODvtJ4wRef5/xjeksYiRkqQOjKGoFRrUtQU553xk7v+EewF5+KXs3nNhNy0A\n sZytwrRhG/T+RHPmA175mfldCrbqqwfq66kz3hhK/78guQUfcTKj3qv/E9A==", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1774890897; x=1775495697; darn=lists.denx.de;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=iy80Js7bnV+SnqQqkACVhIrdRYyTidBddHsEI8ZZoTE=;\n b=ckvVZ9J7cW6lpNa5IY9+EPfAtzGly01Erp7xdyIxdHarCVbEsdzRN2pvCgIHL94yVv\n OI0FHAV0Nu5OeFBEyiY4aZG8KoYkNLqubZHbbSfskDSiFZe+Wum0LSS1E7F1UFbZ9QX7\n 9PvSWfssESBs9379PYzzPOezT0GsJOwl5JqrQmmVq5KJQJvQV27XtaRm1qarSdnn/nEM\n rBlOCo9Y6vtd0QIowu4Hn3SicER+AIBtl5lIc5TKZcjvOtsXEpyy+6yXrwR1aSe07cFp\n HqwG3j01stgVI0GImv7hMw0Ys1W7uU7Vvx25pihGPfN5zu6Ah4fBVm4KGxZ9PxLi5cmo\n o68w==" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774890897; x=1775495697;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=iy80Js7bnV+SnqQqkACVhIrdRYyTidBddHsEI8ZZoTE=;\n b=D9uhZG0Hz2hcjmj0lX4yB86AkZXZM2/8h4WWVkM2zqj0NvxSWYhb0f9sxfkONrY105\n 2917V1O2erietCg7QAzIoB6FYQB31VplfDRRtl6K77daBdCBpspTho9c8ydIarLRzi7S\n moOZAdN1QH040rFTouzPySCMuNAmAToZy/FsJLmWEK+FZLJ2poLyyHIanSRm5BPTKm4o\n WE0CDfO9ugJTnfhHUbIA1fADfaFlyPWbO2OBrXix2T4rhZVEposRSl0AuRB9BEu0Ob9I\n 5aa1akjLE5rENrheMt7r6UuLD17llOz03NSeGr1lV+XgphNU8697Xv8yJsR1IwCoNJeg\n LVHg==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCU1B+ydJ46iMcizmQY8yL/qCHoIsXr21duRo7nc5nnStdvmlBjJM0ib9Yeq4RsjfL+WCuzOuxA=@lists.denx.de", "X-Gm-Message-State": "AOJu0Yy1fHro2XZeZtWwhC1wSvRSYAAkuZKdNig4L46MpeF8wupHo+g+\n 1i5R+gro8tYqH5B3gXlF5wgBubQD99aBBPHlg8g67js1HGBr79Eaa4+5AdaCcbeuDDNcmLBlBfl\n hG+VvcXSw1O+EBjh/uLENWjc257Ic1fcneo0QZcYQ28w/Vcpq0Wf5O65z", "X-Gm-Gg": "ATEYQzz8t27TBwyrVt0r1eMLYT5KUj4aAqpwd0T4cLV8jm6LZADhMePZAXNX9njf4pY\n MwofZhxC4IOuT3Xqkis/jDCiBh124+loRZT58bjJEh7Ucx6KeFHN0XHzmoOazQ3kNVnAIO1+W//\n H8e7l3+jvINtpxB9c4zxFhSLI9aDXvu/OXnQv+MEWcQHgtmiJjw+VmOkFPCk/BkZgYxRQnNvXWA\n xaqAWa1t6/JYMnotZXfQRUhHKGPpnFLKsC4TUP6f05JPdx6u1t77AxOub2eHUfuViYbYYQYtFbz\n wCX/oaLyEXcbUCyh1G9SJGeV3/t1H8LClJ0Yq0V4HZM/n2w4hWojyn2tk+va4bVZwwd2r3Orcgr\n A4ix1GsiEYmwOsIg3VVADf6B5+J5jOFTglD+YfAr6etMs6+Y6wpHVjeVAkIHrrJqkciBKOqYIoE\n 47mlWnrgeDfUnOwguV1MBJZnZU9fCMG/VKFrzXVfZ3", "X-Received": [ "by 2002:a05:6a00:2e9c:b0:824:a635:4181 with SMTP id\n d2e1a72fcca58-82c95afa7femr13999619b3a.15.1774890897233;\n Mon, 30 Mar 2026 10:14:57 -0700 (PDT)", "by 2002:a05:6a00:2e9c:b0:824:a635:4181 with SMTP id\n d2e1a72fcca58-82c95afa7femr13999573b3a.15.1774890896707;\n Mon, 30 Mar 2026 10:14:56 -0700 (PDT)" ], "From": "Aswin Murugan <aswin.murugan@oss.qualcomm.com>", "To": "trini@konsulko.com, aswin.murugan@oss.qualcomm.com,\n casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, sjg@chromium.org, seanga2@gmail.com,\n sughosh.ganu@arm.com, ilias.apalodimas@linaro.org, gchan9527@gmail.com,\n mkorpershoek@kernel.org, hs@nabladev.com,\n marek.vasut+renesas@mailbox.org, msp@baylibre.com,\n dinesh.maniyam@altera.com, peng.fan@nxp.com, quentin.schulz@cherry.de,\n kever.yang@rock-chips.com, jamie.gibbons@microchip.com,\n justin@tidylabs.net, xypron.glpk@gmx.de, n-francis@ti.com, h-vm@ti.com,\n ycliang@andestech.com, u-boot@lists.denx.de, u-boot-qcom@groups.io", "Subject": "[PATCH v3 2/7] misc: qcom: Add Qualcomm SPMI SDAM NVMEM driver", "Date": "Mon, 30 Mar 2026 22:44:14 +0530", "Message-Id": "<20260330171419.1117817-3-aswin.murugan@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260330171419.1117817-1-aswin.murugan@oss.qualcomm.com>", "References": "<20260330171419.1117817-1-aswin.murugan@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMzMwMDE0MCBTYWx0ZWRfXzzfdjKuQmvgU\n KG5QW0RYTM09NXNjtjS4FKctvUgPX5DNCOmpLuH5admfY3ykfQrEY98RhximB/RF4sEl02YsmVg\n svlQUfqzGwUgpx0S4eu25hAAG8G/TcQa2ETFrTo1aNNEAH0KDxvALOg4qapIvOMiXjJYhCWpKFU\n PII4jgIWGZ7cvyusyR/8OmOCDljbNGi4tBd2d8JmwlzXE+kCWYSN5xFvAAfUZGx8FQcKAEY3LN8\n LAKwy4sH4xA8/lw+QfYmluJW2bL1+n66cv0jDxv944wEI1m5bG/35i0GL+S/+OJ1GMkd0MvrFEC\n 7AjlJqJtwDihOrbakpyrFfhZWwfxPaWGBd7QnpbKPnAzlPkojCeH31NERPlzLHW0M4XFN6NwC3z\n iVWlxFVYHiuvCZ8SWj5bCOTuVHCPH7Uts9+HMBGlmYIImFMicYcrm1cHMl4NpzoYWXl/P0YDWjR\n Xm4Xo5M+8/Z6TJnT9BA==", "X-Proofpoint-ORIG-GUID": "Le3ai4oCEqwbuVprx2gGYlR4eOXLBK5r", "X-Authority-Analysis": "v=2.4 cv=PI0COPqC c=1 sm=1 tr=0 ts=69caaf92 cx=c_pps\n a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8\n a=xi5d6GjbYgY_MreKiQQA:9 a=IoOABgeZipijB_acs4fv:22", "X-Proofpoint-GUID": "Le3ai4oCEqwbuVprx2gGYlR4eOXLBK5r", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-03-29_05,2026-03-28_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 phishscore=0 adultscore=0 impostorscore=0 malwarescore=0\n lowpriorityscore=0 spamscore=0 suspectscore=0 clxscore=1015 bulkscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603300140", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Qualcomm PMICs include SDAM (Shared Direct Access Memory) regions which\nare used to store persistent data like reboot reasons that must survive\nacross reboots.\n\nWithout this driver, U-Boot cannot access PMIC storage, preventing\nreboot-to-bootloader functionality and other features that rely on\npersistent state.\n\nAdd qcom-spmi-sdam driver that:\n- Probes SDAM regions from device tree compatible \"qcom,spmi-sdam\"\n- Implements NVMEM provider interface for standard cell-based access\n- Uses SPMI register read/write operations for data access\n\nThis enables reboot-mode and other subsystems to access PMIC storage\nthrough standard NVMEM APIs.\n\nSigned-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>\n---\nChanges in v3:\n1. No change in v3\n---\n drivers/misc/Kconfig | 8 ++\n drivers/misc/Makefile | 1 +\n drivers/misc/qcom-spmi-sdam.c | 200 ++++++++++++++++++++++++++++++++++\n 3 files changed, 209 insertions(+)\n create mode 100644 drivers/misc/qcom-spmi-sdam.c", "diff": "diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig\nindex a0aa290480e..8ace19c1128 100644\n--- a/drivers/misc/Kconfig\n+++ b/drivers/misc/Kconfig\n@@ -92,6 +92,14 @@ config QCOM_GENI\n \t for providing a common interface for various peripherals like UART, I2C, SPI,\n \t etc.\n \n+config QCOM_SPMI_SDAM\n+\tbool \"Qualcomm SPMI SDAM NVMEM driver\"\n+\tdepends on MISC && NVMEM && SPMI\n+\thelp\n+\t Enable support for Qualcomm SPMI SDAM (Shared Direct Access Memory) blocks\n+\t as NVMEM providers. This driver support accessing SDAM blocks in PMICs\n+\t for reboot reason functionality and other NVMEM use cases.\n+\n config ROCKCHIP_EFUSE\n bool \"Rockchip e-fuse support\"\n \tdepends on MISC\ndiff --git a/drivers/misc/Makefile b/drivers/misc/Makefile\nindex 1d950f7a0ab..bed2cb63fcb 100644\n--- a/drivers/misc/Makefile\n+++ b/drivers/misc/Makefile\n@@ -68,6 +68,7 @@ obj-$(CONFIG_QFW_SMBIOS) += qfw_smbios.o\n obj-$(CONFIG_SANDBOX) += qfw_sandbox.o\n endif\n obj-$(CONFIG_QCOM_GENI) += qcom_geni.o\n+obj-$(CONFIG_QCOM_SPMI_SDAM) += qcom-spmi-sdam.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_EFUSE) += rockchip-efuse.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_OTP) += rockchip-otp.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_IODOMAIN) += rockchip-io-domain.o\ndiff --git a/drivers/misc/qcom-spmi-sdam.c b/drivers/misc/qcom-spmi-sdam.c\nnew file mode 100644\nindex 00000000000..482156f3bb7\n--- /dev/null\n+++ b/drivers/misc/qcom-spmi-sdam.c\n@@ -0,0 +1,200 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Qualcomm SPMI SDAM NVMEM driver\n+ *\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#include <dm.h>\n+#include <misc.h>\n+#include <dm/device_compat.h>\n+#include <dm/uclass.h>\n+#include <spmi/spmi.h>\n+\n+#define PID_SHIFT 8\n+#define PID_MASK (0xFF << PID_SHIFT)\n+#define REG_MASK 0xFF\n+#define SDAM_SIZE 0x100\n+\n+struct qcom_sdam_priv {\n+\tu32 base;\n+\tu32 size;\n+\tu32 pmic_usid;\n+\tstruct udevice *spmi_dev;\n+};\n+\n+/**\n+ * qcom_sdam_find_spmi_pmic() - Find SPMI controller and PMIC USID\n+ * @dev: SDAM device\n+ * @spmi_dev: Returns SPMI controller device\n+ * @pmic_usid: Returns PMIC USID for SPMI access\n+ *\n+ * Walks up the device tree to find the PMIC parent and SPMI controller.\n+ * Supports both direct SDAM under PMIC and virtual NVMEM under PON.\n+ *\n+ * Return: 0 on success, negative error code on failure\n+ */\n+static int qcom_sdam_find_spmi_pmic(struct udevice *dev,\n+\t\t\t\t struct udevice **spmi_dev,\n+\t\t\t\t u32 *pmic_usid)\n+{\n+\tstruct udevice *pmic_dev = dev->parent;\n+\tint ret;\n+\n+\tif (!pmic_dev) {\n+\t\tdev_err(dev, \"No parent device found\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tret = dev_read_u32_index(pmic_dev, \"reg\", 0, pmic_usid);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Could not read PMIC USID: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t*spmi_dev = pmic_dev->parent;\n+\tif (!*spmi_dev || (*spmi_dev)->uclass->uc_drv->id != UCLASS_SPMI) {\n+\t\tdev_err(dev, \"Could not find SPMI controller\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tdev_dbg(dev, \"Found PMIC USID=%d, SPMI controller=%s\\n\",\n+\t\t*pmic_usid, (*spmi_dev)->name);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * qcom_sdam_read() - Read data from SDAM/NVMEM region\n+ * @dev: MISC device (SDAM)\n+ * @offset: Offset within SDAM/NVMEM region\n+ * @buf: Buffer to read data into\n+ * @size: Number of bytes to read\n+ *\n+ * Uses the same SPMI register access pattern as pmic_qcom.c driver\n+ * for consistency and reliability. This function is called by the\n+ * NVMEM subsystem via misc_read().\n+ *\n+ * Return: number of bytes read on success, negative error code on failure\n+ */\n+static int qcom_sdam_read(struct udevice *dev, int offset,\n+\t\t\t void *buf, int size)\n+{\n+\tstruct qcom_sdam_priv *priv = dev_get_priv(dev);\n+\tu8 *buffer = buf;\n+\tint ret;\n+\n+\tif (offset + size > priv->size)\n+\t\treturn -EINVAL;\n+\n+\tfor (size_t i = 0; i < size; i++) {\n+\t\tu32 reg = priv->base + offset + i;\n+\n+\t\tret = spmi_reg_read(priv->spmi_dev, priv->pmic_usid,\n+\t\t\t\t (reg & PID_MASK) >> PID_SHIFT,\n+\t\t\t\t reg & REG_MASK);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(dev, \"SPMI read failed at 0x%x: %d\\n\", reg, ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tbuffer[i] = ret;\n+\n+\t\tdev_dbg(dev, \"Read 0x%02x from 0x%x (PID=0x%02x REG=0x%02x)\\n\",\n+\t\t\tbuffer[i], reg, (reg & PID_MASK) >> PID_SHIFT, reg & REG_MASK);\n+\t}\n+\n+\treturn size;\n+}\n+\n+/**\n+ * qcom_sdam_write() - Write data to SDAM/NVMEM region\n+ * @dev: MISC device (SDAM)\n+ * @offset: Offset within SDAM/NVMEM region\n+ * @buf: Buffer containing data to write\n+ * @size: Number of bytes to write\n+ *\n+ * Uses the same SPMI register access pattern as pmic_qcom.c driver\n+ * for consistency and reliability. This function is called by the\n+ * NVMEM subsystem via misc_write().\n+ *\n+ * Return: number of bytes written on success, negative error code on failure\n+ */\n+static int qcom_sdam_write(struct udevice *dev, int offset,\n+\t\t\t const void *buf, int size)\n+{\n+\tstruct qcom_sdam_priv *priv = dev_get_priv(dev);\n+\tconst u8 *buffer = buf;\n+\tint ret;\n+\n+\tif (offset + size > priv->size)\n+\t\treturn -EINVAL;\n+\n+\tfor (size_t i = 0; i < size; i++) {\n+\t\tu32 reg = priv->base + offset + i;\n+\n+\t\tret = spmi_reg_write(priv->spmi_dev, priv->pmic_usid,\n+\t\t\t\t (reg & PID_MASK) >> PID_SHIFT,\n+\t\t\t\t reg & REG_MASK,\n+\t\t\t\t buffer[i]);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(dev, \"SPMI write failed at 0x%x: %d\\n\", reg, ret);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tdev_dbg(dev, \"Wrote 0x%02x to 0x%x (PID=0x%02x REG=0x%02x)\\n\",\n+\t\t\tbuffer[i], reg, (reg & PID_MASK) >> PID_SHIFT, reg & REG_MASK);\n+\t}\n+\n+\treturn size;\n+}\n+\n+static const struct misc_ops qcom_sdam_ops = {\n+\t.read = qcom_sdam_read,\n+\t.write = qcom_sdam_write,\n+};\n+\n+/**\n+ * qcom_sdam_probe() - Probe SDAM device and register as NVMEM provider\n+ * @dev: SDAM device\n+ *\n+ * Handles both real SDAM blocks and virtual NVMEM under PON blocks.\n+ * For virtual NVMEM, adds the parent PON base address to the offset.\n+ *\n+ * Return: 0 on success, negative error code on failure\n+ */\n+static int qcom_sdam_probe(struct udevice *dev)\n+{\n+\tstruct qcom_sdam_priv *priv = dev_get_priv(dev);\n+\tint ret;\n+\n+\tpriv->base = dev_read_addr(dev);\n+\tif (priv->base == FDT_ADDR_T_NONE) {\n+\t\tdev_err(dev, \"Could not read base address\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpriv->size = dev_read_u32_default(dev, \"qcom,sdam-size\", SDAM_SIZE);\n+\n+\tret = qcom_sdam_find_spmi_pmic(dev, &priv->spmi_dev, &priv->pmic_usid);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdev_info(dev, \"SDAM base=0x%x size=0x%x PMIC_USID=%d\\n\",\n+\t\t priv->base, priv->size, priv->pmic_usid);\n+\n+\treturn 0;\n+}\n+\n+static const struct udevice_id qcom_sdam_ids[] = {\n+\t{ .compatible = \"qcom,spmi-sdam\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(qcom_spmi_sdam) = {\n+\t.name = \"qcom-spmi-sdam\",\n+\t.id = UCLASS_MISC,\n+\t.of_match = qcom_sdam_ids,\n+\t.probe = qcom_sdam_probe,\n+\t.ops = &qcom_sdam_ops,\n+\t.priv_auto = sizeof(struct qcom_sdam_priv),\n+};\n", "prefixes": [ "v3", "2/7" ] }