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GET /api/patches/2217825/?format=api
{ "id": 2217825, "url": "http://patchwork.ozlabs.org/api/patches/2217825/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260330171419.1117817-2-aswin.murugan@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330171419.1117817-2-aswin.murugan@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-03-30T17:14:13", "name": "[v3,1/7] misc: Add support for bit fields in NVMEM cells", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a82d291e7687f68e71c9fc9cc0f7652a3e6d3939", "submitter": { "id": 90811, "url": "http://patchwork.ozlabs.org/api/people/90811/?format=api", "name": "Aswin Murugan", "email": "aswin.murugan@oss.qualcomm.com" }, "delegate": { "id": 151538, "url": "http://patchwork.ozlabs.org/api/users/151538/?format=api", "username": "kcxt", "first_name": "Casey", "last_name": "Connolly", "email": "casey.connolly@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260330171419.1117817-2-aswin.murugan@oss.qualcomm.com/mbox/", "series": [ { "id": 498069, "url": "http://patchwork.ozlabs.org/api/series/498069/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=498069", "date": "2026-03-30T17:14:12", "name": "qcom: Add NVMEM bitfield support and reboot���mode integration", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/498069/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217825/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217825/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Ddl2CptG;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=I8FKIuwB;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"Ddl2CptG\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"I8FKIuwB\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fkyYP4XGXz1xtJ\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 31 Mar 2026 04:15:05 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 9048584056;\n\tMon, 30 Mar 2026 19:14:55 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id D357E83DBF; Mon, 30 Mar 2026 19:14:54 +0200 (CEST)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 3E8DB83DBF\n for <u-boot@lists.denx.de>; Mon, 30 Mar 2026 19:14:52 +0200 (CEST)", "from pps.filterd (m0279871.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 62UGCCYQ3173878\n for <u-boot@lists.denx.de>; Mon, 30 Mar 2026 17:14:50 GMT", "from mail-pg1-f198.google.com (mail-pg1-f198.google.com\n [209.85.215.198])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d7q9h1mvv-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Mon, 30 Mar 2026 17:14:50 +0000 (GMT)", "by mail-pg1-f198.google.com with SMTP id\n 41be03b00d2f7-c739120475fso3072326a12.3\n for <u-boot@lists.denx.de>; Mon, 30 Mar 2026 10:14:50 -0700 (PDT)", "from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMzMwMDE0MCBTYWx0ZWRfX4tGhleJNP5Qh\n ImT4IfM8PAH5A8H+NrM7kH4CAo7IomRITPYSTBPZg9XB0nDJR70FhXK49KJkUTEgFVS4GfEaEm5\n JRrW8boTdyucpRL41lq0A6BYCWhTE/yMXRPnvF14wmFKAC1NVn2JD4OEQyaTwzzLJPL7bIwYslk\n eENDXUjP0uKY0mhv7RcvlvfexhwlLSiXqoPiqGsRrlYhjlYZv7LtGAlqab8of56LQg1SDdQgBVA\n FXM+N3FZMjzndif0SwYSlP87XN+6B00s8k/Yyg/LpMBmMEk2e1wmIMZdRgEWjzcf8nVtNv3ZNiO\n CK8JSZL1bRr2JbVa4gUIyYjQEHGMvwxRL1ZilzLS2+pHWfIST2b/g3yYqKw7+Ph9cFe4JKxbayC\n /imps38X0EwOwfZxkMI1VNZiuQo3BH1tR9cejcJmHTBdwXXdI5vEy+XRl7/EVwZLxUXem+zsq7D\n PPl0Z5BhNmVLT4wHJcw==", "X-Authority-Analysis": "v=2.4 cv=AZS83nXG c=1 sm=1 tr=0 ts=69caaf8a cx=c_pps\n a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22\n a=EUspDBNiAAAA:8 a=77Gp4gJqd9K2asR3UTEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=x9snwWr2DeNwDh03kgHS:22", "X-Proofpoint-GUID": "JL4BSR_TtpZR77W_xLOaB47ZUV7LShIq", "X-Proofpoint-ORIG-GUID": "JL4BSR_TtpZR77W_xLOaB47ZUV7LShIq", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-03-29_05,2026-03-28_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 phishscore=0 priorityscore=1501 clxscore=1015\n impostorscore=0 suspectscore=0 bulkscore=0 adultscore=0 malwarescore=0\n spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound\n adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001\n definitions=main-2603300140", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "NVMEM cells currently only support byte-level access. Many hardware\nregisters pack multiple fields into single bytes, requiring bit-level\ngranularity. For example, Qualcomm PMIC PON registers store a 7-bit\nreboot reason field within a single byte, with bit 0 reserved for other\npurposes.\n\nAdd support for the optional 'bits' property in NVMEM cell device tree\nbindings. This property specifies <bit_offset num_bits> to define a bit\nfield within the cell's register space.\n\nImplement bit‑field handling in the driver to max u32 size\n\nExample device tree usage:\n reboot-reason@48 {\n reg = <0x48 0x01>;\n bits = <0x01 0x07>; /* 7 bits starting at bit 1 */\n };\n\nThis reads bits [7:1] from the byte at offset 0x48, leaving bit 0\nuntouched during write operations.\n\nCells without the 'bits' property continue to work unchanged, ensuring\nbackward compatibility with existing device trees.\n\nSigned-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>\n---\nChanges in v3:\n1. Simplified bit field handling to maximum u32 size (32 bits).\n2. Enforced strict size matching (size == cell->size) when nbits == 0.\n\n---\n drivers/misc/nvmem.c | 159 +++++++++++++++++++++++++++++++++++++------\n include/nvmem.h | 4 ++\n 2 files changed, 141 insertions(+), 22 deletions(-)", "diff": "diff --git a/drivers/misc/nvmem.c b/drivers/misc/nvmem.c\nindex 33e80858565..883ced9e898 100644\n--- a/drivers/misc/nvmem.c\n+++ b/drivers/misc/nvmem.c\n@@ -12,55 +12,156 @@\n #include <dm/ofnode.h>\n #include <dm/read.h>\n #include <dm/uclass.h>\n+#include <linux/bitops.h>\n+#include <linux/kernel.h>\n \n-int nvmem_cell_read(struct nvmem_cell *cell, void *buf, size_t size)\n+/* Maximum supported NVMEM cell size */\n+#define MAX_NVMEM_CELL_SIZE sizeof(u32) /* 4 bytes */\n+\n+/**\n+ * nvmem_cell_read_raw() - Read raw bytes from NVMEM cell without bit field extraction\n+ * @cell: NVMEM cell to read from\n+ * @buf: Buffer to store read data\n+ * @size: Size of buffer\n+ *\n+ * This is an internal helper that reads raw bytes from hardware without applying\n+ * bit field extraction. Used by both nvmem_cell_read() and nvmem_cell_write().\n+ * Caller must validate buffer size before calling this function.\n+ *\n+ * Return: Number of bytes read on success, negative error code on failure\n+ */\n+static int nvmem_cell_read_raw(struct nvmem_cell *cell, void *buf, size_t size)\n {\n-\tdev_dbg(cell->nvmem, \"%s: off=%u size=%zu\\n\", __func__, cell->offset, size);\n-\tif (size != cell->size)\n-\t\treturn -EINVAL;\n+\tint ret;\n+\n+\tmemset(buf, 0, size);\n \n \tswitch (cell->nvmem->driver->id) {\n \tcase UCLASS_I2C_EEPROM:\n-\t\treturn i2c_eeprom_read(cell->nvmem, cell->offset, buf, size);\n-\tcase UCLASS_MISC: {\n-\t\tint ret = misc_read(cell->nvmem, cell->offset, buf, size);\n-\n+\t\tret = i2c_eeprom_read(cell->nvmem, cell->offset, buf, cell->size);\n+\t\tbreak;\n+\tcase UCLASS_MISC:\n+\t\tret = misc_read(cell->nvmem, cell->offset, buf, cell->size);\n \t\tif (ret < 0)\n \t\t\treturn ret;\n-\t\tif (ret != size)\n+\t\tif (ret != cell->size)\n \t\t\treturn -EIO;\n-\t\treturn 0;\n-\t}\n+\t\tret = 0;\n+\t\tbreak;\n \tcase UCLASS_RTC:\n-\t\treturn dm_rtc_read(cell->nvmem, cell->offset, buf, size);\n+\t\tret = dm_rtc_read(cell->nvmem, cell->offset, buf, cell->size);\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENOSYS;\n \t}\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn cell->size;\n+}\n+\n+int nvmem_cell_read(struct nvmem_cell *cell, void *buf, size_t size)\n+{\n+\tint ret, bytes_needed;\n+\tu32 value;\n+\n+\tdev_dbg(cell->nvmem, \"%s: off=%u size=%zu\\n\", __func__, cell->offset, size);\n+\n+\tif ((cell->nbits && size < cell->size) || (!cell->nbits && size != cell->size)) {\n+\t\tdev_dbg(cell->nvmem, \"NVMEM: buffer size %zu invalid for cell size %zu\\n\",\n+\t\t\tsize, cell->size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (cell->nbits) {\n+\t\tbytes_needed = DIV_ROUND_UP(cell->nbits + cell->bit_offset, BITS_PER_BYTE);\n+\n+\t\tif (bytes_needed > cell->size || bytes_needed > MAX_NVMEM_CELL_SIZE ||\n+\t\t size != MAX_NVMEM_CELL_SIZE) {\n+\t\t\tdev_dbg(cell->nvmem, \"NVMEM: bit field requires %d bytes, cell size %zu, buffer size %d, got %zu\\n\",\n+\t\t\t\tbytes_needed, cell->size, MAX_NVMEM_CELL_SIZE, size);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tret = nvmem_cell_read_raw(cell, buf, size);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (cell->nbits) {\n+\t\tvalue = *(u32 *)buf;\n+\t\tvalue >>= cell->bit_offset;\n+\t\t/* Handle nbits == 32 specially to avoid undefined behavior */\n+\t\tif (cell->nbits < 32)\n+\t\t\tvalue &= (1U << cell->nbits) - 1;\n+\t\t*(u32 *)buf = value;\n+\t}\n+\n+\treturn 0;\n }\n \n int nvmem_cell_write(struct nvmem_cell *cell, const void *buf, size_t size)\n {\n+\tint ret, bytes_needed;\n+\tu32 current, value, mask;\n+\n \tdev_dbg(cell->nvmem, \"%s: off=%u size=%zu\\n\", __func__, cell->offset, size);\n-\tif (size != cell->size)\n+\n+\tif ((cell->nbits && size < cell->size) || (!cell->nbits && size != cell->size)) {\n+\t\tdev_dbg(cell->nvmem, \"NVMEM: buffer size %zu invalid for cell size %zu\\n\",\n+\t\t\tsize, cell->size);\n \t\treturn -EINVAL;\n+\t}\n+\n+\tif (cell->nbits) {\n+\t\tbytes_needed = DIV_ROUND_UP(cell->nbits + cell->bit_offset, BITS_PER_BYTE);\n+\n+\t\tif (bytes_needed > cell->size || bytes_needed > MAX_NVMEM_CELL_SIZE ||\n+\t\t size != MAX_NVMEM_CELL_SIZE) {\n+\t\t\tdev_dbg(cell->nvmem, \"NVMEM: bit field requires %d bytes, cell size %zu, buffer size %d, got %zu\\n\",\n+\t\t\t\tbytes_needed, cell->size, MAX_NVMEM_CELL_SIZE, size);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\t/* For bit fields, perform Read-Modify-Write */\n+\t\tret = nvmem_cell_read_raw(cell, ¤t, sizeof(current));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\t/* Apply masked bitfield update (shift + mask + merge) */\n+\t\tvalue = *(u32 *)buf;\n+\t\tvalue &= (1U << cell->nbits) - 1;\n+\t\tvalue <<= cell->bit_offset;\n+\n+\t\tmask = ((1U << cell->nbits) - 1) << cell->bit_offset;\n+\n+\t\t*(u32 *)buf = (current & ~mask) | value;\n+\t}\n \n \tswitch (cell->nvmem->driver->id) {\n \tcase UCLASS_I2C_EEPROM:\n-\t\treturn i2c_eeprom_write(cell->nvmem, cell->offset, buf, size);\n-\tcase UCLASS_MISC: {\n-\t\tint ret = misc_write(cell->nvmem, cell->offset, buf, size);\n-\n+\t\tret = i2c_eeprom_write(cell->nvmem, cell->offset, buf, cell->size);\n+\t\tbreak;\n+\tcase UCLASS_MISC:\n+\t\tret = misc_write(cell->nvmem, cell->offset, buf, cell->size);\n \t\tif (ret < 0)\n \t\t\treturn ret;\n-\t\tif (ret != size)\n+\t\tif (ret != cell->size)\n \t\t\treturn -EIO;\n-\t\treturn 0;\n-\t}\n+\t\tret = 0;\n+\t\tbreak;\n \tcase UCLASS_RTC:\n-\t\treturn dm_rtc_write(cell->nvmem, cell->offset, buf, size);\n+\t\tret = dm_rtc_write(cell->nvmem, cell->offset, buf, cell->size);\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENOSYS;\n \t}\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n }\n \n /**\n@@ -121,13 +222,27 @@ int nvmem_cell_get_by_index(struct udevice *dev, int index,\n \n \toffset = ofnode_get_addr_size_index_notrans(args.node, 0, &size);\n \tif (offset == FDT_ADDR_T_NONE || size == FDT_SIZE_T_NONE) {\n-\t\tdev_dbg(cell->nvmem, \"missing address or size for %s\\n\",\n+\t\tdev_err(cell->nvmem, \"missing address or size for %s\\n\",\n \t\t\tofnode_get_name(args.node));\n \t\treturn -EINVAL;\n \t}\n \n \tcell->offset = offset;\n \tcell->size = size;\n+\n+\tret = ofnode_read_u32_index(args.node, \"bits\", 0, &cell->bit_offset);\n+\tif (ret) {\n+\t\tcell->bit_offset = 0;\n+\t\tcell->nbits = 0;\n+\t} else {\n+\t\tret = ofnode_read_u32_index(args.node, \"bits\", 1, &cell->nbits);\n+\t\tif (ret)\n+\t\t\treturn -EINVAL;\n+\n+\t\tif (cell->bit_offset + cell->nbits > cell->size * 8)\n+\t\t\treturn -EINVAL;\n+\t}\n+\n \treturn 0;\n }\n \ndiff --git a/include/nvmem.h b/include/nvmem.h\nindex e6a8a98828b..dd82122f16f 100644\n--- a/include/nvmem.h\n+++ b/include/nvmem.h\n@@ -26,11 +26,15 @@\n * @nvmem: The backing storage device\n * @offset: The offset of the cell from the start of @nvmem\n * @size: The size of the cell, in bytes\n+ * @bit_offset: Bit offset within the cell (0 for byte-level access)\n+ * @nbits: Number of bits to use (0 for byte-level access)\n */\n struct nvmem_cell {\n \tstruct udevice *nvmem;\n \tunsigned int offset;\n \tsize_t size;\n+\tunsigned int bit_offset;\n+\tunsigned int nbits;\n };\n \n struct udevice;\n", "prefixes": [ "v3", "1/7" ] }