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GET /api/patches/2217819/?format=api
{ "id": 2217819, "url": "http://patchwork.ozlabs.org/api/patches/2217819/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260330164707.87441-4-mailingradian@gmail.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330164707.87441-4-mailingradian@gmail.com>", "list_archive_url": null, "date": "2026-03-30T16:47:05", "name": "[v4,3/5] pinctrl: qcom: add sdm670 lpi tlmm", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "06b1d7a7f08f13a3d98a125242ac0e69db6df230", "submitter": { "id": 84825, "url": "http://patchwork.ozlabs.org/api/people/84825/?format=api", "name": "Richard Acayan", "email": "mailingradian@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260330164707.87441-4-mailingradian@gmail.com/mbox/", "series": [ { "id": 498067, "url": "http://patchwork.ozlabs.org/api/series/498067/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=498067", "date": "2026-03-30T16:47:02", "name": "SDM670 LPASS LPI pin controller support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/498067/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217819/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217819/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-34440-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=MV2eX5LZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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Add the driver for this.\n\nSigned-off-by: Richard Acayan <mailingradian@gmail.com>\nReviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>\n---\n drivers/pinctrl/qcom/Kconfig | 10 ++\n drivers/pinctrl/qcom/Makefile | 1 +\n .../pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c | 166 ++++++++++++++++++\n 3 files changed, 177 insertions(+)\n create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c", "diff": "diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig\nindex f56592411cf6..eb8ed3effd58 100644\n--- a/drivers/pinctrl/qcom/Kconfig\n+++ b/drivers/pinctrl/qcom/Kconfig\n@@ -89,6 +89,16 @@ config PINCTRL_SM4250_LPASS_LPI\n \t Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI\n \t (Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform.\n \n+config PINCTRL_SDM670_LPASS_LPI\n+\ttristate \"Qualcomm Technologies Inc SDM670 LPASS LPI pin controller driver\"\n+\tdepends on GPIOLIB\n+\tdepends on ARM64 || COMPILE_TEST\n+\tdepends on PINCTRL_LPASS_LPI\n+\thelp\n+\t This is the pinctrl, pinmux, pinconf and gpiolib driver for the\n+\t Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI\n+\t (Low Power Island) found on the Qualcomm Technologies Inc SDM670 platform.\n+\n config PINCTRL_SM6115_LPASS_LPI\n \ttristate \"Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver\"\n \tdepends on ARM64 || COMPILE_TEST\ndiff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile\nindex 4269d1781015..ed2127d26912 100644\n--- a/drivers/pinctrl/qcom/Makefile\n+++ b/drivers/pinctrl/qcom/Makefile\n@@ -48,6 +48,7 @@ obj-$(CONFIG_PINCTRL_SC8280XP)\t+= pinctrl-sc8280xp.o\n obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o\n obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) += pinctrl-sdm660-lpass-lpi.o\n obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o\n+obj-$(CONFIG_PINCTRL_SDM670_LPASS_LPI) += pinctrl-sdm670-lpass-lpi.o\n obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o\n obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o\n obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o\ndiff --git a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c\nnew file mode 100644\nindex 000000000000..6270c6d09c22\n--- /dev/null\n+++ b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c\n@@ -0,0 +1,166 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (c) 2023-2026, Richard Acayan. All rights reserved.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/pinctrl/pinctrl.h>\n+\n+#include \"pinctrl-lpass-lpi.h\"\n+\n+enum lpass_lpi_functions {\n+\tLPI_MUX_comp_rx,\n+\tLPI_MUX_dmic1_clk,\n+\tLPI_MUX_dmic1_data,\n+\tLPI_MUX_dmic2_clk,\n+\tLPI_MUX_dmic2_data,\n+\tLPI_MUX_i2s1_clk,\n+\tLPI_MUX_i2s1_data,\n+\tLPI_MUX_i2s1_ws,\n+\tLPI_MUX_lpi_cdc_rst,\n+\tLPI_MUX_mclk0,\n+\tLPI_MUX_pdm_rx,\n+\tLPI_MUX_pdm_sync,\n+\tLPI_MUX_pdm_tx,\n+\tLPI_MUX_slimbus_clk,\n+\tLPI_MUX_gpio,\n+\tLPI_MUX__,\n+};\n+\n+static const struct pinctrl_pin_desc sdm670_lpi_pinctrl_pins[] = {\n+\tPINCTRL_PIN(0, \"gpio0\"),\n+\tPINCTRL_PIN(1, \"gpio1\"),\n+\tPINCTRL_PIN(2, \"gpio2\"),\n+\tPINCTRL_PIN(3, \"gpio3\"),\n+\tPINCTRL_PIN(4, \"gpio4\"),\n+\tPINCTRL_PIN(5, \"gpio5\"),\n+\tPINCTRL_PIN(6, \"gpio6\"),\n+\tPINCTRL_PIN(7, \"gpio7\"),\n+\tPINCTRL_PIN(8, \"gpio8\"),\n+\tPINCTRL_PIN(9, \"gpio9\"),\n+\tPINCTRL_PIN(10, \"gpio10\"),\n+\tPINCTRL_PIN(11, \"gpio11\"),\n+\tPINCTRL_PIN(12, \"gpio12\"),\n+\tPINCTRL_PIN(13, \"gpio13\"),\n+\tPINCTRL_PIN(14, \"gpio14\"),\n+\tPINCTRL_PIN(15, \"gpio15\"),\n+\tPINCTRL_PIN(16, \"gpio16\"),\n+\tPINCTRL_PIN(17, \"gpio17\"),\n+\tPINCTRL_PIN(18, \"gpio18\"),\n+\tPINCTRL_PIN(19, \"gpio19\"),\n+\tPINCTRL_PIN(20, \"gpio20\"),\n+\tPINCTRL_PIN(21, \"gpio21\"),\n+\tPINCTRL_PIN(22, \"gpio22\"),\n+\tPINCTRL_PIN(23, \"gpio23\"),\n+\tPINCTRL_PIN(24, \"gpio24\"),\n+\tPINCTRL_PIN(25, \"gpio25\"),\n+\tPINCTRL_PIN(26, \"gpio26\"),\n+\tPINCTRL_PIN(27, \"gpio27\"),\n+\tPINCTRL_PIN(28, \"gpio28\"),\n+\tPINCTRL_PIN(29, \"gpio29\"),\n+\tPINCTRL_PIN(30, \"gpio30\"),\n+\tPINCTRL_PIN(31, \"gpio31\"),\n+};\n+\n+static const char * const comp_rx_groups[] = { \"gpio22\", \"gpio24\" };\n+static const char * const dmic1_clk_groups[] = { \"gpio26\" };\n+static const char * const dmic1_data_groups[] = { \"gpio27\" };\n+static const char * const dmic2_clk_groups[] = { \"gpio28\" };\n+static const char * const dmic2_data_groups[] = { \"gpio29\" };\n+static const char * const i2s1_clk_groups[] = { \"gpio8\" };\n+static const char * const i2s1_ws_groups[] = { \"gpio9\" };\n+static const char * const i2s1_data_groups[] = { \"gpio10\", \"gpio11\" };\n+static const char * const lpi_cdc_rst_groups[] = { \"gpio29\" };\n+static const char * const mclk0_groups[] = { \"gpio19\" };\n+static const char * const pdm_rx_groups[] = { \"gpio21\", \"gpio23\", \"gpio25\" };\n+static const char * const pdm_sync_groups[] = { \"gpio19\" };\n+static const char * const pdm_tx_groups[] = { \"gpio20\" };\n+static const char * const slimbus_clk_groups[] = { \"gpio18\" };\n+\n+const struct lpi_pingroup sdm670_lpi_pinctrl_groups[] = {\n+\tLPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(8, LPI_NO_SLEW, _, _, i2s1_clk, _),\n+\tLPI_PINGROUP(9, LPI_NO_SLEW, _, _, i2s1_ws, _),\n+\tLPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, i2s1_data),\n+\tLPI_PINGROUP(11, LPI_NO_SLEW, _, i2s1_data, _, _),\n+\tLPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(18, LPI_NO_SLEW, _, slimbus_clk, _, _),\n+\tLPI_PINGROUP(19, LPI_NO_SLEW, mclk0, _, pdm_sync, _),\n+\tLPI_PINGROUP(20, LPI_NO_SLEW, _, pdm_tx, _, _),\n+\tLPI_PINGROUP(21, LPI_NO_SLEW, _, pdm_rx, _, _),\n+\tLPI_PINGROUP(22, LPI_NO_SLEW, _, comp_rx, _, _),\n+\tLPI_PINGROUP(23, LPI_NO_SLEW, pdm_rx, _, _, _),\n+\tLPI_PINGROUP(24, LPI_NO_SLEW, comp_rx, _, _, _),\n+\tLPI_PINGROUP(25, LPI_NO_SLEW, pdm_rx, _, _, _),\n+\tLPI_PINGROUP(26, LPI_NO_SLEW, dmic1_clk, _, _, _),\n+\tLPI_PINGROUP(27, LPI_NO_SLEW, dmic1_data, _, _, _),\n+\tLPI_PINGROUP(28, LPI_NO_SLEW, dmic2_clk, _, _, _),\n+\tLPI_PINGROUP(29, LPI_NO_SLEW, dmic2_data, lpi_cdc_rst, _, _),\n+\tLPI_PINGROUP(30, LPI_NO_SLEW, _, _, _, _),\n+\tLPI_PINGROUP(31, LPI_NO_SLEW, _, _, _, _),\n+};\n+\n+const struct lpi_function sdm670_lpi_pinctrl_functions[] = {\n+\tLPI_FUNCTION(comp_rx),\n+\tLPI_FUNCTION(dmic1_clk),\n+\tLPI_FUNCTION(dmic1_data),\n+\tLPI_FUNCTION(dmic2_clk),\n+\tLPI_FUNCTION(dmic2_data),\n+\tLPI_FUNCTION(i2s1_clk),\n+\tLPI_FUNCTION(i2s1_data),\n+\tLPI_FUNCTION(i2s1_ws),\n+\tLPI_FUNCTION(lpi_cdc_rst),\n+\tLPI_FUNCTION(mclk0),\n+\tLPI_FUNCTION(pdm_tx),\n+\tLPI_FUNCTION(pdm_rx),\n+\tLPI_FUNCTION(pdm_sync),\n+\tLPI_FUNCTION(slimbus_clk),\n+};\n+\n+static const struct lpi_pinctrl_variant_data sdm670_lpi_pinctrl_data = {\n+\t.pins = sdm670_lpi_pinctrl_pins,\n+\t.npins = ARRAY_SIZE(sdm670_lpi_pinctrl_pins),\n+\t.groups = sdm670_lpi_pinctrl_groups,\n+\t.ngroups = ARRAY_SIZE(sdm670_lpi_pinctrl_groups),\n+\t.functions = sdm670_lpi_pinctrl_functions,\n+\t.nfunctions = ARRAY_SIZE(sdm670_lpi_pinctrl_functions),\n+\t.flags = LPI_FLAG_SLEW_RATE_SAME_REG,\n+};\n+\n+static const struct of_device_id sdm670_lpi_pinctrl_of_match[] = {\n+\t{\n+\t\t.compatible = \"qcom,sdm670-lpass-lpi-pinctrl\",\n+\t\t.data = &sdm670_lpi_pinctrl_data,\n+\t},\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, sdm670_lpi_pinctrl_of_match);\n+\n+static struct platform_driver sdm670_lpi_pinctrl_driver = {\n+\t.driver = {\n+\t\t.name = \"qcom-sdm670-lpass-lpi-pinctrl\",\n+\t\t.of_match_table = sdm670_lpi_pinctrl_of_match,\n+\t},\n+\t.probe = lpi_pinctrl_probe,\n+\t.remove = lpi_pinctrl_remove,\n+};\n+module_platform_driver(sdm670_lpi_pinctrl_driver);\n+\n+MODULE_AUTHOR(\"Richard Acayan <mailingradian@gmail.com>\");\n+MODULE_DESCRIPTION(\"QTI SDM670 LPI GPIO pin control driver\");\n+MODULE_LICENSE(\"GPL\");\n", "prefixes": [ "v4", "3/5" ] }