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GET /api/patches/2217814/?format=api
{ "id": 2217814, "url": "http://patchwork.ozlabs.org/api/patches/2217814/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260330161914.1071118-1-flavra@baylibre.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330161914.1071118-1-flavra@baylibre.com>", "list_archive_url": null, "date": "2026-03-30T16:19:14", "name": "pinctrl: mcp23s08: Disable all pin interrupts during probe", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c43a91dd8eb8184a8cafbe83475d67abf1a550e0", "submitter": { "id": 90414, "url": "http://patchwork.ozlabs.org/api/people/90414/?format=api", "name": "Francesco Lavra", "email": "flavra@baylibre.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260330161914.1071118-1-flavra@baylibre.com/mbox/", "series": [ { "id": 498064, "url": "http://patchwork.ozlabs.org/api/series/498064/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=498064", "date": "2026-03-30T16:19:14", "name": "pinctrl: mcp23s08: Disable all pin interrupts during probe", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498064/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217814/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217814/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-34436-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=Xdbv6kfx;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-gpio+bounces-34436-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.b=\"Xdbv6kfx\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.128.49", "smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=baylibre.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=baylibre.com" ], "Received": [ "from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fkxP41VnCz1xtJ\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 31 Mar 2026 03:22:48 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sto.lore.kernel.org (Postfix) with ESMTP id 29AEC30266DE\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 30 Mar 2026 16:19:24 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id EBF7D37757D;\n\tMon, 30 Mar 2026 16:19:21 +0000 (UTC)", "from mail-wm1-f49.google.com (mail-wm1-f49.google.com\n [209.85.128.49])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 63BC937700F\n\tfor <linux-gpio@vger.kernel.org>; Mon, 30 Mar 2026 16:19:18 +0000 (UTC)", "by mail-wm1-f49.google.com with SMTP id\n 5b1f17b1804b1-48704db565eso61006355e9.1\n for <linux-gpio@vger.kernel.org>;\n Mon, 30 Mar 2026 09:19:18 -0700 (PDT)", "from localhost (mob-176-247-30-22.net.vodafone.it. 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a=openpgp-sha256; l=4436; i=flavra@baylibre.com;\n h=from:subject; bh=hgGtkNEYd3/BeM5nsJ4Pr/kLRh68Go04WXIspuv2d8I=;\n b=owEB7QES/pANAwAKAe3xO3POlDZfAcsmYgBpyqJ6k+fhPfJ2tZeDtag7fp7JU0CzQvwwvHbQk\n OPfzSXzcXaJAbMEAAEKAB0WIQSGV4VPlTvcox7DFObt8TtzzpQ2XwUCacqiegAKCRDt8TtzzpQ2\n X3o6C/0fIDZXhIG0IXYz4VynyCvWA9w+4hUrLt2WOAd6jICfZFuO7mBkE95B7qAJj073SX3NFbi\n dulU/PbCisLROc3qq2myaRHisrc2hodJOyA5w0KeddwniOWg0ppBQRLSwHCPK1U+PpWfH5mgX5w\n 06+QgX8xP7bR8tCTlKYMk9DhO6nDKOgJGdiBzERnuhsOYfwDk1bw29jCp6tA+1M09iwynWvd8FM\n ZSZGJZVvwE2aSRsnJkxyMgkW1vl71lrKOJnBiF6aNd8Y6jpCfrdlrfn9lO4feJGo4Ix13gSrgkg\n JQR86hQqm0Q6WJcCADtNbuntVFg5DgMhBHsCJpmy/ChbA35a5NN3nVCK+7w6sArtrFHzhMkMWLA\n 3/zxTtP4SUbpZDqfLi0Rd8GUQEeqVdBIGFrqtZxeENeoSEiun0UczI80YAlRaZciZP3jjEJLXlJ\n z38n0KtDilNUo6bEjqXAoQVVbIK7ZfwGZYDa1JpNLEwneWXknAnoyqbmsLvdT2Yv1vd2E=", "X-Developer-Key": "i=flavra@baylibre.com; a=openpgp;\n fpr=8657854F953BDCA31EC314E6EDF13B73CE94365F", "Content-Transfer-Encoding": "8bit" }, "content": "A chip being probed may have the interrupt-on-change feature enabled on\nsome of its pins, for example after a reboot. This can cause the chip to\ngenerate interrupts for pins that don't have a registered nested handler,\nwhich leads to a kernel crash such as below:\n\n[ 7.928897] Unable to handle kernel read from unreadable memory at virtual address 00000000000000ac\n[ 7.932314] Mem abort info:\n[ 7.935081] ESR = 0x0000000096000004\n[ 7.938808] EC = 0x25: DABT (current EL), IL = 32 bits\n[ 7.944094] SET = 0, FnV = 0\n[ 7.947127] EA = 0, S1PTW = 0\n[ 7.950247] FSC = 0x04: level 0 translation fault\n[ 7.955101] Data abort info:\n[ 7.957961] ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000\n[ 7.963421] CM = 0, WnR = 0, TnD = 0, TagAccess = 0\n[ 7.968447] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0\n[ 7.973734] user pgtable: 4k pages, 48-bit VAs, pgdp=00000000089b7000\n[ 7.980148] [00000000000000ac] pgd=0000000000000000, p4d=0000000000000000\n[ 7.986913] Internal error: Oops: 0000000096000004 [#1] SMP\n[ 7.992545] Modules linked in:\n[ 8.073678] CPU: 0 UID: 0 PID: 81 Comm: irq/18-4-0025 Not tainted 7.0.0-rc6-gd2b5a1f931c8-dirty #199\n[ 8.073689] Hardware name: Khadas VIM3 (DT)\n[ 8.073692] pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)\n[ 8.094639] pc : _raw_spin_lock_irq+0x40/0x80\n[ 8.098970] lr : handle_nested_irq+0x2c/0x168\n[ 8.098979] sp : ffff800082b2bd20\n[ 8.106599] x29: ffff800082b2bd20 x28: ffff800080107920 x27: ffff800080104d88\n[ 8.106611] x26: ffff000003298080 x25: 0000000000000001 x24: 000000000000ff00\n[ 8.113707] x23: 0000000000000001 x22: 0000000000000000 x21: 000000000000000e\n[ 8.120850] x20: 0000000000000000 x19: 00000000000000ac x18: 0000000000000000\n[ 8.135046] x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000000\n[ 8.135062] x14: ffff800081567ea8 x13: ffffffffffffffff x12: 0000000000000000\n[ 8.135070] x11: 00000000000000c0 x10: 0000000000000b60 x9 : ffff800080109e0c\n[ 8.135078] x8 : 1fffe0000069dbc1 x7 : 0000000000000001 x6 : ffff0000034ede00\n[ 8.135086] x5 : 0000000000000000 x4 : ffff0000034ede08 x3 : 0000000000000001\n[ 8.163460] x2 : 0000000000000000 x1 : 0000000000000001 x0 : 00000000000000ac\n[ 8.170560] Call trace:\n[ 8.180094] _raw_spin_lock_irq+0x40/0x80 (P)\n[ 8.184443] mcp23s08_irq+0x248/0x358\n[ 8.184462] irq_thread_fn+0x34/0xb8\n[ 8.184470] irq_thread+0x1a4/0x310\n[ 8.195093] kthread+0x13c/0x150\n[ 8.198309] ret_from_fork+0x10/0x20\n[ 8.201850] Code: d65f03c0 d2800002 52800023 f9800011 (885ffc01)\n[ 8.207931] ---[ end trace 0000000000000000 ]---\n\nThis issue has always been present, but has been latent until commit\n\"f9f4fda15e72\" (\"pinctrl: mcp23s08: init reg_defaults from HW at probe and\nswitch cache type\"), which correctly removed reg_defaults from the regmap\nand as a side effect changed the behavior of the interrupt handler so that\nthe real value of the MCP_GPINTEN register is now being read from the chip\ninstead of using a bogus 0 default value; a non-zero value for this\nregister can trigger the invocation of a nested handler which may not exist\n(yet).\nFix this issue by disabling all pin interrupts during initialization.\n\nFixes: \"f9f4fda15e72\" (\"pinctrl: mcp23s08: init reg_defaults from HW at probe and switch cache type\")\nSigned-off-by: Francesco Lavra <flavra@baylibre.com>\n---\n drivers/pinctrl/pinctrl-mcp23s08.c | 9 +++++++++\n 1 file changed, 9 insertions(+)", "diff": "diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c\nindex 586f2f67c617..b89b3169e8be 100644\n--- a/drivers/pinctrl/pinctrl-mcp23s08.c\n+++ b/drivers/pinctrl/pinctrl-mcp23s08.c\n@@ -664,6 +664,15 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,\n \tif (mcp->irq && mcp->irq_controller) {\n \t\tstruct gpio_irq_chip *girq = &mcp->chip.irq;\n \n+\t\t/*\n+\t\t * Disable all pin interrupts, to prevent the interrupt handler from\n+\t\t * calling nested handlers for any currently-enabled interrupts that\n+\t\t * do not (yet) have an actual handler.\n+\t\t */\n+\t\tret = mcp_write(mcp, MCP_GPINTEN, 0);\n+\t\tif (ret < 0)\n+\t\t\treturn dev_err_probe(dev, ret, \"can't disable interrupts\\n\");\n+\n \t\tgpio_irq_chip_set_chip(girq, &mcp23s08_irq_chip);\n \t\t/* This will let us handle the parent IRQ in the driver */\n \t\tgirq->parent_handler = NULL;\n", "prefixes": [] }