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GET /api/patches/2217810/?format=api
{ "id": 2217810, "url": "http://patchwork.ozlabs.org/api/patches/2217810/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260330-pinctrl-mtk-fix-mt8189-v2-2-05a737ec623d@baylibre.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330-pinctrl-mtk-fix-mt8189-v2-2-05a737ec623d@baylibre.com>", "list_archive_url": null, "date": "2026-03-30T16:00:34", "name": "[v2,2/4] pinctrl: mediatek: mt8189: fix pinconf bias", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5c4a70a43c1059f6c95ba6ef47e82824b3ce835a", "submitter": { "id": 87228, "url": "http://patchwork.ozlabs.org/api/people/87228/?format=api", "name": "David Lechner", "email": "dlechner@baylibre.com" }, "delegate": { "id": 161331, "url": "http://patchwork.ozlabs.org/api/users/161331/?format=api", "username": "dlech", "first_name": "David", "last_name": "Lechner", "email": "dlechner@baylibre.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260330-pinctrl-mtk-fix-mt8189-v2-2-05a737ec623d@baylibre.com/mbox/", "series": [ { "id": 498062, "url": "http://patchwork.ozlabs.org/api/series/498062/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=498062", "date": "2026-03-30T16:00:32", "name": "pinctrl: mediatek: fix mt8189 MSDC and I2C pins", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498062/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217810/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217810/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=CjjFrR9V;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260330-pinctrl-mtk-fix-mt8189-v2-2-05a737ec623d@baylibre.com>", "References": "<20260330-pinctrl-mtk-fix-mt8189-v2-0-05a737ec623d@baylibre.com>", "In-Reply-To": "<20260330-pinctrl-mtk-fix-mt8189-v2-0-05a737ec623d@baylibre.com>", "To": "Ryder Lee <ryder.lee@mediatek.com>, Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,\n Tom Rini <trini@konsulko.com>", "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>", "X-Mailer": "b4 0.16-dev", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=20756;\n i=dlechner@baylibre.com; h=from:subject:message-id;\n bh=WnRF5C7wmJTHedlhLXyTSeQ2Te8EwQSYMEC8pzxwwj8=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpyp5DqOzEUSJ+V87rQYy2wYR7rMa7IGGe3eF8l\n BxRZRLaGsaJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCacqeQxYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/AKcAH/1CaP7ebShgPH/DP351abpiSx5BFpyKv57xowfi\n 4mzheuv7eiCN44joTxqnxR73IjemxS2ZG6nn85ReTicRfF9En5xlVuqc429dcMJKmAAUFBrj+j+\n OHWsdQX158eS1JnSXs6eKtvO8hhDqHxSzv2B4Bi74yO0pZMuasA7zSTmYlB7ZQNgldf6MvkIl/v\n wah2/dt5DTc+BYDoHzh9X73x+DpdcEVYYwQB3D5+6MegmrKZPGJx46QSuMdUGb5wMzzdQbcMyGH\n m7a8kTZdUL58VHvZAeqTnqPO7/iyKEYIOQg73QCmsOzpXAdez6SENv+pI8g5lprGSp6Fg4ivE4z\n uvuU=", "X-Developer-Key": "i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Fix setting pinconf bias for MT8189.\n\nUsing mtk_pinconf_bias_set_v1() was wrong because MT8189 does not have\nPULLEN/PULLSEL registers. It has PU and PD registers for most pins.\nMSDC pins need special handling since they have PUPD/R1/R0 registers.\nI2C pins need special handling since they have PU/PD/RSEL registers.\nNew groups are added for MSDC and I2C pins and the bias_set callback\nis now set appropriately for all groups.\n\nA new table is needed for the RSEL registers since those were missing.\n\nSome new macros are introduced to avoid repeating the same info many\ntimes in MTK_TYPED_PIN(). This also fixes the semantically incorrect\nuse of DRV_GRPX for the IO_TYPE_GRPX field.\n\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n drivers/pinctrl/mediatek/pinctrl-mt8189.c | 413 +++++++++++++++++-------------\n 1 file changed, 229 insertions(+), 184 deletions(-)", "diff": "diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8189.c b/drivers/pinctrl/mediatek/pinctrl-mt8189.c\nindex a64440d8bb3..9bcabe03151 100644\n--- a/drivers/pinctrl/mediatek/pinctrl-mt8189.c\n+++ b/drivers/pinctrl/mediatek/pinctrl-mt8189.c\n@@ -1015,6 +1015,29 @@ static const struct mtk_pin_field_calc mt8189_pin_drv_range[] = {\n \tPIN_FIELD_BASE(182, IO_BASE_RT, 0x0000, 9, 3),\n };\n \n+static const struct mtk_pin_field_calc mt8189_pin_rsel_range[] = {\n+\tPIN_FIELD_BASE(51, IO_BASE_RB1, 0x00B0, 0, 3), /* SCP_SCL0 */\n+\tPIN_FIELD_BASE(52, IO_BASE_RB1, 0x00B0, 6, 3), /* SCP_SDA0 */\n+\tPIN_FIELD_BASE(53, IO_BASE_RB1, 0x00B0, 3, 3), /* SCP_SCL1 */\n+\tPIN_FIELD_BASE(54, IO_BASE_RB1, 0x00B0, 9, 3), /* SCP_SDA1 */\n+\tPIN_FIELD_BASE(55, IO_BASE_LM, 0x00B0, 0, 3), /* SCL2 */\n+\tPIN_FIELD_BASE(56, IO_BASE_LM, 0x00B0, 3, 3), /* SDA2 */\n+\tPIN_FIELD_BASE(57, IO_BASE_BM1, 0x00B0, 0, 3), /* SCL3 */\n+\tPIN_FIELD_BASE(58, IO_BASE_BM1, 0x00B0, 12, 3), /* SDA3 */\n+\tPIN_FIELD_BASE(59, IO_BASE_BM1, 0x00B0, 3, 3), /* SCL4 */\n+\tPIN_FIELD_BASE(60, IO_BASE_BM1, 0x00B0, 15, 3), /* SDA4 */\n+\tPIN_FIELD_BASE(61, IO_BASE_BM1, 0x00B0, 6, 3), /* SCL5 */\n+\tPIN_FIELD_BASE(62, IO_BASE_BM1, 0x00B0, 18, 3), /* SDA5 */\n+\tPIN_FIELD_BASE(63, IO_BASE_BM1, 0x00B0, 9, 3), /* SCL6 */\n+\tPIN_FIELD_BASE(64, IO_BASE_BM1, 0x00B0, 21, 3), /* SDA6 */\n+\tPIN_FIELD_BASE(65, IO_BASE_RT, 0x00E0, 0, 3), /* SCL7 */\n+\tPIN_FIELD_BASE(66, IO_BASE_RT, 0x00E0, 6, 3), /* SDA7 */\n+\tPIN_FIELD_BASE(67, IO_BASE_RT, 0x00E0, 3, 3), /* SCL8 */\n+\tPIN_FIELD_BASE(68, IO_BASE_RT, 0x00E0, 9, 3), /* SDA8 */\n+\tPIN_FIELD_BASE(180, IO_BASE_LT0, 0x0110, 0, 3), /* SPMI_P_SCL */\n+\tPIN_FIELD_BASE(181, IO_BASE_LT0, 0x0110, 3, 3), /* SPMI_P_SDA */\n+};\n+\n static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = {\n \t[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8189_pin_mode_range),\n \t[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8189_pin_dir_range),\n@@ -1028,6 +1051,7 @@ static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = {\n \t[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8189_pin_pu_range),\n \t[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8189_pin_pd_range),\n \t[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8189_pin_drv_range),\n+\t[PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8189_pin_rsel_range),\n };\n \n static const char * const mt8189_pinctrl_register_base_names[] = {\n@@ -1048,196 +1072,217 @@ static const char * const mt8189_pinctrl_register_base_names[] = {\n \t[IO_BASE_EINT4] = \"eint4\",\n };\n \n+#define MT8189_TYPE0_PIN(_number, _name) \\\n+\tMTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)\n+\n+#define MT8189_TYPE1_PIN(_number, _name) \\\n+\tMTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)\n+\n+#define MT8189_TYPE2_PIN(_number, _name) \\\n+\tMTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP2)\n+\n static const struct mtk_pin_desc mt8189_pins[] = {\n-\tMTK_TYPED_PIN(0, \"GPIO00\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(1, \"GPIO01\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(2, \"GPIO02\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(3, \"GPIO03\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(4, \"GPIO04\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(5, \"GPIO05\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(6, \"GPIO06\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(7, \"GPIO07\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(8, \"GPIO08\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(9, \"GPIO09\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(10, \"GPIO10\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(11, \"GPIO11\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(12, \"GPIO12\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(13, \"GPIO13\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(14, \"GPIO14\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(15, \"GPIO15\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(16, \"GPIO16\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(17, \"GPIO17\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(18, \"GPIO18\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(19, \"GPIO19\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(20, \"GPIO20\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(21, \"GPIO21\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(22, \"GPIO22\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(23, \"GPIO23\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(24, \"GPIO24\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(25, \"GPIO25\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(26, \"GPIO26\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(27, \"GPIO27\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(28, \"GPIO28\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(29, \"GPIO29\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(30, \"GPIO30\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(31, \"GPIO31\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(32, \"GPIO32\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(33, \"GPIO33\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(34, \"GPIO34\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(35, \"GPIO35\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(36, \"GPIO36\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(37, \"GPIO37\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(38, \"GPIO38\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(39, \"GPIO39\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(40, \"GPIO40\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(41, \"GPIO41\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(42, \"GPIO42\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(43, \"GPIO43\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(44, \"GPIO44\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(45, \"GPIO45\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(46, \"GPIO46\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(47, \"GPIO47\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(48, \"GPIO48\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(49, \"GPIO49\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(50, \"GPIO50\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(51, \"GPIO51\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(52, \"GPIO52\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(53, \"GPIO53\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(54, \"GPIO54\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(55, \"GPIO55\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(56, \"GPIO56\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(57, \"GPIO57\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(58, \"GPIO58\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(59, \"GPIO59\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(60, \"GPIO60\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(61, \"GPIO61\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(62, \"GPIO62\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(63, \"GPIO63\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(64, \"GPIO64\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(65, \"GPIO65\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(66, \"GPIO66\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(67, \"GPIO67\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(68, \"GPIO68\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(69, \"GPIO69\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(70, \"GPIO70\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(71, \"GPIO71\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(72, \"GPIO72\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(73, \"GPIO73\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(74, \"GPIO74\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(75, \"GPIO75\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(76, \"GPIO76\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(77, \"GPIO77\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(78, \"GPIO78\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(79, \"GPIO79\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(80, \"GPIO80\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(81, \"GPIO81\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(82, \"GPIO82\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(83, \"GPIO83\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(84, \"GPIO84\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(85, \"GPIO85\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(86, \"GPIO86\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(87, \"GPIO87\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(88, \"GPIO88\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(89, \"GPIO89\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(90, \"GPIO90\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(91, \"GPIO91\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(92, \"GPIO92\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(93, \"GPIO93\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(94, \"GPIO94\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(95, \"GPIO95\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(96, \"GPIO96\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(97, \"GPIO97\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(98, \"GPIO98\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(99, \"GPIO99\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(100, \"GPIO100\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(101, \"GPIO101\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(102, \"GPIO102\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(103, \"GPIO103\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(104, \"GPIO104\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(105, \"GPIO105\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(106, \"GPIO106\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(107, \"GPIO107\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(108, \"GPIO108\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(109, \"GPIO109\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(110, \"GPIO110\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(111, \"GPIO111\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(112, \"GPIO112\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(113, \"GPIO113\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(114, \"GPIO114\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(115, \"GPIO115\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(116, \"GPIO116\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(117, \"GPIO117\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(118, \"GPIO118\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(119, \"GPIO119\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(120, \"GPIO120\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(121, \"GPIO121\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(122, \"GPIO122\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(123, \"GPIO123\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(124, \"GPIO124\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(125, \"GPIO125\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(126, \"GPIO126\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(127, \"GPIO127\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(128, \"GPIO128\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(129, \"GPIO129\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(130, \"GPIO130\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(131, \"GPIO131\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(132, \"GPIO132\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(133, \"GPIO133\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(134, \"GPIO134\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(135, \"GPIO135\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(136, \"GPIO136\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(137, \"GPIO137\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(138, \"GPIO138\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(139, \"GPIO139\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(140, \"GPIO140\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(141, \"GPIO141\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(142, \"GPIO142\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(143, \"GPIO143\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(144, \"GPIO144\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(145, \"GPIO145\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(146, \"GPIO146\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(147, \"GPIO147\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(148, \"GPIO148\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(149, \"GPIO149\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(150, \"GPIO150\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(151, \"GPIO151\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(152, \"GPIO152\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(153, \"GPIO153\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(154, \"GPIO154\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(155, \"GPIO155\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(156, \"GPIO156\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(157, \"GPIO157\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(158, \"GPIO158\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(159, \"GPIO159\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(160, \"GPIO160\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(161, \"GPIO161\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(162, \"GPIO162\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(163, \"GPIO163\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(164, \"GPIO164\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(165, \"GPIO165\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(166, \"GPIO166\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(167, \"GPIO167\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(168, \"GPIO168\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(169, \"GPIO169\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(170, \"GPIO170\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(171, \"GPIO171\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(172, \"GPIO172\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(173, \"GPIO173\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(174, \"GPIO174\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(175, \"GPIO175\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(176, \"GPIO176\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(177, \"GPIO177\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(178, \"GPIO178\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(179, \"GPIO179\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(180, \"GPIO180\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(181, \"GPIO181\", DRV_GRP4, DRV_GRP0),\n-\tMTK_TYPED_PIN(182, \"GPIO182\", DRV_GRP4, DRV_GRP0),\n+\tMT8189_TYPE0_PIN(0, \"GPIO00\"),\n+\tMT8189_TYPE0_PIN(1, \"GPIO01\"),\n+\tMT8189_TYPE0_PIN(2, \"GPIO02\"),\n+\tMT8189_TYPE0_PIN(3, \"GPIO03\"),\n+\tMT8189_TYPE0_PIN(4, \"GPIO04\"),\n+\tMT8189_TYPE0_PIN(5, \"GPIO05\"),\n+\tMT8189_TYPE0_PIN(6, \"GPIO06\"),\n+\tMT8189_TYPE0_PIN(7, \"GPIO07\"),\n+\tMT8189_TYPE0_PIN(8, \"GPIO08\"),\n+\tMT8189_TYPE0_PIN(9, \"GPIO09\"),\n+\tMT8189_TYPE0_PIN(10, \"GPIO10\"),\n+\tMT8189_TYPE0_PIN(11, \"GPIO11\"),\n+\tMT8189_TYPE0_PIN(12, \"GPIO12\"),\n+\tMT8189_TYPE0_PIN(13, \"GPIO13\"),\n+\tMT8189_TYPE0_PIN(14, \"GPIO14\"),\n+\tMT8189_TYPE0_PIN(15, \"GPIO15\"),\n+\tMT8189_TYPE0_PIN(16, \"GPIO16\"),\n+\tMT8189_TYPE0_PIN(17, \"GPIO17\"),\n+\tMT8189_TYPE0_PIN(18, \"GPIO18\"),\n+\tMT8189_TYPE0_PIN(19, \"GPIO19\"),\n+\tMT8189_TYPE0_PIN(20, \"GPIO20\"),\n+\tMT8189_TYPE0_PIN(21, \"GPIO21\"),\n+\tMT8189_TYPE0_PIN(22, \"GPIO22\"),\n+\tMT8189_TYPE0_PIN(23, \"GPIO23\"),\n+\tMT8189_TYPE0_PIN(24, \"GPIO24\"),\n+\tMT8189_TYPE0_PIN(25, \"GPIO25\"),\n+\tMT8189_TYPE0_PIN(26, \"GPIO26\"),\n+\tMT8189_TYPE0_PIN(27, \"GPIO27\"),\n+\tMT8189_TYPE0_PIN(28, \"GPIO28\"),\n+\tMT8189_TYPE0_PIN(29, \"GPIO29\"),\n+\tMT8189_TYPE0_PIN(30, \"GPIO30\"),\n+\tMT8189_TYPE0_PIN(31, \"GPIO31\"),\n+\tMT8189_TYPE0_PIN(32, \"GPIO32\"),\n+\tMT8189_TYPE0_PIN(33, \"GPIO33\"),\n+\tMT8189_TYPE0_PIN(34, \"GPIO34\"),\n+\tMT8189_TYPE0_PIN(35, \"GPIO35\"),\n+\tMT8189_TYPE0_PIN(36, \"GPIO36\"),\n+\tMT8189_TYPE0_PIN(37, \"GPIO37\"),\n+\tMT8189_TYPE0_PIN(38, \"GPIO38\"),\n+\tMT8189_TYPE0_PIN(39, \"GPIO39\"),\n+\tMT8189_TYPE0_PIN(40, \"GPIO40\"),\n+\tMT8189_TYPE0_PIN(41, \"GPIO41\"),\n+\tMT8189_TYPE0_PIN(42, \"GPIO42\"),\n+\tMT8189_TYPE0_PIN(43, \"GPIO43\"),\n+\tMT8189_TYPE1_PIN(44, \"GPIO44\"),\n+\tMT8189_TYPE1_PIN(45, \"GPIO45\"),\n+\tMT8189_TYPE1_PIN(46, \"GPIO46\"),\n+\tMT8189_TYPE1_PIN(47, \"GPIO47\"),\n+\tMT8189_TYPE0_PIN(48, \"GPIO48\"),\n+\tMT8189_TYPE0_PIN(49, \"GPIO49\"),\n+\tMT8189_TYPE0_PIN(50, \"GPIO50\"),\n+\tMT8189_TYPE2_PIN(51, \"GPIO51\"),\n+\tMT8189_TYPE2_PIN(52, \"GPIO52\"),\n+\tMT8189_TYPE2_PIN(53, \"GPIO53\"),\n+\tMT8189_TYPE2_PIN(54, \"GPIO54\"),\n+\tMT8189_TYPE2_PIN(55, \"GPIO55\"),\n+\tMT8189_TYPE2_PIN(56, \"GPIO56\"),\n+\tMT8189_TYPE2_PIN(57, \"GPIO57\"),\n+\tMT8189_TYPE2_PIN(58, \"GPIO58\"),\n+\tMT8189_TYPE2_PIN(59, \"GPIO59\"),\n+\tMT8189_TYPE2_PIN(60, \"GPIO60\"),\n+\tMT8189_TYPE2_PIN(61, \"GPIO61\"),\n+\tMT8189_TYPE2_PIN(62, \"GPIO62\"),\n+\tMT8189_TYPE2_PIN(63, \"GPIO63\"),\n+\tMT8189_TYPE2_PIN(64, \"GPIO64\"),\n+\tMT8189_TYPE2_PIN(65, \"GPIO65\"),\n+\tMT8189_TYPE2_PIN(66, \"GPIO66\"),\n+\tMT8189_TYPE2_PIN(67, \"GPIO67\"),\n+\tMT8189_TYPE2_PIN(68, \"GPIO68\"),\n+\tMT8189_TYPE0_PIN(69, \"GPIO69\"),\n+\tMT8189_TYPE0_PIN(70, \"GPIO70\"),\n+\tMT8189_TYPE0_PIN(71, \"GPIO71\"),\n+\tMT8189_TYPE0_PIN(72, \"GPIO72\"),\n+\tMT8189_TYPE0_PIN(73, \"GPIO73\"),\n+\tMT8189_TYPE0_PIN(74, \"GPIO74\"),\n+\tMT8189_TYPE0_PIN(75, \"GPIO75\"),\n+\tMT8189_TYPE0_PIN(76, \"GPIO76\"),\n+\tMT8189_TYPE0_PIN(77, \"GPIO77\"),\n+\tMT8189_TYPE0_PIN(78, \"GPIO78\"),\n+\tMT8189_TYPE0_PIN(79, \"GPIO79\"),\n+\tMT8189_TYPE0_PIN(80, \"GPIO80\"),\n+\tMT8189_TYPE0_PIN(81, \"GPIO81\"),\n+\tMT8189_TYPE0_PIN(82, \"GPIO82\"),\n+\tMT8189_TYPE0_PIN(83, \"GPIO83\"),\n+\tMT8189_TYPE0_PIN(84, \"GPIO84\"),\n+\tMT8189_TYPE0_PIN(85, \"GPIO85\"),\n+\tMT8189_TYPE0_PIN(86, \"GPIO86\"),\n+\tMT8189_TYPE0_PIN(87, \"GPIO87\"),\n+\tMT8189_TYPE0_PIN(88, \"GPIO88\"),\n+\tMT8189_TYPE0_PIN(89, \"GPIO89\"),\n+\tMT8189_TYPE0_PIN(90, \"GPIO90\"),\n+\tMT8189_TYPE0_PIN(91, \"GPIO91\"),\n+\tMT8189_TYPE0_PIN(92, \"GPIO92\"),\n+\tMT8189_TYPE0_PIN(93, \"GPIO93\"),\n+\tMT8189_TYPE0_PIN(94, \"GPIO94\"),\n+\tMT8189_TYPE0_PIN(95, \"GPIO95\"),\n+\tMT8189_TYPE0_PIN(96, \"GPIO96\"),\n+\tMT8189_TYPE0_PIN(97, \"GPIO97\"),\n+\tMT8189_TYPE0_PIN(98, \"GPIO98\"),\n+\tMT8189_TYPE0_PIN(99, \"GPIO99\"),\n+\tMT8189_TYPE0_PIN(100, \"GPIO100\"),\n+\tMT8189_TYPE0_PIN(101, \"GPIO101\"),\n+\tMT8189_TYPE0_PIN(102, \"GPIO102\"),\n+\tMT8189_TYPE0_PIN(103, \"GPIO103\"),\n+\tMT8189_TYPE0_PIN(104, \"GPIO104\"),\n+\tMT8189_TYPE0_PIN(105, \"GPIO105\"),\n+\tMT8189_TYPE0_PIN(106, \"GPIO106\"),\n+\tMT8189_TYPE0_PIN(107, \"GPIO107\"),\n+\tMT8189_TYPE0_PIN(108, \"GPIO108\"),\n+\tMT8189_TYPE0_PIN(109, \"GPIO109\"),\n+\tMT8189_TYPE0_PIN(110, \"GPIO110\"),\n+\tMT8189_TYPE0_PIN(111, \"GPIO111\"),\n+\tMT8189_TYPE0_PIN(112, \"GPIO112\"),\n+\tMT8189_TYPE0_PIN(113, \"GPIO113\"),\n+\tMT8189_TYPE0_PIN(114, \"GPIO114\"),\n+\tMT8189_TYPE0_PIN(115, \"GPIO115\"),\n+\tMT8189_TYPE0_PIN(116, \"GPIO116\"),\n+\tMT8189_TYPE0_PIN(117, \"GPIO117\"),\n+\tMT8189_TYPE0_PIN(118, \"GPIO118\"),\n+\tMT8189_TYPE0_PIN(119, \"GPIO119\"),\n+\tMT8189_TYPE0_PIN(120, \"GPIO120\"),\n+\tMT8189_TYPE0_PIN(121, \"GPIO121\"),\n+\tMT8189_TYPE0_PIN(122, \"GPIO122\"),\n+\tMT8189_TYPE0_PIN(123, \"GPIO123\"),\n+\tMT8189_TYPE0_PIN(124, \"GPIO124\"),\n+\tMT8189_TYPE0_PIN(125, \"GPIO125\"),\n+\tMT8189_TYPE0_PIN(126, \"GPIO126\"),\n+\tMT8189_TYPE0_PIN(127, \"GPIO127\"),\n+\tMT8189_TYPE0_PIN(128, \"GPIO128\"),\n+\tMT8189_TYPE0_PIN(129, \"GPIO129\"),\n+\tMT8189_TYPE0_PIN(130, \"GPIO130\"),\n+\tMT8189_TYPE0_PIN(131, \"GPIO131\"),\n+\tMT8189_TYPE0_PIN(132, \"GPIO132\"),\n+\tMT8189_TYPE0_PIN(133, \"GPIO133\"),\n+\tMT8189_TYPE0_PIN(134, \"GPIO134\"),\n+\tMT8189_TYPE0_PIN(135, \"GPIO135\"),\n+\tMT8189_TYPE0_PIN(136, \"GPIO136\"),\n+\tMT8189_TYPE0_PIN(137, \"GPIO137\"),\n+\tMT8189_TYPE0_PIN(138, \"GPIO138\"),\n+\tMT8189_TYPE0_PIN(139, \"GPIO139\"),\n+\tMT8189_TYPE0_PIN(140, \"GPIO140\"),\n+\tMT8189_TYPE0_PIN(141, \"GPIO141\"),\n+\tMT8189_TYPE0_PIN(142, \"GPIO142\"),\n+\tMT8189_TYPE0_PIN(143, \"GPIO143\"),\n+\tMT8189_TYPE0_PIN(144, \"GPIO144\"),\n+\tMT8189_TYPE0_PIN(145, \"GPIO145\"),\n+\tMT8189_TYPE0_PIN(146, \"GPIO146\"),\n+\tMT8189_TYPE0_PIN(147, \"GPIO147\"),\n+\tMT8189_TYPE0_PIN(148, \"GPIO148\"),\n+\tMT8189_TYPE0_PIN(149, \"GPIO149\"),\n+\tMT8189_TYPE0_PIN(150, \"GPIO150\"),\n+\tMT8189_TYPE0_PIN(151, \"GPIO151\"),\n+\tMT8189_TYPE0_PIN(152, \"GPIO152\"),\n+\tMT8189_TYPE0_PIN(153, \"GPIO153\"),\n+\tMT8189_TYPE0_PIN(154, \"GPIO154\"),\n+\tMT8189_TYPE0_PIN(155, \"GPIO155\"),\n+\tMT8189_TYPE1_PIN(156, \"GPIO156\"),\n+\tMT8189_TYPE1_PIN(157, \"GPIO157\"),\n+\tMT8189_TYPE1_PIN(158, \"GPIO158\"),\n+\tMT8189_TYPE1_PIN(159, \"GPIO159\"),\n+\tMT8189_TYPE1_PIN(160, \"GPIO160\"),\n+\tMT8189_TYPE1_PIN(161, \"GPIO161\"),\n+\tMT8189_TYPE1_PIN(162, \"GPIO162\"),\n+\tMT8189_TYPE1_PIN(163, \"GPIO163\"),\n+\tMT8189_TYPE1_PIN(164, \"GPIO164\"),\n+\tMT8189_TYPE1_PIN(165, \"GPIO165\"),\n+\tMT8189_TYPE1_PIN(166, \"GPIO166\"),\n+\tMT8189_TYPE1_PIN(167, \"GPIO167\"),\n+\tMT8189_TYPE1_PIN(168, \"GPIO168\"),\n+\tMT8189_TYPE1_PIN(169, \"GPIO169\"),\n+\tMT8189_TYPE1_PIN(170, \"GPIO170\"),\n+\tMT8189_TYPE1_PIN(171, \"GPIO171\"),\n+\tMT8189_TYPE1_PIN(172, \"GPIO172\"),\n+\tMT8189_TYPE1_PIN(173, \"GPIO173\"),\n+\tMT8189_TYPE1_PIN(174, \"GPIO174\"),\n+\tMT8189_TYPE1_PIN(175, \"GPIO175\"),\n+\tMT8189_TYPE1_PIN(176, \"GPIO176\"),\n+\tMT8189_TYPE1_PIN(177, \"GPIO177\"),\n+\tMT8189_TYPE1_PIN(178, \"GPIO178\"),\n+\tMT8189_TYPE1_PIN(179, \"GPIO179\"),\n+\tMT8189_TYPE2_PIN(180, \"GPIO180\"),\n+\tMT8189_TYPE2_PIN(181, \"GPIO181\"),\n+\tMT8189_TYPE0_PIN(182, \"GPIO182\"),\n };\n \n static const struct mtk_io_type_desc mt8189_io_type_desc[] = {\n \t[IO_TYPE_GRP0] = {\n \t\t.name = \"mt8189\",\n-\t\t.bias_set = mtk_pinconf_bias_set_v1,\n+\t\t.bias_set = mtk_pinconf_bias_set_pu_pd,\n+\t\t.drive_set = mtk_pinconf_drive_set_v1,\n+\t\t.input_enable = mtk_pinconf_input_enable_v1,\n+\t},\n+\t[IO_TYPE_GRP1] = {\n+\t\t.name = \"MSDC\",\n+\t\t.bias_set = mtk_pinconf_bias_set_pupd_r1_r0,\n+\t\t.drive_set = mtk_pinconf_drive_set_v1,\n+\t\t.input_enable = mtk_pinconf_input_enable_v1,\n+\t},\n+\t[IO_TYPE_GRP2] = {\n+\t\t.name = \"I2C\",\n+\t\t.bias_set = mtk_pinconf_bias_set_pu_pd_rsel,\n \t\t.drive_set = mtk_pinconf_drive_set_v1,\n \t\t.input_enable = mtk_pinconf_input_enable_v1,\n \t},\n", "prefixes": [ "v2", "2/4" ] }