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GET /api/patches/2217796/?format=api
{ "id": 2217796, "url": "http://patchwork.ozlabs.org/api/patches/2217796/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/D1C3B3DF-960F-40C7-BBD7-994359F0C8AD@vanvalzah.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<D1C3B3DF-960F-40C7-BBD7-994359F0C8AD@vanvalzah.com>", "list_archive_url": null, "date": "2026-03-29T03:25:41", "name": "igc: fix Tx timestamp timeout caused by unlocked TIMINCA write in adj fine", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "5fedeca90bf67be6349586a623466c072e506e6d", "submitter": { "id": 93009, "url": "http://patchwork.ozlabs.org/api/people/93009/?format=api", "name": "Bob Van Valzah", "email": "bob@vanvalzah.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/D1C3B3DF-960F-40C7-BBD7-994359F0C8AD@vanvalzah.com/mbox/", "series": [ { "id": 498057, "url": "http://patchwork.ozlabs.org/api/series/498057/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=498057", "date": "2026-03-29T03:25:41", "name": "igc: fix Tx timestamp timeout caused by unlocked TIMINCA write in adj fine", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498057/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217796/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217796/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=RT2+CUCK;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::136; 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a=rsa-sha256; c=relaxed/relaxed;\n d=vanvalzah-com.20230601.gappssmtp.com; s=20230601; t=1774754755;\n x=1775359555;\n darn=lists.osuosl.org;\n h=to:cc:date:message-id:subject:mime-version:from:from:to:cc:subject\n :date:message-id:reply-to;\n bh=Q3zHZR2nqCQ4BfQwwL3YtsGWqRQDle8jBml0c4WJz+U=;\n b=QyLzBgoVhdGc+Lu+13otaBD7woDCizviGr5zHHMV+y/88xPKKlUyqjESYe/NmgCcRN\n 06d6cIkF2NhUiNKRmlmAgoCrm/9IiEBNGee9SNtb0OQE6vd2N6ItIuvYNo6pxOu43cbe\n md0Wf+uCZ9dAmnlBFt+Tc15oCubU1N7cThsgtdGkNoC2fIpfXf/AM9zAZwsnIYwvnOV7\n 4juHNnr1ydQkDRwIaRJqYm5AbgsDfsThch/qIoU2vtQTW+KzHw57UPW9L4+Tlndq4jOG\n PEUJvhrrHKUyXF9N8Qz5NPHHcv+DCRbh3V85BlxA1U9jz+9qDMnZ6W4anvSgsRz/PNiI\n P1pw==", "X-Mailman-Original-Authentication-Results": [ "smtp4.osuosl.org;\n dmarc=none (p=none dis=none)\n header.from=vanvalzah.com", "smtp4.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=vanvalzah-com.20230601.gappssmtp.com\n header.i=@vanvalzah-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=QyLzBgoV" ], "Subject": "[Intel-wired-lan] [PATCH] igc: fix Tx timestamp timeout caused by\n unlocked TIMINCA write in adj fine", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Hi,\n\nWe found a race in igc_ptp_adjfine_i225() that causes \"Tx timestamp\ntimeout\" errors and eventually wedges EXTTS when a PTP grandmaster\n(ptp4l with hardware timestamping) runs concurrently with PHC\nfrequency discipline (any GPSDO calling clock_adjtime ADJ_FREQUENCY).\n\nRoot cause: igc_ptp_adjfine_i225() writes IGC_TIMINCA without holding\nany lock. Every other PTP clock operation in igc_ptp.c (adjtime,\ngettime, settime) holds tmreg_lock, but adjfine does not. When the\nincrement rate changes while the hardware is capturing a TX timestamp,\nthe captured value is corrupt. The driver retries for\nIGC_PTP_TX_TIMEOUT (15s), then logs the timeout and frees the skb.\nRepeated occurrences eventually prevent EXTTS from delivering events.\n\nThe attached reproducer (triggers in ~17 seconds on i226):\n\n One thread calling clock_adjtime(ADJ_FREQUENCY) at ~200k/s on the\n PHC, another sending UDP packets with SO_TIMESTAMPING requesting\n hardware TX timestamps at ~100k/s. A Python reproducer is at:\n https://github.com/bobvan/PePPAR-Fix/blob/main/tools/igc_tx_timeout_repro.py\n\n At realistic rates (1 Hz adjfine from a GPSDO + ptp4l at 128 Hz\n sync), the race triggers in ~30 minutes.\n\nThe attached patch holds ptp_tx_lock around the TIMINCA write and\nskips the write if any TX timestamps are pending (tx_tstamp[i].skb\n!= NULL), returning -EBUSY. This doesn't fully close the hardware\nrace (a new TX capture can start between the check and the write),\nbut at realistic rates the residual probability gives ~25 year MTBF\nvs ~30 minutes without the patch.\n\nA complete fix would likely require either disabling TX timestamping\naround TIMINCA writes (via TSYNCTXCTL), or making the timeout recovery\npath more robust so a single corrupt timestamp doesn't wedge the\nsubsystem. We'd welcome guidance from the igc maintainers on the\npreferred approach.\n\nTested on:\n - Intel i226 (TimeHAT v5 board on Raspberry Pi 5)\n - Kernel 6.12.62+rpt-rpi-2712 (Raspberry Pi OS)\n - Intel out-of-tree igc driver 5.4.0-7642.46\n - Stock upstream igc_ptp.c (same code, same bug)\n\n\tBob\n\n---\n\n drivers/net/ethernet/intel/igc/igc_ptp.c | 18 +++++++++++++++++-\n 1 file changed, 17 insertions(+), 1 deletion(-)\n\n if (scaled_ppm < 0) {\n neg_adj = 1;\n@@ -63,7 +65,21 @@ static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm)\n if (neg_adj)\n inca |= ISGN;\n\n- wr32(IGC_TIMINCA, inca);\n+ /* Changing the clock increment rate while a TX timestamp is being\n+ * captured by the hardware can corrupt the timestamp, causing the\n+ * driver to report \"Tx timestamp timeout\" and eventually wedging\n+ * the EXTTS subsystem. Serialize with pending TX timestamps:\n+ * skip the rate change if any are in flight.\n+ */\n+ spin_lock_irqsave(&igc->ptp_tx_lock, flags);\n+ for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) {\n+ if (igc->tx_tstamp[i].skb) {\n+ spin_unlock_irqrestore(&igc->ptp_tx_lock, flags);\n+ return -EBUSY;\n+ }\n+ }\n+ wr32(IGC_TIMINCA, inca);\n+ spin_unlock_irqrestore(&igc->ptp_tx_lock, flags);\n\n return 0;\n }\n--\n2.39.2", "diff": "diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c\nindex XXXXXXX..XXXXXXX 100644\n--- a/drivers/net/ethernet/intel/igc/igc_ptp.c\n+++ b/drivers/net/ethernet/intel/igc/igc_ptp.c\n@@ -47,8 +47,10 @@ static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm)\n {\n struct igc_adapter *igc = container_of(ptp, struct igc_adapter,\n ptp_caps);\n struct igc_hw *hw = &igc->hw;\n+ unsigned long flags;\n int neg_adj = 0;\n u64 rate;\n u32 inca;\n+ int i;\n\n", "prefixes": [] }