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GET /api/patches/2217785/?format=api
{ "id": 2217785, "url": "http://patchwork.ozlabs.org/api/patches/2217785/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260330144456.13551-10-akhilrajeev@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330144456.13551-10-akhilrajeev@nvidia.com>", "list_archive_url": null, "date": "2026-03-30T14:44:55", "name": "[v5,09/10] dmaengine: tegra: Add Tegra264 support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d28559497444a2956dba94a6a13dc3be674f913b", "submitter": { "id": 81965, "url": "http://patchwork.ozlabs.org/api/people/81965/?format=api", "name": "Akhil R", "email": "akhilrajeev@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260330144456.13551-10-akhilrajeev@nvidia.com/mbox/", "series": [ { "id": 498044, "url": "http://patchwork.ozlabs.org/api/series/498044/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=498044", "date": "2026-03-30T14:44:52", "name": "Add GPCDMA support in Tegra264", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/498044/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217785/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217785/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13430-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Akhil R <akhilrajeev@nvidia.com>", "To": "Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>, Rob Herring\n\t<robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley\n\t<conor+dt@kernel.org>, Thierry Reding <thierry.reding@gmail.com>, \"Jonathan\n Hunter\" <jonathanh@nvidia.com>, Laxman Dewangan <ldewangan@nvidia.com>,\n\tPhilipp Zabel <p.zabel@pengutronix.de>, <dmaengine@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "Akhil R <akhilrajeev@nvidia.com>, Frank Li <Frank.Li@nxp.com>", "Subject": "[PATCH v5 09/10] dmaengine: tegra: Add Tegra264 support", "Date": "Mon, 30 Mar 2026 20:14:55 +0530", "Message-ID": "<20260330144456.13551-10-akhilrajeev@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": 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"\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(7416014)(376014)(921020)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t1mCNhS93+qIU3nPF+n3iNN81BhH82Ocru3Dgj/WaI2KsfrSTK5e9fTvgGvFavWaTZP/1wmn3l6dAEzP50M1+B9jFfZ7V04K9kaQQCyCE6Sl+cAsOo9phjCup11iaMbC2NzheZB3jMY1r01/FCRNu6m04E8Yu7RbATgvP+A3ArEmK6/KCsNQwhe1afjxe49LKkRmJFQhUtzK2WU+hBtWr08G1DTVqtWw4XvkJJ2e2ldWra/9rc0jSQHLDNu9k5wC1bFx4FD1+WsIBMx3+UJhuIK2htK19X8vPjzkzRumsSvEYBRmtv/dRJ9VM7MJ2nPWgrhhyhyb43arAAWSsTodJ9l4udIP0wJcdJbcQL5a8PsMv6ENrYhRrREpZsqiZ6m92Z1YNYXz6w6t1d4j9hQFo6cjrvfbLA3GzWBz2JdPw2SQVMrzNaQbDG6pDARgka9f4", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Mar 2026 14:46:53.3937\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d25d8ba1-cec3-4a43-6dca-08de8e6b2f0b", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCY4PEPF0000EE39.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB9740" }, "content": "Add compatible and chip data to support GPCDMA in Tegra264, which has\ndifferences in register layout and address bits compared to previous\nversions.\n\nSigned-off-by: Akhil R <akhilrajeev@nvidia.com>\nReviewed-by: Frank Li <Frank.Li@nxp.com>\n---\n drivers/dma/tegra186-gpc-dma.c | 30 ++++++++++++++++++++++++++++++\n 1 file changed, 30 insertions(+)", "diff": "diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c\nindex 64743d852dda..0b7faf8bb80b 100644\n--- a/drivers/dma/tegra186-gpc-dma.c\n+++ b/drivers/dma/tegra186-gpc-dma.c\n@@ -1319,6 +1319,23 @@ static const struct tegra_dma_channel_regs tegra186_reg_offsets = {\n \t.fixed_pattern = 0x34,\n };\n \n+static const struct tegra_dma_channel_regs tegra264_reg_offsets = {\n+\t.csr = 0x0,\n+\t.status = 0x4,\n+\t.csre = 0x8,\n+\t.src = 0xc,\n+\t.dst = 0x10,\n+\t.src_high = 0x14,\n+\t.dst_high = 0x18,\n+\t.mc_seq = 0x1c,\n+\t.mmio_seq = 0x20,\n+\t.wcount = 0x24,\n+\t.wxfer = 0x28,\n+\t.wstatus = 0x2c,\n+\t.err_status = 0x34,\n+\t.fixed_pattern = 0x38,\n+};\n+\n static const struct tegra_dma_chip_data tegra186_dma_chip_data = {\n \t.nr_channels = 32,\n \t.addr_bits = 39,\n@@ -1349,6 +1366,16 @@ static const struct tegra_dma_chip_data tegra234_dma_chip_data = {\n \t.terminate = tegra_dma_pause_noerr,\n };\n \n+static const struct tegra_dma_chip_data tegra264_dma_chip_data = {\n+\t.nr_channels = 32,\n+\t.addr_bits = 41,\n+\t.channel_reg_size = SZ_64K,\n+\t.max_dma_count = SZ_1G,\n+\t.hw_support_pause = true,\n+\t.channel_regs = &tegra264_reg_offsets,\n+\t.terminate = tegra_dma_pause_noerr,\n+};\n+\n static const struct of_device_id tegra_dma_of_match[] = {\n \t{\n \t\t.compatible = \"nvidia,tegra186-gpcdma\",\n@@ -1359,6 +1386,9 @@ static const struct of_device_id tegra_dma_of_match[] = {\n \t}, {\n \t\t.compatible = \"nvidia,tegra234-gpcdma\",\n \t\t.data = &tegra234_dma_chip_data,\n+\t}, {\n+\t\t.compatible = \"nvidia,tegra264-gpcdma\",\n+\t\t.data = &tegra264_dma_chip_data,\n \t}, {\n \t},\n };\n", "prefixes": [ "v5", "09/10" ] }