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GET /api/patches/2217784/?format=api
{ "id": 2217784, "url": "http://patchwork.ozlabs.org/api/patches/2217784/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260330144456.13551-9-akhilrajeev@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330144456.13551-9-akhilrajeev@nvidia.com>", "list_archive_url": null, "date": "2026-03-30T14:44:54", "name": "[v5,08/10] dmaengine: tegra: Use iommu-map for stream ID", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3cd67aa33dd22de48b7308839d1d673df2c97af7", "submitter": { "id": 81965, "url": "http://patchwork.ozlabs.org/api/people/81965/?format=api", "name": "Akhil R", "email": "akhilrajeev@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260330144456.13551-9-akhilrajeev@nvidia.com/mbox/", "series": [ { "id": 498044, "url": "http://patchwork.ozlabs.org/api/series/498044/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=498044", "date": "2026-03-30T14:44:52", "name": "Add GPCDMA support in Tegra264", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/498044/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217784/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217784/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13429-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=PuJ0FRBd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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pr=C", "From": "Akhil R <akhilrajeev@nvidia.com>", "To": "Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>, Rob Herring\n\t<robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley\n\t<conor+dt@kernel.org>, Thierry Reding <thierry.reding@gmail.com>, \"Jonathan\n Hunter\" <jonathanh@nvidia.com>, Laxman Dewangan <ldewangan@nvidia.com>,\n\tPhilipp Zabel <p.zabel@pengutronix.de>, <dmaengine@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "Akhil R <akhilrajeev@nvidia.com>", "Subject": "[PATCH v5 08/10] dmaengine: tegra: Use iommu-map for stream ID", "Date": "Mon, 30 Mar 2026 20:14:54 +0530", "Message-ID": "<20260330144456.13551-9-akhilrajeev@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260330144456.13551-1-akhilrajeev@nvidia.com>", "References": "<20260330144456.13551-1-akhilrajeev@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3D:EE_|CH3PR12MB9023:EE_", "X-MS-Office365-Filtering-Correlation-Id": "459522b5-d1cc-4d65-e93b-08de8e6b2964", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|7416014|82310400026|1800799024|36860700016|376014|921020|22082099003|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\tlZBssmX4Xs0aPc039KQ9+J2eYy7RlnvqRnln0ICiFe2/WWcHeTgBT0JvD9GJAMqHzbe74C8GNmjfdLaJkAlON9shYMTPwH9DoUuFh0CoQmD/SmUxgFmhuSeHLovNMD0+4rD6f7k5xD+O8rSnpWIC5NYBs2jLNZ4jZLDoRz9xgbBsaDgE97TwnL2LT8ta0hjUFqpQPmMJ6Oi/qq1zAbXdilR9yvL9MVHkvzo2FI9hufdLctg0U8ke6iqsv3Vy0b4gRZvQ16uK3TYoQNz3ElJBpjCurWnwoFINkRrJmQcVPr8NbQqkHurLpJ85pg57Xn8OkUa1LCi2tQfhp77USwOe2dw8LKFmS0adswcYXdI6ed7DBDoc76uQiGM8d7QvsrCR4eCGBOyx++nX3NURcw2p5taZHyaa4gbc980g+DnUcYFD0rtpo4KYpZd/1oK497S+LuynXh5Y2mbJdOljZGFEtQCTrewtI8I9aUgoohRihrL1U+ZrWIQWQJc6LlDrbP9Mx9HiS6DDbuSkxMQSVv8AXijISGVeh/EsPc1q9FO9RjscAyEwYh2228GSIDcmsRHZQUNt5miPbMkGST95V7YtJN5d0PDomHD2JoDWAJ4l3iHb4T/I9fqtrhrtX+xlS8+A9S0U2D7Fk54kr0JP34RZ1K4NIBYQPk5txTsHbaH3IR4RdaQvfSwPi6T2OoR0QaiRD67SQc4N0gI7lMX1ALZRnjaSorAqrPv/nNwUgSGEiNLejjX8zf6Q1VBnI4fUwEbHdREwotzSodKp/mvv4omEQrmR+g5juZ7ocLXwagjAZ8gIlbPZnUdJxbJdnZTB3NU9", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(1800799024)(36860700016)(376014)(921020)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tE5WNI2N6yqjTysDanMnPiHWMD2c48agkwoYXawezrasJl9Fv7jZ1PkVUxy9lmkDIl2pdDgarn1VcgCRrE5l7vIY3SmaXDogJ698nElBctrchuE/azC3dSix6x1S2/304KnY9Y0cxN26mhZoB9zZC/EgPLxPxipnYszQiO/eAuwJR7h/cCj0YjeIdkjQcfIea1Jc57WAWtVZduWUGzKoW5WLrbIL3eyVDcnUDqOrY6DbITkTTD48c+1H9c4p005EvFYHLbMG/OwfzUsHHgCUkq3t6rvjmLNE5C4SFPgAuGIC5TemSBkNK6WwSSD3/kITavM5iCIgSgjzLHrYJ3Xv+KIOg4ZxLxo3CybmRn6cEbbk5uW4fB3Yvd/BW8ByIlU97GQ6JYaOKwsWKCzfBH9Jqer8aoA2lXqNuO0D3lVJb296fhR7CkvDA/uBgi/fAiq+q", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Mar 2026 14:46:43.8427\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 459522b5-d1cc-4d65-e93b-08de8e6b2964", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCY4PEPF0000EE3D.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB9023" }, "content": "Use 'iommu-map', when provided, to get the stream ID to be programmed\nfor each channel. Iterate over the channels registered and configure\neach channel device separately using of_dma_configure_id() to allow\nit to use a separate IOMMU domain for the transfer. However, do this\nin a second loop since the first loop populates the DMA device channels\nlist and async_device_register() registers the channels. Both are\nprerequisites for using the channel device in the next loop.\n\nChannels will continue to use the same global stream ID if the\n'iommu-map' property is not present in the device tree.\n\nSigned-off-by: Akhil R <akhilrajeev@nvidia.com>\n---\n drivers/dma/tegra186-gpc-dma.c | 57 ++++++++++++++++++++++++++++------\n 1 file changed, 48 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c\nindex 9bea2ffb3b9e..64743d852dda 100644\n--- a/drivers/dma/tegra186-gpc-dma.c\n+++ b/drivers/dma/tegra186-gpc-dma.c\n@@ -15,6 +15,7 @@\n #include <linux/module.h>\n #include <linux/of.h>\n #include <linux/of_dma.h>\n+#include <linux/of_device.h>\n #include <linux/platform_device.h>\n #include <linux/reset.h>\n #include <linux/slab.h>\n@@ -1380,9 +1381,13 @@ static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id)\n static int tegra_dma_probe(struct platform_device *pdev)\n {\n \tconst struct tegra_dma_chip_data *cdata = NULL;\n+\tstruct tegra_dma_channel *tdc;\n+\tstruct tegra_dma *tdma;\n+\tstruct dma_chan *chan;\n+\tstruct device *chdev;\n+\tbool use_iommu_map = false;\n \tunsigned int i;\n \tu32 stream_id;\n-\tstruct tegra_dma *tdma;\n \tint ret;\n \n \tcdata = of_device_get_match_data(&pdev->dev);\n@@ -1410,9 +1415,12 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \n \ttdma->dma_dev.dev = &pdev->dev;\n \n-\tif (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) {\n-\t\tdev_err(&pdev->dev, \"Missing iommu stream-id\\n\");\n-\t\treturn -EINVAL;\n+\tuse_iommu_map = of_property_present(pdev->dev.of_node, \"iommu-map\");\n+\tif (!use_iommu_map) {\n+\t\tif (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) {\n+\t\t\tdev_err(&pdev->dev, \"Missing iommu stream-id\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n \t}\n \n \tret = device_property_read_u32(&pdev->dev, \"dma-channel-mask\",\n@@ -1424,9 +1432,10 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \t\ttdma->chan_mask = TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK;\n \t}\n \n+\t/* Initialize vchan for each channel and populate the channels list */\n \tINIT_LIST_HEAD(&tdma->dma_dev.channels);\n \tfor (i = 0; i < cdata->nr_channels; i++) {\n-\t\tstruct tegra_dma_channel *tdc = &tdma->channels[i];\n+\t\ttdc = &tdma->channels[i];\n \n \t\t/* Check for channel mask */\n \t\tif (!(tdma->chan_mask & BIT(i)))\n@@ -1446,10 +1455,6 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \n \t\tvchan_init(&tdc->vc, &tdma->dma_dev);\n \t\ttdc->vc.desc_free = tegra_dma_desc_free;\n-\n-\t\t/* program stream-id for this channel */\n-\t\ttegra_dma_program_sid(tdc, stream_id);\n-\t\ttdc->stream_id = stream_id;\n \t}\n \n \tdma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(cdata->addr_bits));\n@@ -1483,6 +1488,7 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \ttdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize;\n \ttdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;\n \n+\t/* Register the DMA device and the channels */\n \tret = dmaenginem_async_device_register(&tdma->dma_dev);\n \tif (ret < 0) {\n \t\tdev_err_probe(&pdev->dev, ret,\n@@ -1490,6 +1496,39 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \t\treturn ret;\n \t}\n \n+\t/*\n+\t * Configure stream ID for each channel from the channels registered\n+\t * above. This is done in a separate iteration to ensure that only\n+\t * the channels available and registered for the DMA device are used.\n+\t */\n+\tlist_for_each_entry(chan, &tdma->dma_dev.channels, device_node) {\n+\t\tchdev = &chan->dev->device;\n+\t\ttdc = to_tegra_dma_chan(chan);\n+\n+\t\tif (use_iommu_map) {\n+\t\t\tchdev->bus = pdev->dev.bus;\n+\t\t\tdma_coerce_mask_and_coherent(chdev, DMA_BIT_MASK(cdata->addr_bits));\n+\n+\t\t\tret = of_dma_configure_id(chdev, pdev->dev.of_node,\n+\t\t\t\t\t\t true, &tdc->id);\n+\t\t\tif (ret)\n+\t\t\t\treturn dev_err_probe(chdev, ret,\n+\t\t\t\t\t \"Failed to configure IOMMU for channel %d\", tdc->id);\n+\n+\t\t\tif (!tegra_dev_iommu_get_stream_id(chdev, &stream_id)) {\n+\t\t\t\tdev_err(chdev, \"Failed to get stream ID for channel %d\\n\",\n+\t\t\t\t\ttdc->id);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\n+\t\t\tchan->dev->chan_dma_dev = true;\n+\t\t}\n+\n+\t\t/* program stream-id for this channel */\n+\t\ttegra_dma_program_sid(tdc, stream_id);\n+\t\ttdc->stream_id = stream_id;\n+\t}\n+\n \tret = devm_of_dma_controller_register(&pdev->dev, pdev->dev.of_node,\n \t\t\t\t\t tegra_dma_of_xlate, tdma);\n \tif (ret < 0) {\n", "prefixes": [ "v5", "08/10" ] }