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GET /api/patches/2217783/?format=api
{ "id": 2217783, "url": "http://patchwork.ozlabs.org/api/patches/2217783/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260330144456.13551-6-akhilrajeev@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330144456.13551-6-akhilrajeev@nvidia.com>", "list_archive_url": null, "date": "2026-03-30T14:44:51", "name": "[v5,05/10] dmaengine: tegra: Use struct for register offsets", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "213247889b46652e6119b0b7adf12fa22e079f62", "submitter": { "id": 81965, "url": "http://patchwork.ozlabs.org/api/people/81965/?format=api", "name": "Akhil R", "email": "akhilrajeev@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260330144456.13551-6-akhilrajeev@nvidia.com/mbox/", "series": [ { "id": 498044, "url": "http://patchwork.ozlabs.org/api/series/498044/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=498044", "date": "2026-03-30T14:44:52", "name": "Add GPCDMA support in Tegra264", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/498044/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217783/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217783/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13426-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=NTI+0ou/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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pr=C", "From": "Akhil R <akhilrajeev@nvidia.com>", "To": "Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>, Rob Herring\n\t<robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley\n\t<conor+dt@kernel.org>, Thierry Reding <thierry.reding@gmail.com>, \"Jonathan\n Hunter\" <jonathanh@nvidia.com>, Laxman Dewangan <ldewangan@nvidia.com>,\n\tPhilipp Zabel <p.zabel@pengutronix.de>, <dmaengine@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "Akhil R <akhilrajeev@nvidia.com>, Frank Li <Frank.Li@nxp.com>", "Subject": "[PATCH v5 05/10] dmaengine: tegra: Use struct for register offsets", "Date": "Mon, 30 Mar 2026 20:14:51 +0530", "Message-ID": "<20260330144456.13551-6-akhilrajeev@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260330144456.13551-1-akhilrajeev@nvidia.com>", "References": "<20260330144456.13551-1-akhilrajeev@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE38:EE_|SJ1PR12MB6049:EE_", "X-MS-Office365-Filtering-Correlation-Id": "e2b8a405-84cb-45e6-8e7d-08de8e6b1aed", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|36860700016|376014|7416014|1800799024|82310400026|56012099003|18002099003|22082099003|921020;", "X-Microsoft-Antispam-Message-Info": "\n\tkujinmfGZaAC3zRXSk1CccLBp10/3z9pF0z8N/YptAIXdrRasdtwutgB3R9FWof9JnRdPJcGxrBov5iD6ZSsI+/RH9RAIYRRIR/Tx5o7b5qin2nlQp9pLJUuQZFNnwuEUEYoRvfyEcx30MctDM3emY0Agv4LNKUb8aRkEeousLwe1LuNO5jRXqerff/pHnNL1iJvzI06h7HOREfVQ7tzDnp88YqAHgPQ7gzqk8k4Uyh+b3Ry5q2NZLPpk7NgupNXLs47vXkHgL9Lzh9GqsNl/19DTnfq945dsq/5QPk4HIXAZVRwkQWPkJodsNZOMbjqQMRHi9eP0yXjuu5PZcnR5+Hsxea5mMnFMsZooXku3Lw9f4SFVP8nJKyuL5ws1oTJ0t0AOzK/IRRZa8n8qr+QZSHEuYF7G6Z3BZpGp0p4n96uqJsuOZqnhtGfSSFa4kU8IefZHtTb+okDJWZtEtNV9jgVckrY8hf9zYjqlCxxfC0Ck2lJW5JlW06gIGxdmtw6eRDB6g+F+oFZJNOkf15kn7RZnKimQ3gPxxbHi39d9jEScyxVSvYDXQScpE/ObJuTmh0TbE0aQcKjIupTMfw6oGDQtezVQo1WZKESYOMs4v0ereBU/tUHDRiOOMhyVTH90A5n83cjYNyYiVaFB6YPLH3+Msj0Vvn8P5W7InxMJVwZWLeLHztyZko8/GflhGzF5yMjHSHRR8EG3PT2/ZXTXqAzm9REl+/sTtjfIT5J5hYCScn1GXZlrYnAm4/prfcULJWSLxoT5oRNn9329+m/DJJ4BoTxBw7R1xHZ1OUSy+Q2k2Gtm2w+dqD3Z/+kDSwn", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(7416014)(1800799024)(82310400026)(56012099003)(18002099003)(22082099003)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t7zCRyFS+8ExUFvCR4ydDSunyL7r09N/xUh8ps3R9+EU9dXh/jXQokCVnjwl/mBy4BHUwp2SzcSYgnwluRuon0Z15hPJQ9PYSvprGQUJEkpnt+xqgsLw5J/RVdnfx1nqni/EhOdsE0rUtkSwNL77lm4CGDd0+eQrIgx2MZ/JLDykAX/cNMaXOBJgBMJHc9bic9S0ffSAs/pWI5rBA5p0c2nsZnDPOkKnCLdknN4eql9/WZMaU45/22Pv/b5z+BOAm94LVlMcHfCVrg8bu6BdKBHzDsQUI7pcjrny2wwSm425F1Mxx6paDlGcxb/0QOBCkHshC4pK1pF7p6cpzBOl0clkN5nOY2GwEvcGx6/brhaYhTNhdzDVvPC8wRudvWgJiRD0lSuTqoQWUvj1n0DUtY6qyAsDx/BNi5/nptxOlq1ZC5AnE2PA8/2H37weWGQM9", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Mar 2026 14:46:19.6515\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e2b8a405-84cb-45e6-8e7d-08de8e6b1aed", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCY4PEPF0000EE38.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ1PR12MB6049" }, "content": "Repurpose the struct tegra_dma_channel_regs to define offsets for all the\nchannel registers. Previously, the struct only held the register values\nfor each transfer and was wrapped within tegra_dma_sg_req. Move the\nvalues directly into tegra_dma_sg_req and use channel_regs for\nstoring the register offsets. Update all register reads/writes to use\nthe struct channel_regs. This prepares for the register offset change\nin Tegra264.\n\nSigned-off-by: Akhil R <akhilrajeev@nvidia.com>\nReviewed-by: Frank Li <Frank.Li@nxp.com>\n---\n drivers/dma/tegra186-gpc-dma.c | 282 +++++++++++++++++----------------\n 1 file changed, 142 insertions(+), 140 deletions(-)", "diff": "diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c\nindex a0522a992ebc..b213c4ae07d2 100644\n--- a/drivers/dma/tegra186-gpc-dma.c\n+++ b/drivers/dma/tegra186-gpc-dma.c\n@@ -22,7 +22,6 @@\n #include \"virt-dma.h\"\n \n /* CSR register */\n-#define TEGRA_GPCDMA_CHAN_CSR\t\t\t0x00\n #define TEGRA_GPCDMA_CSR_ENB\t\t\tBIT(31)\n #define TEGRA_GPCDMA_CSR_IE_EOC\t\t\tBIT(30)\n #define TEGRA_GPCDMA_CSR_ONCE\t\t\tBIT(27)\n@@ -58,7 +57,6 @@\n #define TEGRA_GPCDMA_CSR_WEIGHT\t\t\tGENMASK(13, 10)\n \n /* STATUS register */\n-#define TEGRA_GPCDMA_CHAN_STATUS\t\t0x004\n #define TEGRA_GPCDMA_STATUS_BUSY\t\tBIT(31)\n #define TEGRA_GPCDMA_STATUS_ISE_EOC\t\tBIT(30)\n #define TEGRA_GPCDMA_STATUS_PING_PONG\t\tBIT(28)\n@@ -70,22 +68,13 @@\n #define TEGRA_GPCDMA_STATUS_IRQ_STA\t\tBIT(21)\n #define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA\tBIT(20)\n \n-#define TEGRA_GPCDMA_CHAN_CSRE\t\t\t0x008\n #define TEGRA_GPCDMA_CHAN_CSRE_PAUSE\t\tBIT(31)\n \n-/* Source address */\n-#define TEGRA_GPCDMA_CHAN_SRC_PTR\t\t0x00C\n-\n-/* Destination address */\n-#define TEGRA_GPCDMA_CHAN_DST_PTR\t\t0x010\n-\n /* High address pointer */\n-#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR\t\t0x014\n #define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR\t\tGENMASK(7, 0)\n #define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR\t\tGENMASK(23, 16)\n \n /* MC sequence register */\n-#define TEGRA_GPCDMA_CHAN_MCSEQ\t\t\t0x18\n #define TEGRA_GPCDMA_MCSEQ_DATA_SWAP\t\tBIT(31)\n #define TEGRA_GPCDMA_MCSEQ_REQ_COUNT\t\tGENMASK(30, 25)\n #define TEGRA_GPCDMA_MCSEQ_BURST\t\tGENMASK(24, 23)\n@@ -101,7 +90,6 @@\n #define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK\tGENMASK(6, 0)\n \n /* MMIO sequence register */\n-#define TEGRA_GPCDMA_CHAN_MMIOSEQ\t\t\t0x01c\n #define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF\t\tBIT(31)\n #define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH\t\tGENMASK(30, 28)\n #define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8\t\\\n@@ -120,17 +108,7 @@\n #define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD\t\tGENMASK(18, 16)\n #define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT\t\tGENMASK(8, 7)\n \n-/* Channel WCOUNT */\n-#define TEGRA_GPCDMA_CHAN_WCOUNT\t\t0x20\n-\n-/* Transfer count */\n-#define TEGRA_GPCDMA_CHAN_XFER_COUNT\t\t0x24\n-\n-/* DMA byte count status */\n-#define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS\t0x28\n-\n /* Error Status Register */\n-#define TEGRA_GPCDMA_CHAN_ERR_STATUS\t\t0x30\n #define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT\t8\n #define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK\t0xF\n #define TEGRA_GPCDMA_CHAN_ERR_TYPE(err)\t(\t\t\t\\\n@@ -143,16 +121,6 @@\n #define TEGRA_DMA_MC_SLAVE_ERR\t\t\t0xB\n #define TEGRA_DMA_MMIO_SLAVE_ERR\t\t0xA\n \n-/* Fixed Pattern */\n-#define TEGRA_GPCDMA_CHAN_FIXED_PATTERN\t\t0x34\n-\n-#define TEGRA_GPCDMA_CHAN_TZ\t\t\t0x38\n-#define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1\tBIT(0)\n-#define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1\t\tBIT(1)\n-\n-#define TEGRA_GPCDMA_CHAN_SPARE\t\t\t0x3c\n-#define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC\tBIT(16)\n-\n /*\n * If any burst is in flight and DMA paused then this is the time to complete\n * on-flight burst and update DMA status register.\n@@ -181,18 +149,24 @@ struct tegra_dma_chip_data {\n \tunsigned int nr_channels;\n \tunsigned int channel_reg_size;\n \tunsigned int max_dma_count;\n+\tconst struct tegra_dma_channel_regs *channel_regs;\n \tint (*terminate)(struct tegra_dma_channel *tdc);\n };\n \n /* DMA channel registers */\n struct tegra_dma_channel_regs {\n \tu32 csr;\n-\tu32 src_ptr;\n-\tu32 dst_ptr;\n-\tu32 high_addr_ptr;\n+\tu32 status;\n+\tu32 csre;\n+\tu32 src;\n+\tu32 dst;\n+\tu32 high_addr;\n \tu32 mc_seq;\n \tu32 mmio_seq;\n \tu32 wcount;\n+\tu32 wxfer;\n+\tu32 wstatus;\n+\tu32 err_status;\n \tu32 fixed_pattern;\n };\n \n@@ -205,7 +179,14 @@ struct tegra_dma_channel_regs {\n */\n struct tegra_dma_sg_req {\n \tunsigned int len;\n-\tstruct tegra_dma_channel_regs ch_regs;\n+\tu32 csr;\n+\tu32 src;\n+\tu32 dst;\n+\tu32 high_addr;\n+\tu32 mc_seq;\n+\tu32 mmio_seq;\n+\tu32 wcount;\n+\tu32 fixed_pattern;\n };\n \n /*\n@@ -228,19 +209,20 @@ struct tegra_dma_desc {\n * tegra_dma_channel: Channel specific information\n */\n struct tegra_dma_channel {\n-\tbool config_init;\n-\tchar name[30];\n-\tenum dma_transfer_direction sid_dir;\n-\tenum dma_status status;\n-\tint id;\n-\tint irq;\n-\tint slave_id;\n+\tconst struct tegra_dma_channel_regs *regs;\n \tstruct tegra_dma *tdma;\n \tstruct virt_dma_chan vc;\n \tstruct tegra_dma_desc *dma_desc;\n \tstruct dma_slave_config dma_sconfig;\n+\tenum dma_transfer_direction sid_dir;\n+\tenum dma_status status;\n \tunsigned int stream_id;\n \tunsigned long chan_base_offset;\n+\tbool config_init;\n+\tchar name[30];\n+\tint id;\n+\tint irq;\n+\tint slave_id;\n };\n \n /*\n@@ -288,22 +270,22 @@ static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)\n {\n \tdev_dbg(tdc2dev(tdc), \"DMA Channel %d name %s register dump:\\n\",\n \t\ttdc->id, tdc->name);\n-\tdev_dbg(tdc2dev(tdc), \"CSR %x STA %x CSRE %x SRC %x DST %x\\n\",\n-\t\ttdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR),\n-\t\ttdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS),\n-\t\ttdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE),\n-\t\ttdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR),\n-\t\ttdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR)\n-\t);\n-\tdev_dbg(tdc2dev(tdc), \"MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\\n\",\n-\t\ttdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ),\n-\t\ttdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ),\n-\t\ttdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT),\n-\t\ttdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT),\n-\t\ttdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS)\n-\t);\n+\tdev_dbg(tdc2dev(tdc), \"CSR %x STA %x CSRE %x\\n\",\n+\t\ttdc_read(tdc, tdc->regs->csr),\n+\t\ttdc_read(tdc, tdc->regs->status),\n+\t\ttdc_read(tdc, tdc->regs->csre));\n+\tdev_dbg(tdc2dev(tdc), \"SRC %x DST %x HI ADDR %x\\n\",\n+\t\ttdc_read(tdc, tdc->regs->src),\n+\t\ttdc_read(tdc, tdc->regs->dst),\n+\t\ttdc_read(tdc, tdc->regs->high_addr));\n+\tdev_dbg(tdc2dev(tdc), \"MCSEQ %x IOSEQ %x WCNT %x XFER %x WSTA %x\\n\",\n+\t\ttdc_read(tdc, tdc->regs->mc_seq),\n+\t\ttdc_read(tdc, tdc->regs->mmio_seq),\n+\t\ttdc_read(tdc, tdc->regs->wcount),\n+\t\ttdc_read(tdc, tdc->regs->wxfer),\n+\t\ttdc_read(tdc, tdc->regs->wstatus));\n \tdev_dbg(tdc2dev(tdc), \"DMA ERR_STA %x\\n\",\n-\t\ttdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS));\n+\t\ttdc_read(tdc, tdc->regs->err_status));\n }\n \n static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc,\n@@ -377,13 +359,13 @@ static int tegra_dma_pause(struct tegra_dma_channel *tdc)\n \tint ret;\n \tu32 val;\n \n-\tval = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);\n+\tval = tdc_read(tdc, tdc->regs->csre);\n \tval |= TEGRA_GPCDMA_CHAN_CSRE_PAUSE;\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);\n+\ttdc_write(tdc, tdc->regs->csre, val);\n \n \t/* Wait until busy bit is de-asserted */\n \tret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +\n-\t\t\ttdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,\n+\t\t\ttdc->chan_base_offset + tdc->regs->status,\n \t\t\tval,\n \t\t\t!(val & TEGRA_GPCDMA_STATUS_BUSY),\n \t\t\tTEGRA_GPCDMA_BURST_COMPLETE_TIME,\n@@ -419,9 +401,9 @@ static void tegra_dma_resume(struct tegra_dma_channel *tdc)\n {\n \tu32 val;\n \n-\tval = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);\n+\tval = tdc_read(tdc, tdc->regs->csre);\n \tval &= ~TEGRA_GPCDMA_CHAN_CSRE_PAUSE;\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);\n+\ttdc_write(tdc, tdc->regs->csre, val);\n \n \ttdc->status = DMA_IN_PROGRESS;\n }\n@@ -456,27 +438,27 @@ static void tegra_dma_disable(struct tegra_dma_channel *tdc)\n {\n \tu32 csr, status;\n \n-\tcsr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);\n+\tcsr = tdc_read(tdc, tdc->regs->csr);\n \n \t/* Disable interrupts */\n \tcsr &= ~TEGRA_GPCDMA_CSR_IE_EOC;\n \n \t/* Disable DMA */\n \tcsr &= ~TEGRA_GPCDMA_CSR_ENB;\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);\n+\ttdc_write(tdc, tdc->regs->csr, csr);\n \n \t/* Clear interrupt status if it is there */\n-\tstatus = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);\n+\tstatus = tdc_read(tdc, tdc->regs->status);\n \tif (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {\n \t\tdev_dbg(tdc2dev(tdc), \"%s():clearing interrupt\\n\", __func__);\n-\t\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status);\n+\t\ttdc_write(tdc, tdc->regs->status, status);\n \t}\n }\n \n static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc)\n {\n \tstruct tegra_dma_desc *dma_desc = tdc->dma_desc;\n-\tstruct tegra_dma_channel_regs *ch_regs;\n+\tstruct tegra_dma_sg_req *sg_req;\n \tint ret;\n \tu32 val;\n \n@@ -488,29 +470,29 @@ static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc)\n \n \t/* Configure next transfer immediately after DMA is busy */\n \tret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +\n-\t\t\ttdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,\n+\t\t\ttdc->chan_base_offset + tdc->regs->status,\n \t\t\tval,\n \t\t\t(val & TEGRA_GPCDMA_STATUS_BUSY), 0,\n \t\t\tTEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);\n \tif (ret)\n \t\treturn;\n \n-\tch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs;\n+\tsg_req = &dma_desc->sg_req[dma_desc->sg_idx];\n \n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);\n+\ttdc_write(tdc, tdc->regs->wcount, sg_req->wcount);\n+\ttdc_write(tdc, tdc->regs->src, sg_req->src);\n+\ttdc_write(tdc, tdc->regs->dst, sg_req->dst);\n+\ttdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr);\n \n \t/* Start DMA */\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,\n-\t\t ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);\n+\ttdc_write(tdc, tdc->regs->csr,\n+\t\t sg_req->csr | TEGRA_GPCDMA_CSR_ENB);\n }\n \n static void tegra_dma_start(struct tegra_dma_channel *tdc)\n {\n \tstruct tegra_dma_desc *dma_desc = tdc->dma_desc;\n-\tstruct tegra_dma_channel_regs *ch_regs;\n+\tstruct tegra_dma_sg_req *sg_req;\n \tstruct virt_dma_desc *vdesc;\n \n \tif (!dma_desc) {\n@@ -526,21 +508,21 @@ static void tegra_dma_start(struct tegra_dma_channel *tdc)\n \t\ttegra_dma_resume(tdc);\n \t}\n \n-\tch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs;\n+\tsg_req = &dma_desc->sg_req[dma_desc->sg_idx];\n \n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0);\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);\n+\ttdc_write(tdc, tdc->regs->wcount, sg_req->wcount);\n+\ttdc_write(tdc, tdc->regs->csr, 0);\n+\ttdc_write(tdc, tdc->regs->src, sg_req->src);\n+\ttdc_write(tdc, tdc->regs->dst, sg_req->dst);\n+\ttdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr);\n+\ttdc_write(tdc, tdc->regs->fixed_pattern, sg_req->fixed_pattern);\n+\ttdc_write(tdc, tdc->regs->mmio_seq, sg_req->mmio_seq);\n+\ttdc_write(tdc, tdc->regs->mc_seq, sg_req->mc_seq);\n+\ttdc_write(tdc, tdc->regs->csr, sg_req->csr);\n \n \t/* Start DMA */\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,\n-\t\t ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);\n+\ttdc_write(tdc, tdc->regs->csr,\n+\t\t sg_req->csr | TEGRA_GPCDMA_CSR_ENB);\n }\n \n static void tegra_dma_xfer_complete(struct tegra_dma_channel *tdc)\n@@ -601,19 +583,19 @@ static irqreturn_t tegra_dma_isr(int irq, void *dev_id)\n \tu32 status;\n \n \t/* Check channel error status register */\n-\tstatus = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);\n+\tstatus = tdc_read(tdc, tdc->regs->err_status);\n \tif (status) {\n \t\ttegra_dma_chan_decode_error(tdc, status);\n \t\ttegra_dma_dump_chan_regs(tdc);\n-\t\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);\n+\t\ttdc_write(tdc, tdc->regs->err_status, 0xFFFFFFFF);\n \t}\n \n \tspin_lock(&tdc->vc.lock);\n-\tstatus = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);\n+\tstatus = tdc_read(tdc, tdc->regs->status);\n \tif (!(status & TEGRA_GPCDMA_STATUS_ISE_EOC))\n \t\tgoto irq_done;\n \n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,\n+\ttdc_write(tdc, tdc->regs->status,\n \t\t TEGRA_GPCDMA_STATUS_ISE_EOC);\n \n \tif (!dma_desc)\n@@ -673,10 +655,10 @@ static int tegra_dma_stop_client(struct tegra_dma_channel *tdc)\n \t * to stop DMA engine from starting any more bursts for\n \t * the given client and wait for in flight bursts to complete\n \t */\n-\tcsr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);\n+\tcsr = tdc_read(tdc, tdc->regs->csr);\n \tcsr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK);\n \tcsr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;\n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);\n+\ttdc_write(tdc, tdc->regs->csr, csr);\n \n \t/* Wait for in flight data transfer to finish */\n \tudelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME);\n@@ -687,7 +669,7 @@ static int tegra_dma_stop_client(struct tegra_dma_channel *tdc)\n \n \tret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +\n \t\t\t\ttdc->chan_base_offset +\n-\t\t\t\tTEGRA_GPCDMA_CHAN_STATUS,\n+\t\t\t\ttdc->regs->status,\n \t\t\t\tstatus,\n \t\t\t\t!(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX |\n \t\t\t\tTEGRA_GPCDMA_STATUS_CHANNEL_RX)),\n@@ -739,14 +721,14 @@ static int tegra_dma_get_residual(struct tegra_dma_channel *tdc)\n \tunsigned int bytes_xfer, residual;\n \tu32 wcount = 0, status;\n \n-\twcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);\n+\twcount = tdc_read(tdc, tdc->regs->wxfer);\n \n \t/*\n \t * Set wcount = 0 if EOC bit is set. The transfer would have\n \t * already completed and the CHAN_XFER_COUNT could have updated\n \t * for the next transfer, specifically in case of cyclic transfers.\n \t */\n-\tstatus = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);\n+\tstatus = tdc_read(tdc, tdc->regs->status);\n \tif (status & TEGRA_GPCDMA_STATUS_ISE_EOC)\n \t\twcount = 0;\n \n@@ -893,7 +875,7 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,\n \t/* Configure default priority weight for the channel */\n \tcsr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);\n \n-\tmc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);\n+\tmc_seq = tdc_read(tdc, tdc->regs->mc_seq);\n \t/* retain stream-id and clean rest */\n \tmc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;\n \n@@ -916,16 +898,16 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,\n \tdma_desc->sg_count = 1;\n \tsg_req = dma_desc->sg_req;\n \n-\tsg_req[0].ch_regs.src_ptr = 0;\n-\tsg_req[0].ch_regs.dst_ptr = dest;\n-\tsg_req[0].ch_regs.high_addr_ptr =\n+\tsg_req[0].src = 0;\n+\tsg_req[0].dst = dest;\n+\tsg_req[0].high_addr =\n \t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));\n-\tsg_req[0].ch_regs.fixed_pattern = value;\n+\tsg_req[0].fixed_pattern = value;\n \t/* Word count reg takes value as (N +1) words */\n-\tsg_req[0].ch_regs.wcount = ((len - 4) >> 2);\n-\tsg_req[0].ch_regs.csr = csr;\n-\tsg_req[0].ch_regs.mmio_seq = 0;\n-\tsg_req[0].ch_regs.mc_seq = mc_seq;\n+\tsg_req[0].wcount = ((len - 4) >> 2);\n+\tsg_req[0].csr = csr;\n+\tsg_req[0].mmio_seq = 0;\n+\tsg_req[0].mc_seq = mc_seq;\n \tsg_req[0].len = len;\n \n \tdma_desc->cyclic = false;\n@@ -961,7 +943,7 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,\n \t/* Configure default priority weight for the channel */\n \tcsr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);\n \n-\tmc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);\n+\tmc_seq = tdc_read(tdc, tdc->regs->mc_seq);\n \t/* retain stream-id and clean rest */\n \tmc_seq &= (TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK) |\n \t\t (TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);\n@@ -985,17 +967,17 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,\n \tdma_desc->sg_count = 1;\n \tsg_req = dma_desc->sg_req;\n \n-\tsg_req[0].ch_regs.src_ptr = src;\n-\tsg_req[0].ch_regs.dst_ptr = dest;\n-\tsg_req[0].ch_regs.high_addr_ptr =\n+\tsg_req[0].src = src;\n+\tsg_req[0].dst = dest;\n+\tsg_req[0].high_addr =\n \t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));\n-\tsg_req[0].ch_regs.high_addr_ptr |=\n+\tsg_req[0].high_addr |=\n \t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));\n \t/* Word count reg takes value as (N +1) words */\n-\tsg_req[0].ch_regs.wcount = ((len - 4) >> 2);\n-\tsg_req[0].ch_regs.csr = csr;\n-\tsg_req[0].ch_regs.mmio_seq = 0;\n-\tsg_req[0].ch_regs.mc_seq = mc_seq;\n+\tsg_req[0].wcount = ((len - 4) >> 2);\n+\tsg_req[0].csr = csr;\n+\tsg_req[0].mmio_seq = 0;\n+\tsg_req[0].mc_seq = mc_seq;\n \tsg_req[0].len = len;\n \n \tdma_desc->cyclic = false;\n@@ -1049,7 +1031,7 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,\n \tif (flags & DMA_PREP_INTERRUPT)\n \t\tcsr |= TEGRA_GPCDMA_CSR_IE_EOC;\n \n-\tmc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);\n+\tmc_seq = tdc_read(tdc, tdc->regs->mc_seq);\n \t/* retain stream-id and clean rest */\n \tmc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;\n \n@@ -1096,14 +1078,14 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,\n \t\tdma_desc->bytes_req += len;\n \n \t\tif (direction == DMA_MEM_TO_DEV) {\n-\t\t\tsg_req[i].ch_regs.src_ptr = mem;\n-\t\t\tsg_req[i].ch_regs.dst_ptr = apb_ptr;\n-\t\t\tsg_req[i].ch_regs.high_addr_ptr =\n+\t\t\tsg_req[i].src = mem;\n+\t\t\tsg_req[i].dst = apb_ptr;\n+\t\t\tsg_req[i].high_addr =\n \t\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));\n \t\t} else if (direction == DMA_DEV_TO_MEM) {\n-\t\t\tsg_req[i].ch_regs.src_ptr = apb_ptr;\n-\t\t\tsg_req[i].ch_regs.dst_ptr = mem;\n-\t\t\tsg_req[i].ch_regs.high_addr_ptr =\n+\t\t\tsg_req[i].src = apb_ptr;\n+\t\t\tsg_req[i].dst = mem;\n+\t\t\tsg_req[i].high_addr =\n \t\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));\n \t\t}\n \n@@ -1111,10 +1093,10 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,\n \t\t * Word count register takes input in words. Writing a value\n \t\t * of N into word count register means a req of (N+1) words.\n \t\t */\n-\t\tsg_req[i].ch_regs.wcount = ((len - 4) >> 2);\n-\t\tsg_req[i].ch_regs.csr = csr;\n-\t\tsg_req[i].ch_regs.mmio_seq = mmio_seq;\n-\t\tsg_req[i].ch_regs.mc_seq = mc_seq;\n+\t\tsg_req[i].wcount = ((len - 4) >> 2);\n+\t\tsg_req[i].csr = csr;\n+\t\tsg_req[i].mmio_seq = mmio_seq;\n+\t\tsg_req[i].mc_seq = mc_seq;\n \t\tsg_req[i].len = len;\n \t}\n \n@@ -1186,7 +1168,7 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_l\n \n \tmmio_seq |= FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1);\n \n-\tmc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);\n+\tmc_seq = tdc_read(tdc, tdc->regs->mc_seq);\n \t/* retain stream-id and clean rest */\n \tmc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;\n \n@@ -1217,24 +1199,24 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_l\n \tfor (i = 0; i < period_count; i++) {\n \t\tmmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);\n \t\tif (direction == DMA_MEM_TO_DEV) {\n-\t\t\tsg_req[i].ch_regs.src_ptr = mem;\n-\t\t\tsg_req[i].ch_regs.dst_ptr = apb_ptr;\n-\t\t\tsg_req[i].ch_regs.high_addr_ptr =\n+\t\t\tsg_req[i].src = mem;\n+\t\t\tsg_req[i].dst = apb_ptr;\n+\t\t\tsg_req[i].high_addr =\n \t\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));\n \t\t} else if (direction == DMA_DEV_TO_MEM) {\n-\t\t\tsg_req[i].ch_regs.src_ptr = apb_ptr;\n-\t\t\tsg_req[i].ch_regs.dst_ptr = mem;\n-\t\t\tsg_req[i].ch_regs.high_addr_ptr =\n+\t\t\tsg_req[i].src = apb_ptr;\n+\t\t\tsg_req[i].dst = mem;\n+\t\t\tsg_req[i].high_addr =\n \t\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));\n \t\t}\n \t\t/*\n \t\t * Word count register takes input in words. Writing a value\n \t\t * of N into word count register means a req of (N+1) words.\n \t\t */\n-\t\tsg_req[i].ch_regs.wcount = ((len - 4) >> 2);\n-\t\tsg_req[i].ch_regs.csr = csr;\n-\t\tsg_req[i].ch_regs.mmio_seq = mmio_seq;\n-\t\tsg_req[i].ch_regs.mc_seq = mc_seq;\n+\t\tsg_req[i].wcount = ((len - 4) >> 2);\n+\t\tsg_req[i].csr = csr;\n+\t\tsg_req[i].mmio_seq = mmio_seq;\n+\t\tsg_req[i].mc_seq = mc_seq;\n \t\tsg_req[i].len = len;\n \n \t\tmem += len;\n@@ -1304,11 +1286,28 @@ static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,\n \treturn chan;\n }\n \n+static const struct tegra_dma_channel_regs tegra186_reg_offsets = {\n+\t.csr = 0x0,\n+\t.status = 0x4,\n+\t.csre = 0x8,\n+\t.src = 0xc,\n+\t.dst = 0x10,\n+\t.high_addr = 0x14,\n+\t.mc_seq = 0x18,\n+\t.mmio_seq = 0x1c,\n+\t.wcount = 0x20,\n+\t.wxfer = 0x24,\n+\t.wstatus = 0x28,\n+\t.err_status = 0x30,\n+\t.fixed_pattern = 0x34,\n+};\n+\n static const struct tegra_dma_chip_data tegra186_dma_chip_data = {\n \t.nr_channels = 32,\n \t.channel_reg_size = SZ_64K,\n \t.max_dma_count = SZ_1G,\n \t.hw_support_pause = false,\n+\t.channel_regs = &tegra186_reg_offsets,\n \t.terminate = tegra_dma_stop_client,\n };\n \n@@ -1317,6 +1316,7 @@ static const struct tegra_dma_chip_data tegra194_dma_chip_data = {\n \t.channel_reg_size = SZ_64K,\n \t.max_dma_count = SZ_1G,\n \t.hw_support_pause = true,\n+\t.channel_regs = &tegra186_reg_offsets,\n \t.terminate = tegra_dma_pause,\n };\n \n@@ -1325,6 +1325,7 @@ static const struct tegra_dma_chip_data tegra234_dma_chip_data = {\n \t.channel_reg_size = SZ_64K,\n \t.max_dma_count = SZ_1G,\n \t.hw_support_pause = true,\n+\t.channel_regs = &tegra186_reg_offsets,\n \t.terminate = tegra_dma_pause_noerr,\n };\n \n@@ -1345,7 +1346,7 @@ MODULE_DEVICE_TABLE(of, tegra_dma_of_match);\n \n static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id)\n {\n-\tunsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);\n+\tunsigned int reg_val = tdc_read(tdc, tdc->regs->mc_seq);\n \n \treg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK);\n \treg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);\n@@ -1353,7 +1354,7 @@ static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id)\n \treg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id);\n \treg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK, stream_id);\n \n-\ttdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val);\n+\ttdc_write(tdc, tdc->regs->mc_seq, reg_val);\n \treturn 0;\n }\n \n@@ -1419,6 +1420,7 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \t\ttdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET +\n \t\t\t\t\ti * cdata->channel_reg_size;\n \t\tsnprintf(tdc->name, sizeof(tdc->name), \"gpcdma.%d\", i);\n+\t\ttdc->regs = cdata->channel_regs;\n \t\ttdc->tdma = tdma;\n \t\ttdc->id = i;\n \t\ttdc->slave_id = -1;\n", "prefixes": [ "v5", "05/10" ] }