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GET /api/patches/2217772/?format=api
{ "id": 2217772, "url": "http://patchwork.ozlabs.org/api/patches/2217772/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260330144456.13551-8-akhilrajeev@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330144456.13551-8-akhilrajeev@nvidia.com>", "list_archive_url": null, "date": "2026-03-30T14:44:53", "name": "[v5,07/10] dmaengine: tegra: Use managed DMA controller registration", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "30a688feb458a9f4b52761b7bff0e88e97ef08a4", "submitter": { "id": 81965, "url": "http://patchwork.ozlabs.org/api/people/81965/?format=api", "name": "Akhil R", "email": "akhilrajeev@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260330144456.13551-8-akhilrajeev@nvidia.com/mbox/", "series": [ { "id": 498044, "url": "http://patchwork.ozlabs.org/api/series/498044/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=498044", "date": "2026-03-30T14:44:52", "name": "Add GPCDMA support in Tegra264", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/498044/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217772/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217772/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13428-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=bGY69NDB;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; 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pr=C", "From": "Akhil R <akhilrajeev@nvidia.com>", "To": "Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>, Rob Herring\n\t<robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley\n\t<conor+dt@kernel.org>, Thierry Reding <thierry.reding@gmail.com>, \"Jonathan\n Hunter\" <jonathanh@nvidia.com>, Laxman Dewangan <ldewangan@nvidia.com>,\n\tPhilipp Zabel <p.zabel@pengutronix.de>, <dmaengine@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "Akhil R <akhilrajeev@nvidia.com>, Frank Li <frank.li@nxp.com>", "Subject": "[PATCH v5 07/10] dmaengine: tegra: Use managed DMA controller\n registration", "Date": "Mon, 30 Mar 2026 20:14:53 +0530", "Message-ID": "<20260330144456.13551-8-akhilrajeev@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260330144456.13551-1-akhilrajeev@nvidia.com>", "References": "<20260330144456.13551-1-akhilrajeev@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE39:EE_|CH1PR12MB9576:EE_", "X-MS-Office365-Filtering-Correlation-Id": "4c4f9079-6f0e-4475-8d3e-08de8e6b25fe", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|7416014|921020|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n\t3H4OItW5uaK7AwNIzHe2XMj2Fe6wyTShyHukwFGhDsDG6f/FwP1k41ZvkktZzGPU4R4urMFH3UUGhRmuIp4K2T+Z1eVOnaeglsChE/4PRd0hlBQs6nOYBwnunJcF1/UZfNTtAbQ0PEGmVBeR0doLHlV+rDy1zzQCepxJMst0b97s82fwdGLF1aJH5/DtLS+uxFMXihpN0W6AXVvXLbWCYGL7737/P4vu/CdevsVVVTWaTWtU3R/BUbTmyMLvtfriw8RBwfRRhf9/wYJyW065D9Mc8uWmdRq5Zkxz7u1ohTBeLS5VFCieehbgTTP97vZoWetiWfsrBwiQpBh8zQuAQuwT7OUXc1eXHWY/A5gegVyqeMC/9qPtnYJ9Ugz1eMfizm1lYaSeJ7xmRQV6hGwmAv1vYgAg5CSvtySGXHPeZpQfy37zPXrs6TJtNGJu5XVLw5DG3OP6OVdH4NO/n6OlH6d4uc0PQBtSUVw1V4quWZhJ90Vav1qBDmUju9Ftc9oW5FnZoTi4hlJI8Mv6yi6tq1Oxxs7i2gUOGUugBkZPyjA/oh5Ow+/peUpQqVVFUC1/GxqFr3xHR9hxDLudGTXT0OjkTPwUo4efFnUDGyqjAXdTPC6LluVVAV2Y65Ql9aa0E1kLYQskQPd1yKnxBP+XXTkYlp76CMeabjV/YOSR/7LnA0cu5FbP2dOgbF+aBDf+uni3z8BESeyTcz5oiKn2RmCxXakTMUD1Z2jh8NaiVzEc6kRzBPOSseAmUYcZvgrHeulkGKC0SQCg6GpaQT8LrBtVyO/YcuWnRfkKHWoJ22R4eJuB4OJ1QZfnsY4nEm5L", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(7416014)(921020)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tL/mDl5Fv/kRvRDwME1BPWX1bsDMP+fT5SHza2nnW1btlqFQv/zGQTnTcq90fABlAppOhFpXtaJJxLqXCQTOzc8A1eirA2efkQcIRDgm3iBcw2wPjvVvUFGWBDDPjmPS+MtFqR9b0EIjBHod3X+tTQgE2GnGnmnJn2ZeULaYqm6TN6vS2EDpH1gZIN969VH+NrKiwSsQK3QPVcjHAvhhSF7UJUlGJmWpMZ+0wmY3/19fxYZz6DKM8uIMMoocZ+jakskGfERRDcnM+FEISGdxGiRf4++yLcDNaeEhFOrapAzjXtME9u1CWg7CN5DRgN9I86RTKJC8+N+QiepbRFntWlkBF+ANckNPER3Ar62eu4bVnANp6n0bB8PfxanhlXmu9csnh9Mh6WfW0JlRwSkfN88UFaYd8cuX/rtz7AXo/AOPt9bQUGV7l1tfwg+gLxYdW", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Mar 2026 14:46:38.2223\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4c4f9079-6f0e-4475-8d3e-08de8e6b25fe", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCY4PEPF0000EE39.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH1PR12MB9576" }, "content": "Switch to managed registration in probe. This simplifies the error\npaths in the probe and also removes the requirement of the driver\nremove function.\n\nSigned-off-by: Akhil R <akhilrajeev@nvidia.com>\nSuggested-by: Frank Li <frank.li@nxp.com>\n---\n drivers/dma/tegra186-gpc-dma.c | 19 ++++---------------\n 1 file changed, 4 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c\nindex 3ac43ad19ed6..9bea2ffb3b9e 100644\n--- a/drivers/dma/tegra186-gpc-dma.c\n+++ b/drivers/dma/tegra186-gpc-dma.c\n@@ -1483,37 +1483,27 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \ttdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize;\n \ttdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;\n \n-\tret = dma_async_device_register(&tdma->dma_dev);\n+\tret = dmaenginem_async_device_register(&tdma->dma_dev);\n \tif (ret < 0) {\n \t\tdev_err_probe(&pdev->dev, ret,\n \t\t\t \"GPC DMA driver registration failed\\n\");\n \t\treturn ret;\n \t}\n \n-\tret = of_dma_controller_register(pdev->dev.of_node,\n-\t\t\t\t\t tegra_dma_of_xlate, tdma);\n+\tret = devm_of_dma_controller_register(&pdev->dev, pdev->dev.of_node,\n+\t\t\t\t\t tegra_dma_of_xlate, tdma);\n \tif (ret < 0) {\n \t\tdev_err_probe(&pdev->dev, ret,\n \t\t\t \"GPC DMA OF registration failed\\n\");\n-\n-\t\tdma_async_device_unregister(&tdma->dma_dev);\n \t\treturn ret;\n \t}\n \n-\tdev_info(&pdev->dev, \"GPC DMA driver register %lu channels\\n\",\n+\tdev_info(&pdev->dev, \"GPC DMA driver registered %lu channels\\n\",\n \t\t hweight_long(tdma->chan_mask));\n \n \treturn 0;\n }\n \n-static void tegra_dma_remove(struct platform_device *pdev)\n-{\n-\tstruct tegra_dma *tdma = platform_get_drvdata(pdev);\n-\n-\tof_dma_controller_free(pdev->dev.of_node);\n-\tdma_async_device_unregister(&tdma->dma_dev);\n-}\n-\n static int __maybe_unused tegra_dma_pm_suspend(struct device *dev)\n {\n \tstruct tegra_dma *tdma = dev_get_drvdata(dev);\n@@ -1564,7 +1554,6 @@ static struct platform_driver tegra_dma_driver = {\n \t\t.of_match_table = tegra_dma_of_match,\n \t},\n \t.probe\t\t= tegra_dma_probe,\n-\t.remove\t\t= tegra_dma_remove,\n };\n \n module_platform_driver(tegra_dma_driver);\n", "prefixes": [ "v5", "07/10" ] }