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GET /api/patches/2217717/?format=api
{ "id": 2217717, "url": "http://patchwork.ozlabs.org/api/patches/2217717/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/patch-20429-tamar@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<patch-20429-tamar@arm.com>", "list_archive_url": null, "date": "2026-03-30T12:10:36", "name": "AArch64: Add if-conversion target cost model [PR123017][GCC 15 backport]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0cddd4a71d7d60ab46c57010a0c17d40ce723a90", "submitter": { "id": 69689, "url": "http://patchwork.ozlabs.org/api/people/69689/?format=api", "name": "Tamar Christina", "email": "Tamar.Christina@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/patch-20429-tamar@arm.com/mbox/", "series": [ { "id": 498013, "url": "http://patchwork.ozlabs.org/api/series/498013/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=498013", "date": "2026-03-30T12:10:36", "name": "AArch64: Add if-conversion target cost model [PR123017][GCC 15 backport]", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498013/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217717/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217717/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=ffkv7yYB;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=ffkv7yYB;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DU2PEPF00028D01.eurprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch implements an if-conversion cost model for AArch64. AArch64 has a\nnumber of conditional instructions that need to be accounted for, however this\ninitial version keeps things simple and is only really concerned about csel.\n\nThe issue specifically with csel is that it may have to wait for two argument\nto be evaluated before it can be executed. This means it has a direct\ncorrelation to increases in dynamic instructions.\n\nTo fix this I add a new tuning parameter that indicates a rough estimation of\nthe branch misprediction cost of a branch. We then accept if-conversion while\nthe cost of this multiplied by the cost of branches is cheaper.\n\nThere is a basic detection of CINC and CSET because these usually are ok. We\nalso accept all if-conversion when not inside a loop. Because CE is not an RTL\nSSA pass we can't do more extensive checks like checking if the csel is a loop\ncarried dependency. As such this is a best effort thing and intends to catch the\nmost egregious cases like the above.\n\nThis recovers the ~25% performance loss in zstd decoding and gives better\nresults than GCC 14 which was before the regression happened.\n\nAdditionally I've benchmarked on a number of cores all the attached examples\nand checked various cases. On average the patch gives an improvement between\n20-40%.\n\n[1] https://github.com/facebook/zstd/pull/4418#issuecomment-3004606000\n\nBootstrapped and regtested on aarch64-none-linux-gnu and no regressions.\n\nPushed to GCC-15 branch.\n\nThanks,\nTamar\n\ngcc/ChangeLog:\n\n\tPR target/123017\n\t* config/aarch64/aarch64-json-schema.h: Add br_mispredict_factor.\n\t* config/aarch64/aarch64-json-tunings-parser-generated.inc\n\t(parse_branch_costs): Add br_mispredict_factor.\n\t* config/aarch64/aarch64-json-tunings-printer-generated.inc\n\t(serialize_branch_costs): Add br_mispredict_factor.\n\t* config/aarch64/aarch64-protos.h (struct cpu_branch_cost): Add\n\tbr_mispredict_factor.\n\t* config/aarch64/aarch64.cc (aarch64_max_noce_ifcvt_seq_cost,\n\taarch64_noce_conversion_profitable_p,\n\tTARGET_MAX_NOCE_IFCVT_SEQ_COST,\n\tTARGET_NOCE_CONVERSION_PROFITABLE_P): New.\n\t* config/aarch64/tuning_models/generic.h (generic_branch_cost): Add\n\tbr_mispredict_factor.\n\t* config/aarch64/tuning_models/generic_armv8_a.h: Remove\n\tgeneric_armv8_a_branch_cost and use generic_branch_cost.\n\ngcc/testsuite/ChangeLog:\n\n\tPR target/123017\n\t* gcc.target/aarch64/pr123017_1.c: New test.\n\t* gcc.target/aarch64/pr123017_2.c: New test.\n\t* gcc.target/aarch64/pr123017_3.c: New test.\n\t* gcc.target/aarch64/pr123017_4.c: New test.\n\t* gcc.target/aarch64/pr123017_5.c: New test.\n\t* gcc.target/aarch64/pr123017_6.c: New test.\n\t* gcc.target/aarch64/pr123017_7.c: New test.\n\n---\n\n\n--", "diff": "diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h\nindex e1caf802d66183590b7e7e31180f4d8317f09e7a..eeaafd5d25b970849b8599f610836498b13da798 100644\n--- a/gcc/config/aarch64/aarch64-protos.h\n+++ b/gcc/config/aarch64/aarch64-protos.h\n@@ -481,6 +481,7 @@ struct cpu_branch_cost\n {\n const int predictable; /* Predictable branch or optimizing for size. */\n const int unpredictable; /* Unpredictable branch or optimizing for speed. */\n+ const int br_mispredict_factor; /* Scale factor for cost of misprediction on branches. */\n };\n \n /* Control approximate alternatives to certain FP operators. */\ndiff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\nindex a39e7c0eaef6fa7f8a29d998cfdd4661d3330138..c2fe272d18cd6dfcf587e6af696b6b351652fea1 100644\n--- a/gcc/config/aarch64/aarch64.cc\n+++ b/gcc/config/aarch64/aarch64.cc\n@@ -97,6 +97,7 @@\n #include \"ipa-prop.h\"\n #include \"ipa-fnsummary.h\"\n #include \"hash-map.h\"\n+#include \"ifcvt.h\"\n \n /* This file should be included last. */\n #include \"target-def.h\"\n@@ -2097,6 +2098,116 @@ aarch64_preferred_else_value (unsigned, tree, unsigned int nops, tree *ops)\n return nops == 3 ? ops[2] : ops[0];\n }\n \n+/* Implement TARGET_MAX_NOCE_IFCVT_SEQ_COST. If an explicit max was set then\n+ honor it, otherwise apply a tuning specific scale to branch costs. */\n+\n+static unsigned int\n+aarch64_max_noce_ifcvt_seq_cost (edge e)\n+{\n+ bool predictable_p = predictable_edge_p (e);\n+ if (predictable_p)\n+ {\n+ if (OPTION_SET_P (param_max_rtl_if_conversion_predictable_cost))\n+\treturn param_max_rtl_if_conversion_predictable_cost;\n+ }\n+ else\n+ {\n+ if (OPTION_SET_P (param_max_rtl_if_conversion_unpredictable_cost))\n+\treturn param_max_rtl_if_conversion_unpredictable_cost;\n+ }\n+\n+ /* For modern machines with long speculative execution chains and modern\n+ branch prediction the penalty of the branch misprediction needs to weighed\n+ against the cost of executing the instructions unconditionally. RISC cores\n+ tend to not have that deep pipelines and so the cost of mispredictions can\n+ be reasonably cheap. */\n+\n+ bool speed_p = optimize_function_for_speed_p (cfun);\n+ return BRANCH_COST (speed_p, predictable_p)\n+\t * aarch64_tune_params.branch_costs->br_mispredict_factor;\n+}\n+\n+/* Return true if SEQ is a good candidate as a replacement for the\n+ if-convertible sequence described in IF_INFO. AArch64 has a range of\n+ branchless statements and not all of them are potentially problematic. For\n+ instance a cset is usually beneficial whereas a csel is more complicated. */\n+\n+static bool\n+aarch64_noce_conversion_profitable_p (rtx_insn *seq,\n+\t\t\t\t struct noce_if_info *if_info)\n+{\n+ /* If not in a loop, just accept all if-conversion as the branch predictor\n+ won't have anything to train on. So assume sequences are essentially\n+ unpredictable. ce1 is in CFG mode still while ce2 is outside. For ce2\n+ accept limited if-conversion based on the shape of the instruction. */\n+ if (current_loops\n+ && (!if_info->test_bb->loop_father\n+\t || !if_info->test_bb->loop_father->header\n+\t || bb_loop_depth (if_info->test_bb->loop_father->header) == 0))\n+ return true;\n+\n+ /* For now we only care about csel speciifcally. */\n+ bool is_csel_p = true;\n+\n+ if (if_info->then_simple\n+ && if_info->a != NULL_RTX\n+ && !REG_P (if_info->a)\n+ && !SUBREG_P (if_info->a))\n+ is_csel_p = false;\n+\n+ if (if_info->else_simple\n+ && if_info->b != NULL_RTX\n+ && !REG_P (if_info->b)\n+ && !SUBREG_P (if_info->b))\n+ is_csel_p = false;\n+\n+ for (rtx_insn *insn = seq; is_csel_p && insn; insn = NEXT_INSN (insn))\n+ {\n+ rtx set = single_set (insn);\n+ if (!set)\n+\tcontinue;\n+\n+ rtx src = SET_SRC (set);\n+ rtx dst = SET_DEST (set);\n+ machine_mode mode = GET_MODE (src);\n+ if (GET_MODE_CLASS (mode) != MODE_INT)\n+\tcontinue;\n+\n+ switch (GET_CODE (src))\n+\t{\n+\tcase PLUS:\n+\tcase MINUS:\n+\t {\n+\t /* Likely a CINC. */\n+\t if (REG_P (dst)\n+\t\t&& (REG_P (XEXP (src, 0)) || SUBREG_P (XEXP (src, 0)))\n+\t\t&& (XEXP (src, 1) == CONST1_RTX (mode)\n+\t\t || XEXP (src, 1) == CONSTM1_RTX (mode)))\n+\t is_csel_p = false;\n+\t break;\n+\t }\n+\tdefault:\n+\t break;\n+\t}\n+ }\n+\n+ /* For now accept every variant but csel unconditionally because CSEL usually\n+ means you have to wait for two values to be computed. */\n+ if (!is_csel_p)\n+ return true;\n+\n+ /* TODO: Add detecting of csel, cinc, cset etc and take profiling in\n+\t consideration. For now this basic costing is enough to cover\n+\t most cases. */\n+ if (if_info->speed_p)\n+ {\n+ unsigned cost = seq_cost (seq, true);\n+ return cost <= if_info->max_seq_cost;\n+ }\n+\n+ return default_noce_conversion_profitable_p (seq, if_info);\n+}\n+\n /* Implement TARGET_HARD_REGNO_NREGS. */\n \n static unsigned int\n@@ -31993,6 +32104,13 @@ aarch64_libgcc_floating_mode_supported_p\n #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \\\n aarch64_atomic_assign_expand_fenv\n \n+/* If-conversion costs. */\n+#undef TARGET_MAX_NOCE_IFCVT_SEQ_COST\n+#define TARGET_MAX_NOCE_IFCVT_SEQ_COST aarch64_max_noce_ifcvt_seq_cost\n+\n+#undef TARGET_NOCE_CONVERSION_PROFITABLE_P\n+#define TARGET_NOCE_CONVERSION_PROFITABLE_P aarch64_noce_conversion_profitable_p\n+\n /* Section anchor support. */\n \n #undef TARGET_MIN_ANCHOR_OFFSET\ndiff --git a/gcc/config/aarch64/tuning_models/generic.h b/gcc/config/aarch64/tuning_models/generic.h\nindex a822c055fe99775c12f121e6186e460dbf90f84f..c5f328a829c3351d5cda92f403ac86efae975251 100644\n--- a/gcc/config/aarch64/tuning_models/generic.h\n+++ b/gcc/config/aarch64/tuning_models/generic.h\n@@ -128,7 +128,8 @@ static const struct cpu_vector_cost generic_vector_cost =\n static const struct cpu_branch_cost generic_branch_cost =\n {\n 1, /* Predictable. */\n- 3 /* Unpredictable. */\n+ 3, /* Unpredictable. */\n+ 7, /* br_mispredict_factor. */\n };\n \n /* Generic approximation modes. */\ndiff --git a/gcc/config/aarch64/tuning_models/generic_armv8_a.h b/gcc/config/aarch64/tuning_models/generic_armv8_a.h\nindex 01080cade464a6fa86d5815649a1190740d6f1fd..0f00d72dddf801635f8a4bf5c1a05e654959ab5d 100644\n--- a/gcc/config/aarch64/tuning_models/generic_armv8_a.h\n+++ b/gcc/config/aarch64/tuning_models/generic_armv8_a.h\n@@ -125,13 +125,6 @@ static const struct cpu_vector_cost generic_armv8_a_vector_cost =\n nullptr /* issue_info */\n };\n \n-/* Generic costs for branch instructions. */\n-static const struct cpu_branch_cost generic_armv8_a_branch_cost =\n-{\n- 1, /* Predictable. */\n- 3 /* Unpredictable. */\n-};\n-\n /* Generic approximation modes. */\n static const cpu_approx_modes generic_armv8_a_approx_modes =\n {\n@@ -158,7 +151,7 @@ static const struct tune_params generic_armv8_a_tunings =\n &generic_armv8_a_addrcost_table,\n &generic_armv8_a_regmove_cost,\n &generic_armv8_a_vector_cost,\n- &generic_armv8_a_branch_cost,\n+ &generic_branch_cost,\n &generic_armv8_a_approx_modes,\n SVE_NOT_IMPLEMENTED, /* sve_width */\n { 4, /* load_int. */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/pr123017_1.c b/gcc/testsuite/gcc.target/aarch64/pr123017_1.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..38e4334c1ea7979a5c535a06e85d027bb4f8a4cc\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/pr123017_1.c\n@@ -0,0 +1,38 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+/* { dg-final { scan-assembler-times \"csel\\t\" 2 } } */\n+\n+#include <stdint.h>\n+#include <stddef.h>\n+\n+// Branchy: compiler can emit a short compare+branch.\n+size_t branchy(size_t cur, size_t dist, size_t fallback, const uint8_t *src, uint8_t *dst, size_t len) {\n+ if (dist < cur && dist < fallback) {\n+ const uint8_t *p = src - dist;\n+ for (size_t i = 0; i < len; ++i)\n+\t dst[i] = p[i];\n+ return dist;\n+ } else {\n+ const uint8_t *p = src - fallback;\n+ for (size_t i = 0; i < len; ++i)\n+\t dst[i] = p[i];\n+ return fallback;\n+ }\n+}\n+\n+// CSEL-heavy: chain ternaries so both paths stay live; compilers emit cmps + csel.\n+size_t selecty(size_t cur, size_t dist, size_t fallback, const uint8_t *src, uint8_t *dst, size_t len) {\n+ // Compute both candidates unconditionally, then pick with ternaries.\n+ size_t candA_off = dist;\n+ size_t candB_off = fallback;\n+ const uint8_t *candA = src - candA_off;\n+ const uint8_t *candB = src - candB_off;\n+\n+ size_t useA = (dist < cur && dist < fallback);\n+ const uint8_t *p = useA ? candA : candB;\n+ size_t chosen = useA ? candA_off : candB_off;\n+\n+ for (size_t i = 0; i < len; ++i)\n+ dst[i] = p[i];\n+ return chosen;\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/pr123017_2.c b/gcc/testsuite/gcc.target/aarch64/pr123017_2.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..72adb418e9e84bd54c2980232a053d88b85ed0b0\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/pr123017_2.c\n@@ -0,0 +1,16 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+/* { dg-final { scan-assembler-times \"csel\\t\" 0 } } */\n+\n+void f(const int *restrict in,\n+ int *restrict out,\n+ int n, int threshold)\n+{\n+ for (int i = 0; i < n; i+=4) {\n+ out[i+0] = in[i+0] > threshold ? in[i+0] : in[i+0] + i;\n+ out[i+1] = in[i+1] > threshold ? in[i+1] : in[i+1] + i;\n+ out[i+2] = in[i+2] > threshold ? in[i+2] : in[i+2] + i;\n+ out[i+3] = in[i+3] > threshold ? in[i+3] : in[i+3] + i;\n+ }\n+}\n+\ndiff --git a/gcc/testsuite/gcc.target/aarch64/pr123017_3.c b/gcc/testsuite/gcc.target/aarch64/pr123017_3.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..ec39d785ee80cdc49db14bbe30d9a6c3668e64dd\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/pr123017_3.c\n@@ -0,0 +1,32 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+/* { dg-final { scan-assembler-times \"csel\\t\" 0 } } */\n+\n+void f(const int *restrict in,\n+ int *restrict out,\n+ int n, int threshold)\n+{\n+ for (int i = 0; i < n; ++i) {\n+ int v = in[i];\n+ if (v > threshold) {\n+ int t = v * 3;\n+ t += 7;\n+ t ^= 0x55;\n+ t *= 0x55;\n+ t -= 0x5;\n+ t &= 0xFE;\n+ t ^= 0x55;\n+ out[i] = t;\n+ } else {\n+ int t = v * 5;\n+ t += 4;\n+ t ^= 0x65;\n+ t *= 0x35;\n+ t -= 0x7;\n+ t &= 0x0E;\n+ t ^= 0x45;\n+ out[i] = t;\n+ }\n+ }\n+}\n+\ndiff --git a/gcc/testsuite/gcc.target/aarch64/pr123017_4.c b/gcc/testsuite/gcc.target/aarch64/pr123017_4.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..b350d492ae46cf79f8107712fafc388554b76654\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/pr123017_4.c\n@@ -0,0 +1,17 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+/* { dg-final { scan-assembler-times \"csel\\t\" 0 } } */\n+\n+void f(const int *restrict in,\n+ int *restrict out,\n+ int n, int threshold)\n+{\n+ for (int i = 0; i < n; ++i) {\n+ int v = in[i];\n+ if (v > threshold) {\n+ int t = v * 3;\n+ out[i] = t;\n+ }\n+ }\n+}\n+\ndiff --git a/gcc/testsuite/gcc.target/aarch64/pr123017_5.c b/gcc/testsuite/gcc.target/aarch64/pr123017_5.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..6d7cd088bd024eeac5821c890cc25d608118dd24\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/pr123017_5.c\n@@ -0,0 +1,20 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+/* { dg-final { scan-assembler-times \"csel\\t\" 1 } } */\n+\n+void f(const int *restrict in,\n+ int *restrict out,\n+ int n, int threshold)\n+{\n+ for (int i = 0; i < n; ++i) {\n+ int v = in[i];\n+ if (v > threshold) {\n+ int t = v * 3;\n+ t += 7;\n+ out[i] = t;\n+ } else {\n+ out[i] = v;\n+ }\n+ }\n+}\n+\ndiff --git a/gcc/testsuite/gcc.target/aarch64/pr123017_6.c b/gcc/testsuite/gcc.target/aarch64/pr123017_6.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..0402c4fdd86d53b2c5ad58792539cef035be115f\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/pr123017_6.c\n@@ -0,0 +1,22 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+/* { dg-final { scan-assembler-times \"csel\\t\" 0 } } */\n+\n+void f(const int *restrict in,\n+ int *restrict out,\n+ int n, int threshold)\n+{\n+ for (int i = 0; i < n; ++i) {\n+ int v = in[i];\n+ if (v > threshold) {\n+ int t = v * 3;\n+ t += 7;\n+ t ^= 0x55;\n+ t *= 0x55;\n+ out[i] = t;\n+ } else {\n+ out[i] = v;\n+ }\n+ }\n+}\n+\ndiff --git a/gcc/testsuite/gcc.target/aarch64/pr123017_7.c b/gcc/testsuite/gcc.target/aarch64/pr123017_7.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..048a69e1c79c11d3b9eddbd3375e05b778da79f4\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/pr123017_7.c\n@@ -0,0 +1,25 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+/* { dg-final { scan-assembler-times \"csel\\t\" 0 } } */\n+\n+void f(const int *restrict in,\n+ int *restrict out,\n+ int n, int threshold)\n+{\n+ for (int i = 0; i < n; ++i) {\n+ int v = in[i];\n+ if (v > threshold) {\n+ int t = v * 3;\n+ t += 7;\n+ t ^= 0x55;\n+ t *= 0x55;\n+ t -= 0x5;\n+ t &= 0xFE;\n+ t ^= 0x55;\n+ out[i] = t;\n+ } else {\n+ out[i] = v;\n+ }\n+ }\n+}\n+\n\n", "prefixes": [] }