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GET /api/patches/2217613/?format=api
{ "id": 2217613, "url": "http://patchwork.ozlabs.org/api/patches/2217613/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260330090714.868443-3-philipp.tomsich@vrull.eu/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330090714.868443-3-philipp.tomsich@vrull.eu>", "list_archive_url": null, "date": "2026-03-30T09:07:14", "name": "[2/2] ext-dce: narrow sign-extending loads to zero-extending when upper bits are dead", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "941a029fdfed584db9ac672ea47ef6d983f6b8a0", "submitter": { "id": 80556, "url": "http://patchwork.ozlabs.org/api/people/80556/?format=api", "name": "Philipp Tomsich", "email": "philipp.tomsich@vrull.eu" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260330090714.868443-3-philipp.tomsich@vrull.eu/mbox/", "series": [ { "id": 497982, "url": "http://patchwork.ozlabs.org/api/series/497982/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=497982", "date": "2026-03-30T09:07:14", "name": "ext-dce: narrow sign-extending loads when upper bits are dead", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497982/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217613/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217613/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=vrull.eu header.i=@vrull.eu header.a=rsa-sha256\n header.s=google header.b=Ro3WGsW5;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=vrull.eu header.i=@vrull.eu header.a=rsa-sha256\n header.s=google header.b=Ro3WGsW5", "sourceware.org;\n dmarc=none (p=none dis=none) header.from=vrull.eu", "sourceware.org; spf=pass smtp.mailfrom=vrull.eu", "server2.sourceware.org;\n arc=none smtp.remote-ip=209.85.167.47" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fkllj33JYz1yG8\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 30 Mar 2026 20:08:17 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 443684BA2E31\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 30 Mar 2026 09:08:15 +0000 (GMT)", "from mail-lf1-f47.google.com (mail-lf1-f47.google.com\n [209.85.167.47])\n by sourceware.org (Postfix) with ESMTPS id 09C604BA2E31\n for <gcc-patches@gcc.gnu.org>; Mon, 30 Mar 2026 09:07:26 +0000 (GMT)", "by mail-lf1-f47.google.com with SMTP id\n 2adb3069b0e04-5a2b0a62ca7so86109e87.2\n for <gcc-patches@gcc.gnu.org>; Mon, 30 Mar 2026 02:07:25 -0700 (PDT)", "from ubuntu-focal.. ([2a01:4f9:3a:1e26::2])\n by smtp.gmail.com with ESMTPSA id\n 2adb3069b0e04-5a2b144e99bsm1552448e87.56.2026.03.30.02.07.22\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 30 Mar 2026 02:07:22 -0700 (PDT)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 443684BA2E31", "OpenDKIM Filter v2.11.0 sourceware.org 09C604BA2E31" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 09C604BA2E31", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 09C604BA2E31", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1774861646; cv=none;\n b=GOLGDBXd/ngvu7QBVFcjHS9HvR9zlivyjKExA80pgpFtZwzWj578AVNUuTA/1I582Bsu/Pc2TikGlvIkTUHA8q9uLo3xuEDEVx/XdLmwpmRdNvNAWxuFJ66x9xm6Xhx8gyyTjPWxVcuVKnyB+9MR2URp31zyaduzKPTW9IhWgjo=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1774861646; c=relaxed/simple;\n bh=5bF+CTfBhoXGF75bRHkOA7Qpt2kbzKzDCG957eRwUU4=;\n h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version;\n b=lym+ApT7K/wdUIDdYfzK6HT/HvM51Kp9CywJbgSu5UEZjL8OWvty1svJku4oq22UNTM5AXt3KKGvyfZQ5VDV2uGwYMlWsvPKRkWz71dZQb6x7FZHq9fzoP5SU1lNq44C8SSDdVafUe5pdBTe+Ypu+bbtzkrtUuIN8pk3MUEJIdY=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=vrull.eu; s=google; t=1774861644; x=1775466444; darn=gcc.gnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=a4bx3EnMyEHxtrL9/u+BfoV/fb1gAPwrD4400gCnR/4=;\n b=Ro3WGsW5Ha89ZVRAKWzsIXU81QZ6oaKtPYnKE9op5mQNgSepRxZW2/mDUpxCrx1e4/\n yfq2iA6jun1S07fEIA1UOZCzYr8jD4Fn7bSVmgTKKx9hQYRihOiQmdCyVl5PVTsf1kyQ\n B5IMMEzMnNOnvtKQ9eku4tjprbDyCq7MDSxEUAt5MviEHjpgpkfJxd4RoShYpElBF+4l\n 2kr3O/+BglytW8DFOP2o/mCGTce3NVMxxhhxAW3kv/gcUHf6iqNEmBtul5VHlNio+7c8\n yrDX23aDfugWpqwaxT1v9lrWLkrO9Ov1WqgMEK1ZmuOPAprvrHA9ZM8A2LTNE9DS5HrL\n u64w==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774861644; x=1775466444;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=a4bx3EnMyEHxtrL9/u+BfoV/fb1gAPwrD4400gCnR/4=;\n b=seLcJB2EmnQCqbZzh7ug8QTf1UDdJlmI5XEZwik+fPZeJaxp1VzRDxijB28CB16RO3\n gjI2T6l7c6HlLP/QPAy6hXM3QLHbpC8G3r3RiDLWMhzVitvzblzlWc0J9poQsCpEkr+V\n TyAGKsqhWWMOmLK3x335YkWMCb4jC7TRjvZW5VzGApIxAuoRb3IFW2stcFBRrTb/BRDn\n 4uINoU/a4MfyhHSxvWutodKp3fTSjdiLGgjlsab1DXDREya/EcjHnsluXf3jmZlfeG9N\n a7aW8Kd2O6UF50lHaiBEQXtqOeGNeMsiliMh/LgRxVAwBbluyegazu2R+Kc+84/ogT7e\n V7vg==", "X-Gm-Message-State": "AOJu0Yw6d1r4LGaSEoN6uqYcWkpGf2vCW1jEpF7lLDgrBDRvLzx+L7+2\n sbZuHQjwZuC3M+aZpcq7ZkLGlugPOQd0jEidoINFpmlLksDkiIX1zoRrcpbWWEnORVW32HSp87O\n relqPFQE=", "X-Gm-Gg": "ATEYQzxJSkC3Rd/+TWg0fWIWIW2ep6vC2K6env6O4g4IXYQq0II/KYhTjNFcpIVz4js\n 9RsCgoeCoV6nYv1vdeX7VV6sosylC/qk7LuqcXG1qPbrOY63nfRSF2V7T4qzN6/0GX7YP7v0OtD\n uwdUqSbqUVRubeodDYa0U2aAF87rXhA7H6GWmSaBY91dT4w7AkBlAMRnLw3zY+9Xtv7T3MX9aba\n iH+n5STM0korS1Oh5XPsf5KXNqHR3YkX0sumfk00G+Of1yasbREzYYGVcFzPZ4mqipfu7XeKObf\n 04aq3F7sx7dQUnw+M4207NQ9w9Cp2h+PYHGJuZnt8YZacp+T06ROLQIo2afZEkI808cVdnHwX2b\n iFLR6fwv5Wl12ljLXp503gb+62QZbMTBzh50Rc6GDXdHwpfnqsLL2F0sZetyZAsb8RpehJSqEZL\n nspj0+Ey9yN6aDnfB7W1akJQVRKsfjTjtcgBPDsGk4RndJA6qpNoff", "X-Received": "by 2002:a05:6512:3501:b0:59e:5796:f6a with SMTP id\n 2adb3069b0e04-5a2ab933298mr2959181e87.7.1774861643021;\n Mon, 30 Mar 2026 02:07:23 -0700 (PDT)", "From": "Philipp Tomsich <philipp.tomsich@vrull.eu>", "To": "gcc-patches@gcc.gnu.org", "Cc": "Philipp Tomsich <philipp.tomsich@vrull.eu>,\n Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>", "Subject": "[PATCH 2/2] ext-dce: narrow sign-extending loads to zero-extending\n when upper bits are dead", "Date": "Mon, 30 Mar 2026 11:07:14 +0200", "Message-Id": "<20260330090714.868443-3-philipp.tomsich@vrull.eu>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260330090714.868443-1-philipp.tomsich@vrull.eu>", "References": "<20260330090714.868443-1-philipp.tomsich@vrull.eu>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "The ext-dce pass tracks bit-level liveness and can replace sign extensions\nwith zero extensions when the upper bits are dead. However,\next_dce_try_optimize_extension bails out when the inner operand is MEM\nrather than REG, missing the opportunity to narrow sign-extending loads\n(e.g. lh -> lhu on RISC-V, ldrsh -> ldrh on AArch64).\n\nAdd handling for SIGN_EXTEND of MEM: when the liveness analysis has\nalready determined the sign bits are dead, replace the sign-extending\nload with a zero-extending load via validate_change, which ensures the\ntarget has a matching instruction pattern.\n\ngcc/ChangeLog:\n\n\t* ext-dce.cc (ext_dce_try_optimize_extension): Handle\n\tSIGN_EXTEND of MEM by replacing with ZERO_EXTEND of MEM\n\twhen upper bits are dead.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/ext-dce-1.c: New test.\n\t* gcc.target/riscv/ext-dce-2.c: New test.\n\t* gcc.target/riscv/ext-dce-3.c: New test.\n\nCo-authored-by: Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>\nSigned-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>\n---\n\n gcc/ext-dce.cc | 46 ++++++++++++++++\n gcc/testsuite/gcc.target/aarch64/ext-dce-1.c | 58 ++++++++++++++++++++\n gcc/testsuite/gcc.target/riscv/ext-dce-2.c | 58 ++++++++++++++++++++\n gcc/testsuite/gcc.target/riscv/ext-dce-3.c | 33 +++++++++++\n 4 files changed, 195 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/ext-dce-1.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/ext-dce-2.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/ext-dce-3.c", "diff": "diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc\nindex caf8a147d976..16a89eb74901 100644\n--- a/gcc/ext-dce.cc\n+++ b/gcc/ext-dce.cc\n@@ -466,6 +466,52 @@ ext_dce_try_optimize_extension (rtx_insn *insn, rtx set)\n rtx src = SET_SRC (set);\n rtx inner = XEXP (src, 0);\n \n+ /* For sign-extending loads from memory, try to replace with a\n+ zero-extending load when the upper bits are dead. E.g. on RISC-V\n+ this turns lh+zext.h into just lhu. */\n+ if (MEM_P (inner) && GET_CODE (src) == SIGN_EXTEND)\n+ {\n+ if (dump_file)\n+\t{\n+\t fprintf (dump_file, \"Processing insn:\\n\");\n+\t dump_insn_slim (dump_file, insn);\n+\t fprintf (dump_file, \"Trying to narrow sign_extend to zero_extend:\\n\");\n+\t print_rtl_single (dump_file, SET_SRC (set));\n+\t}\n+\n+ if (!dbg_cnt (::ext_dce))\n+\t{\n+\t if (dump_file)\n+\t fprintf (dump_file, \"Rejected due to debug counter.\\n\");\n+\t return;\n+\t}\n+\n+ rtx new_pattern = gen_rtx_ZERO_EXTEND (GET_MODE (src), inner);\n+ int ok = validate_change (insn, &SET_SRC (set), new_pattern, false);\n+\n+ rtx x = SET_DEST (set);\n+ while (SUBREG_P (x) || GET_CODE (x) == ZERO_EXTRACT)\n+\tx = XEXP (x, 0);\n+\n+ gcc_assert (REG_P (x));\n+ if (ok)\n+\t{\n+\t bitmap_set_bit (changed_pseudos, REGNO (x));\n+\t remove_reg_equal_equiv_notes (insn, false);\n+\t}\n+\n+ if (dump_file)\n+\t{\n+\t if (ok)\n+\t fprintf (dump_file, \"Successfully transformed to:\\n\");\n+\t else\n+\t fprintf (dump_file, \"Failed transformation to:\\n\");\n+\t print_rtl_single (dump_file, new_pattern);\n+\t fprintf (dump_file, \"\\n\");\n+\t}\n+ return;\n+ }\n+\n /* Avoid (subreg (mem)) and other constructs which may be valid RTL, but\n not useful for this optimization. */\n if (!(REG_P (inner) || (SUBREG_P (inner) && REG_P (SUBREG_REG (inner)))))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/ext-dce-1.c b/gcc/testsuite/gcc.target/aarch64/ext-dce-1.c\nnew file mode 100644\nindex 000000000000..329c101855fb\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/ext-dce-1.c\n@@ -0,0 +1,58 @@\n+/* Verify that ext-dce narrows sign-extending loads to zero-extending loads\n+ when the upper bits are dead. */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" } } */\n+\n+/*\n+** test_half:\n+**\t...\n+**\tldrh\t.*\n+**\t...\n+*/\n+/* Positive: halfword load-modify-store -- sign bits are dead. */\n+void\n+test_half (signed short *p)\n+{\n+ *p = (*p & 0xff00) | (0x00ff & (*p >> 8));\n+}\n+\n+/*\n+** test_byte:\n+**\t...\n+**\tldrb\t.*\n+**\t...\n+*/\n+/* Positive: byte load-modify-store -- sign bits are dead. */\n+void\n+test_byte (signed char *p)\n+{\n+ *p = (*p & 0xf0) | (0x0f & (*p >> 4));\n+}\n+\n+/*\n+** test_half_sign_needed:\n+**\t...\n+**\tldrsb\t.*\n+**\t...\n+*/\n+/* Negative: arithmetic right shift needs the sign extension. */\n+int\n+test_half_sign_needed (signed short *p)\n+{\n+ return *p >> 8;\n+}\n+\n+/*\n+** test_half_compare:\n+**\t...\n+**\tldrsh\t.*\n+**\t...\n+*/\n+/* Negative: sign-dependent comparison. */\n+int\n+test_half_compare (signed short *p)\n+{\n+ return *p < 0;\n+}\n+\ndiff --git a/gcc/testsuite/gcc.target/riscv/ext-dce-2.c b/gcc/testsuite/gcc.target/riscv/ext-dce-2.c\nnew file mode 100644\nindex 000000000000..e5ec9df3e46f\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/ext-dce-2.c\n@@ -0,0 +1,58 @@\n+/* Verify that ext-dce narrows sign-extending loads to zero-extending loads\n+ when the upper bits are dead. */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" } } */\n+\n+/*\n+** test_half:\n+**\t...\n+**\tlhu\t.*\n+**\t...\n+*/\n+/* Positive: halfword load-modify-store -- sign bits are dead. */\n+void\n+test_half (signed short *p)\n+{\n+ *p = (*p & 0xff00) | (0x00ff & (*p >> 8));\n+}\n+\n+/*\n+** test_byte:\n+**\t...\n+**\tlbu\t.*\n+**\t...\n+*/\n+/* Positive: byte load-modify-store -- sign bits are dead. */\n+void\n+test_byte (signed char *p)\n+{\n+ *p = (*p & 0xf0) | (0x0f & (*p >> 4));\n+}\n+\n+/*\n+** test_half_sign_needed:\n+**\t...\n+**\tlh\t.*\n+**\t...\n+*/\n+/* Negative: arithmetic right shift needs the sign extension. */\n+int\n+test_half_sign_needed (signed short *p)\n+{\n+ return *p >> 8;\n+}\n+\n+/*\n+** test_half_compare:\n+**\t...\n+**\tlh\t.*\n+**\t...\n+*/\n+/* Negative: sign-dependent comparison. */\n+int\n+test_half_compare (signed short *p)\n+{\n+ return *p < 0;\n+}\n+\ndiff --git a/gcc/testsuite/gcc.target/riscv/ext-dce-3.c b/gcc/testsuite/gcc.target/riscv/ext-dce-3.c\nnew file mode 100644\nindex 000000000000..45af6eac9704\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/ext-dce-3.c\n@@ -0,0 +1,33 @@\n+/* Verify ext-dce for word loads on RV64: lw sign-extends to 64 bits,\n+ so when the upper 32 bits are dead lw should be narrowed to lwu. */\n+/* { dg-do compile } */\n+/* { dg-require-effective-target rv64 } */\n+/* { dg-options \"-march=rv64gc -mabi=lp64d -O2\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" } } */\n+\n+/*\n+** test_word:\n+**\t...\n+**\tlwu\t.*\n+**\t...\n+*/\n+/* Positive: word load-modify-store -- upper 32 bits are dead. */\n+void\n+test_word (signed int *p)\n+{\n+ *p = (*p & 0xffff0000) | (0x0000ffff & ((unsigned int)*p >> 16));\n+}\n+\n+/*\n+** test_word_sign_needed:\n+**\t...\n+**\tlw\t.*\n+**\t...\n+*/\n+/* Negative: return value is long -- sign extension is needed. */\n+long\n+test_word_sign_needed (signed int *p)\n+{\n+ return *p;\n+}\n+\n", "prefixes": [ "2/2" ] }