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GET /api/patches/2217606/?format=api
{ "id": 2217606, "url": "http://patchwork.ozlabs.org/api/patches/2217606/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260330-t264-pwm-v3-4-5714427d5976@nvidia.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330-t264-pwm-v3-4-5714427d5976@nvidia.com>", "list_archive_url": null, "date": "2026-03-30T08:53:53", "name": "[v3,4/7] pwm: tegra: Parametrize enable register offset", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "9f835a66c4f91a16c46f6baff746abe9ab9d76d0", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260330-t264-pwm-v3-4-5714427d5976@nvidia.com/mbox/", "series": [ { "id": 497978, "url": "http://patchwork.ozlabs.org/api/series/497978/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=497978", "date": "2026-03-30T08:53:54", "name": "Tegra264 PWM support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497978/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217606/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217606/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pwm+bounces-8414-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n 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header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=DD56M22Y17aXtRpKBTowRAmFt2qj3NH7Zvb4xJmEOR0=;\n b=HChM+7M2QuAEmlqIUZZ6u9VN3+CB5djqfUvBKJSIaoLFDQcydrR66qF7nNFnUjwHZlWfkPaotA3Ifx97+2gyAzCD4J2668Vyp0KAtvyVvcBAauk4bCslqbui+o82W0RnPM/scb/wbm9Tw/cxCw1p3zgKiINt4+X4b8CycSJWSvenzSi/M9Mkdge8iA5Ac8VeA2ybSmb5I8QYeuHdIr6Ru3s/sgxbyROH63P2dorb4cbTjqQDeuvnJzOA3vVuaOQqsYffTVWaCgEqB59C3mIVqlLQDg0PkZbaMcAutfc8Z8/4Dkd9RFwxK0twW+I8wEUP4wiYnpYKVr+hsmvEXPgcTA==", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "Date": "Mon, 30 Mar 2026 17:53:53 +0900", "Subject": "[PATCH v3 4/7] pwm: tegra: Parametrize enable register offset", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260330-t264-pwm-v3-4-5714427d5976@nvidia.com>", "References": "<20260330-t264-pwm-v3-0-5714427d5976@nvidia.com>", "In-Reply-To": "<20260330-t264-pwm-v3-0-5714427d5976@nvidia.com>", "To": "Thierry Reding <thierry.reding@gmail.com>, =?utf-8?q?Uwe_Kleine-K=C3=B6n?=\n\t=?utf-8?q?ig?= <ukleinek@kernel.org>,\n Jonathan Hunter <jonathanh@nvidia.com>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n Yi-Wei Wang <yiweiw@nvidia.com>, Mikko Perttunen <mperttunen@nvidia.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": "MW4PR04CA0292.namprd04.prod.outlook.com\n (2603:10b6:303:89::27) To SJ2PR12MB9161.namprd12.prod.outlook.com\n (2603:10b6:a03:566::20)", "Precedence": "bulk", "X-Mailing-List": "linux-pwm@vger.kernel.org", "List-Id": "<linux-pwm.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pwm+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pwm+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", 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"X-MS-Exchange-AntiSpam-MessageData-1": "PZxxsy41c5YmPQ==", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a8b36800-bce5-4961-4e4e-08de8e39e6ea", "X-MS-Exchange-CrossTenant-AuthSource": "SJ2PR12MB9161.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Mar 2026 08:54:07.2616\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n qJNEh2qfYeQgJjq5hetQmmzjJukNeC/Z524LMVMOeQ8VzP5fIIZR3bY/C11RO+Ahk87uTugCuTM+Mbw7Aou4Ug==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH8PR12MB7207" }, "content": "On Tegra264, the PWM enablement bit is not located at the base address\nof the PWM controller. Hence, introduce an enablement offset field in\nthe tegra_pwm_soc structure to describe the offset of the register.\n\nCo-developed-by: Yi-Wei Wang <yiweiw@nvidia.com>\nSigned-off-by: Yi-Wei Wang <yiweiw@nvidia.com>\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\n drivers/pwm/pwm-tegra.c | 17 ++++++++++++-----\n 1 file changed, 12 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c\nindex cf54f75d92a5..22d709986e8c 100644\n--- a/drivers/pwm/pwm-tegra.c\n+++ b/drivers/pwm/pwm-tegra.c\n@@ -61,6 +61,7 @@\n \n struct tegra_pwm_soc {\n \tunsigned int num_channels;\n+\tunsigned int enable_reg;\n };\n \n struct tegra_pwm_chip {\n@@ -197,8 +198,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \t\terr = pm_runtime_resume_and_get(pwmchip_parent(chip));\n \t\tif (err)\n \t\t\treturn err;\n-\t} else\n+\t} else if (pc->soc->enable_reg == PWM_CSR_0) {\n \t\tval |= PWM_ENABLE;\n+\t}\n \n \tpwm_writel(pwm, PWM_CSR_0, val);\n \n@@ -213,6 +215,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \n static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)\n {\n+\tstruct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);\n \tint rc = 0;\n \tu32 val;\n \n@@ -220,20 +223,22 @@ static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)\n \tif (rc)\n \t\treturn rc;\n \n-\tval = pwm_readl(pwm, PWM_CSR_0);\n+\n+\tval = pwm_readl(pwm, pc->soc->enable_reg);\n \tval |= PWM_ENABLE;\n-\tpwm_writel(pwm, PWM_CSR_0, val);\n+\tpwm_writel(pwm, pc->soc->enable_reg, val);\n \n \treturn 0;\n }\n \n static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)\n {\n+\tstruct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);\n \tu32 val;\n \n-\tval = pwm_readl(pwm, PWM_CSR_0);\n+\tval = pwm_readl(pwm, pc->soc->enable_reg);\n \tval &= ~PWM_ENABLE;\n-\tpwm_writel(pwm, PWM_CSR_0, val);\n+\tpwm_writel(pwm, pc->soc->enable_reg, val);\n \n \tpm_runtime_put_sync(pwmchip_parent(chip));\n }\n@@ -398,10 +403,12 @@ static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)\n \n static const struct tegra_pwm_soc tegra20_pwm_soc = {\n \t.num_channels = 4,\n+\t.enable_reg = PWM_CSR_0,\n };\n \n static const struct tegra_pwm_soc tegra186_pwm_soc = {\n \t.num_channels = 1,\n+\t.enable_reg = PWM_CSR_0,\n };\n \n static const struct of_device_id tegra_pwm_of_match[] = {\n", "prefixes": [ "v3", "4/7" ] }