Patch Detail
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Show a patch.
patch:
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Update a patch.
GET /api/patches/2217604/?format=api
{ "id": 2217604, "url": "http://patchwork.ozlabs.org/api/patches/2217604/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260330-t264-pwm-v3-2-5714427d5976@nvidia.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330-t264-pwm-v3-2-5714427d5976@nvidia.com>", "list_archive_url": null, "date": "2026-03-30T08:53:51", "name": "[v3,2/7] pwm: tegra: Avoid hard-coded max clock frequency", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "579bcd179eb413e94911aaa03823622c6c8eebf5", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260330-t264-pwm-v3-2-5714427d5976@nvidia.com/mbox/", "series": [ { "id": 497978, "url": "http://patchwork.ozlabs.org/api/series/497978/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=497978", "date": "2026-03-30T08:53:54", "name": "Tegra264 PWM support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497978/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217604/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217604/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pwm+bounces-8412-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass 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header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=7WzpC8XB3r9UwHrYFPsetBhLf+npXX5syYX0SBE7EY8=;\n b=Fph4WgwChgy89EKf7hKh/Cz3MkEMabZmIYWVIBgmJefLV3tkWMgIV3w0dNcwyHwGUthhzgLzFSsQWF1gVlUSkf5y9kczFVQfZcij8vUdph+IjhY2JGEnraAjd7L//ZFlpc2GQpqRa4Y2/VJ9IV5Z+7QQdpkjRM3UTgCr0sS0KQq3kVGFx3IadwRH6NSpl3tyXtE/VTiKoyJpVjFBk8Gb/jYHVeh8HI0Ndm5zWiWIml49SJACQW0cMk16aN50yRutaahee1tY3Pu1Kcy+mrsheKLqy+QKkIDK/TEihtyVdAJG6nDzXElGqUEaEEwaILjXghmYWlEvJDDbaeQrCD//WQ==", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "Date": "Mon, 30 Mar 2026 17:53:51 +0900", "Subject": "[PATCH v3 2/7] pwm: tegra: Avoid hard-coded max clock frequency", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260330-t264-pwm-v3-2-5714427d5976@nvidia.com>", "References": "<20260330-t264-pwm-v3-0-5714427d5976@nvidia.com>", "In-Reply-To": "<20260330-t264-pwm-v3-0-5714427d5976@nvidia.com>", "To": "Thierry Reding <thierry.reding@gmail.com>, =?utf-8?q?Uwe_Kleine-K=C3=B6n?=\n\t=?utf-8?q?ig?= <ukleinek@kernel.org>,\n Jonathan Hunter <jonathanh@nvidia.com>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n Yi-Wei Wang <yiweiw@nvidia.com>, Thierry Reding <treding@nvidia.com>,\n Mikko Perttunen <mperttunen@nvidia.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": "MW4PR04CA0271.namprd04.prod.outlook.com\n (2603:10b6:303:89::6) To SJ2PR12MB9161.namprd12.prod.outlook.com\n (2603:10b6:a03:566::20)", "Precedence": "bulk", "X-Mailing-List": "linux-pwm@vger.kernel.org", "List-Id": "<linux-pwm.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pwm+subscribe@vger.kernel.org>", "List-Unsubscribe": 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"X-MS-Exchange-AntiSpam-MessageData-1": "SLyjzmae/9vj0A==", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 14ee3e62-0e4c-459a-d033-08de8e39e3ad", "X-MS-Exchange-CrossTenant-AuthSource": "SJ2PR12MB9161.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Mar 2026 08:54:01.8215\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n KyF89udqHufdHc4mE3XlagVxlULXmHgYsjhKZxH9k+GbKcPvB932n2yjQQJPVJaKWPQIJQnI2eX1RAaPu1ySUQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH0PR12MB7839" }, "content": "From: Yi-Wei Wang <yiweiw@nvidia.com>\n\nThe clock driving the Tegra PWM IP can be sourced from different parent\nclocks. Hence, let dev_pm_opp_set_rate() set the max clock rate based\nupon the current parent clock that can be specified via device-tree.\n\nAfter this, the Tegra194 SoC data becomes redundant, so get rid of it.\n\nSigned-off-by: Yi-Wei Wang <yiweiw@nvidia.com>\nReviewed-by: Thierry Reding <treding@nvidia.com>\nCo-developed-by: Mikko Perttunen <mperttunen@nvidia.com>\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\n drivers/pwm/pwm-tegra.c | 16 +++-------------\n 1 file changed, 3 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c\nindex 172063b51d44..759b98b97b6e 100644\n--- a/drivers/pwm/pwm-tegra.c\n+++ b/drivers/pwm/pwm-tegra.c\n@@ -59,9 +59,6 @@\n \n struct tegra_pwm_soc {\n \tunsigned int num_channels;\n-\n-\t/* Maximum IP frequency for given SoCs */\n-\tunsigned long max_frequency;\n };\n \n struct tegra_pwm_chip {\n@@ -303,7 +300,7 @@ static int tegra_pwm_probe(struct platform_device *pdev)\n \t\treturn ret;\n \n \t/* Set maximum frequency of the IP */\n-\tret = dev_pm_opp_set_rate(&pdev->dev, pc->soc->max_frequency);\n+\tret = dev_pm_opp_set_rate(&pdev->dev, S64_MAX);\n \tif (ret < 0) {\n \t\tdev_err(&pdev->dev, \"Failed to set max frequency: %d\\n\", ret);\n \t\tgoto put_pm;\n@@ -318,7 +315,7 @@ static int tegra_pwm_probe(struct platform_device *pdev)\n \n \t/* Set minimum limit of PWM period for the IP */\n \tpc->min_period_ns =\n-\t (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;\n+\t (NSEC_PER_SEC / (pc->clk_rate >> PWM_DUTY_WIDTH)) + 1;\n \n \tpc->rst = devm_reset_control_get_exclusive(&pdev->dev, \"pwm\");\n \tif (IS_ERR(pc->rst)) {\n@@ -397,23 +394,16 @@ static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)\n \n static const struct tegra_pwm_soc tegra20_pwm_soc = {\n \t.num_channels = 4,\n-\t.max_frequency = 48000000UL,\n };\n \n static const struct tegra_pwm_soc tegra186_pwm_soc = {\n \t.num_channels = 1,\n-\t.max_frequency = 102000000UL,\n-};\n-\n-static const struct tegra_pwm_soc tegra194_pwm_soc = {\n-\t.num_channels = 1,\n-\t.max_frequency = 408000000UL,\n };\n \n static const struct of_device_id tegra_pwm_of_match[] = {\n \t{ .compatible = \"nvidia,tegra20-pwm\", .data = &tegra20_pwm_soc },\n \t{ .compatible = \"nvidia,tegra186-pwm\", .data = &tegra186_pwm_soc },\n-\t{ .compatible = \"nvidia,tegra194-pwm\", .data = &tegra194_pwm_soc },\n+\t{ .compatible = \"nvidia,tegra194-pwm\", .data = &tegra186_pwm_soc },\n \t{ }\n };\n MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);\n", "prefixes": [ "v3", "2/7" ] }