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{
    "id": 2217600,
    "url": "http://patchwork.ozlabs.org/api/patches/2217600/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260330-smarc-of-upstream-v1-1-c5b8cab32a22@toradex.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
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    "msgid": "<20260330-smarc-of-upstream-v1-1-c5b8cab32a22@toradex.com>",
    "list_archive_url": null,
    "date": "2026-03-30T07:59:41",
    "name": "[1/2] arm: dts: imx95-toradex-smarc: migrate to OF_UPSTREAM",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "c9ed3c6e51c0a04e1ada8ecf0003599e60779508",
    "submitter": {
        "id": 92056,
        "url": "http://patchwork.ozlabs.org/api/people/92056/?format=api",
        "name": "Franz Schnyder",
        "email": "fra.schnyder@gmail.com"
    },
    "delegate": {
        "id": 151988,
        "url": "http://patchwork.ozlabs.org/api/users/151988/?format=api",
        "username": "festevam",
        "first_name": "Fabio",
        "last_name": "Estevam",
        "email": "festevam@gmail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260330-smarc-of-upstream-v1-1-c5b8cab32a22@toradex.com/mbox/",
    "series": [
        {
            "id": 497979,
            "url": "http://patchwork.ozlabs.org/api/series/497979/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497979",
            "date": "2026-03-30T07:59:40",
            "name": "imx95-toradex-smarc: Migrate to OF_UPSTREAM and enable GPIO_HOG",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/497979/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2217600/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2217600/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Franz Schnyder <fra.schnyder@gmail.com>",
        "Date": "Mon, 30 Mar 2026 09:59:41 +0200",
        "Subject": "[PATCH 1/2] arm: dts: imx95-toradex-smarc: migrate to OF_UPSTREAM",
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        "Message-Id": "<20260330-smarc-of-upstream-v1-1-c5b8cab32a22@toradex.com>",
        "References": "<20260330-smarc-of-upstream-v1-0-c5b8cab32a22@toradex.com>",
        "In-Reply-To": "<20260330-smarc-of-upstream-v1-0-c5b8cab32a22@toradex.com>",
        "To": "u-boot@lists.denx.de",
        "Cc": "Francesco Dolcini <francesco.dolcini@toradex.com>,\n Fabio Estevam <festevam@gmail.com>,\n Franz Schnyder <franz.schnyder@toradex.com>",
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    "content": "From: Franz Schnyder <franz.schnyder@toradex.com>\n\nAllow CONFIG_OF_UPSTREAM to receive automatic device tree updates for\nthe Toradex SMARC iMX95.\n\nRemove the now obsolete device tree files:\n- imx95-toradex-smarc-dev.dts\n- imx95-toradex-smarc.dtsi\n\nSigned-off-by: Franz Schnyder <franz.schnyder@toradex.com>\n---\n arch/arm/dts/imx95-toradex-smarc-dev.dts |  277 -------\n arch/arm/dts/imx95-toradex-smarc.dtsi    | 1153 ------------------------------\n arch/arm/mach-imx/imx9/Kconfig           |    1 +\n board/toradex/smarc-imx95/MAINTAINERS    |    2 -\n configs/toradex-smarc-imx95_defconfig    |    2 +-\n 5 files changed, 2 insertions(+), 1433 deletions(-)",
    "diff": "diff --git a/arch/arm/dts/imx95-toradex-smarc-dev.dts b/arch/arm/dts/imx95-toradex-smarc-dev.dts\ndeleted file mode 100644\nindex 5b05f256fd5..00000000000\n--- a/arch/arm/dts/imx95-toradex-smarc-dev.dts\n+++ /dev/null\n@@ -1,277 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n-/*\n- * Copyright (C) 2025 Toradex\n- *\n- * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95\n- * https://www.toradex.com/products/carrier-board/smarc-development-board-kit\n- */\n-\n-/dts-v1/;\n-\n-#include <dt-bindings/pwm/pwm.h>\n-#include \"imx95-toradex-smarc.dtsi\"\n-\n-/ {\n-\tmodel = \"Toradex SMARC iMX95 on Toradex SMARC Development Board\";\n-\tcompatible = \"toradex,smarc-imx95-dev\",\n-\t\t     \"toradex,smarc-imx95\",\n-\t\t     \"fsl,imx95\";\n-\n-\treg_carrier_1p8v: regulator-carrier-1p8v {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-max-microvolt = <1800000>;\n-\t\tregulator-min-microvolt = <1800000>;\n-\t\tregulator-name = \"On-carrier 1V8\";\n-\t};\n-\n-\tsound {\n-\t\tcompatible = \"simple-audio-card\";\n-\t\tsimple-audio-card,bitclock-master = <&codec_dai>;\n-\t\tsimple-audio-card,format = \"i2s\";\n-\t\tsimple-audio-card,frame-master = <&codec_dai>;\n-\t\tsimple-audio-card,mclk-fs = <256>;\n-\t\tsimple-audio-card,name = \"tdx-smarc-wm8904\";\n-\t\tsimple-audio-card,routing =\n-\t\t\t\"Headphone Jack\", \"HPOUTL\",\n-\t\t\t\"Headphone Jack\", \"HPOUTR\",\n-\t\t\t\"IN2L\", \"Line In Jack\",\n-\t\t\t\"IN2R\", \"Line In Jack\",\n-\t\t\t\"Microphone Jack\", \"MICBIAS\",\n-\t\t\t\"IN1L\", \"Microphone Jack\";\n-\t\tsimple-audio-card,widgets =\n-\t\t\t\"Microphone\", \"Microphone Jack\",\n-\t\t\t\"Headphone\", \"Headphone Jack\",\n-\t\t\t\"Line\", \"Line In Jack\";\n-\n-\t\tcodec_dai: simple-audio-card,codec {\n-\t\t\tclocks = <&scmi_clk IMX95_CLK_SAI3>;\n-\t\t\tsound-dai = <&wm8904_1a>;\n-\t\t};\n-\n-\t\tsimple-audio-card,cpu {\n-\t\t\tsound-dai = <&sai3>;\n-\t\t};\n-\t};\n-};\n-\n-/* SMARC GBE0 */\n-&enetc_port0 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC GBE1 */\n-&enetc_port1 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC CAN0 */\n-&flexcan1 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC CAN1 */\n-&flexcan2 {\n-\tstatus = \"okay\";\n-};\n-\n-&gpio2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_gpio12>, <&pinctrl_gpio13>;\n-};\n-\n-&gpio4 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_gpio10>, <&pinctrl_gpio11>;\n-};\n-\n-&gpio5 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_gpio2>,\n-\t\t    <&pinctrl_gpio3>,\n-\t\t    <&pinctrl_gpio4>,\n-\t\t    <&pinctrl_gpio6>,\n-\t\t    <&pinctrl_gpio8>,\n-\t\t    <&pinctrl_gpio9>;\n-};\n-\n-/* SMARC I2C_CAM0 */\n-&i2c_cam0 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC I2C_CAM1 */\n-&i2c_cam1 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC I2C_GP */\n-&lpi2c2 {\n-\tstatus = \"okay\";\n-\n-\twm8904_1a: audio-codec@1a {\n-\t\tcompatible = \"wlf,wm8904\";\n-\t\treg = <0x1a>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_sai3>, <&pinctrl_sai3_mclk>;\n-\t\t#sound-dai-cells = <0>;\n-\t\tclocks = <&scmi_clk IMX95_CLK_SAI3>;\n-\t\tclock-names = \"mclk\";\n-\t\tAVDD-supply = <&reg_carrier_1p8v>;\n-\t\tCPVDD-supply = <&reg_carrier_1p8v>;\n-\t\tDBVDD-supply = <&reg_carrier_1p8v>;\n-\t\tDCVDD-supply = <&reg_carrier_1p8v>;\n-\t\tMICVDD-supply = <&reg_carrier_1p8v>;\n-\t};\n-\n-\ttemperature-sensor@4f {\n-\t\tcompatible = \"ti,tmp1075\";\n-\t\treg = <0x4f>;\n-\t};\n-\n-\teeprom@57 {\n-\t\tcompatible = \"st,24c02\", \"atmel,24c02\";\n-\t\treg = <0x57>;\n-\t\tpagesize = <16>;\n-\t};\n-\n-};\n-\n-/* SMARC I2C_PM */\n-&lpi2c3 {\n-\tclock-frequency = <100000>;\n-\tstatus = \"okay\";\n-\n-\tfan_controller: fan@18 {\n-\t\tcompatible = \"ti,amc6821\";\n-\t\treg = <0x18>;\n-\t\t#pwm-cells = <2>;\n-\n-\t\tfan {\n-\t\t\tcooling-levels = <255>;\n-\t\t\tpwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;\n-\t\t};\n-\t};\n-\n-\t/* Current measurement into module VCC */\n-\thwmon@40 {\n-\t\tcompatible = \"ti,ina226\";\n-\t\treg = <0x40>;\n-\t\tshunt-resistor = <5000>;\n-\t};\n-};\n-\n-/* SMARC I2C_LCD */\n-&lpi2c5 {\n-\tstatus = \"okay\";\n-\n-\ti2c-mux@70 {\n-\t\tcompatible = \"nxp,pca9543\";\n-\t\treg = <0x70>;\n-\t\ti2c-mux-idle-disconnect;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\t/* I2C on DSI Connector Pins 4/6 */\n-\t\ti2c_dsi_0: i2c@0 {\n-\t\t\treg = <0>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t};\n-\n-\t\t/* I2C on DSI Connector Pins 52/54 */\n-\t\ti2c_dsi_1: i2c@1 {\n-\t\t\treg = <1>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t};\n-\t};\n-};\n-\n-/* SMARC SPI0 */\n-&lpspi6 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC SER1, used as the Linux Console */\n-&lpuart1 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC SER0, RS485 */\n-&lpuart2 {\n-\tlinux,rs485-enabled-at-boot-time;\n-\trs485-rts-active-low;\n-\trs485-rx-during-tx;\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC SER3, RS232 */\n-&lpuart3 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC MDIO, shared between all ethernet ports */\n-&netc_emdio {\n-\tstatus = \"okay\";\n-\n-\tethphy3: ethernet-phy@4 {\n-\t\treg = <4>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_gpio7>;\n-\t\tinterrupt-parent = <&gpio5>;\n-\t\tinterrupts = <9 IRQ_TYPE_LEVEL_LOW>;\n-\t};\n-};\n-\n-/* SMARC PCIE_A / M2 Key B */\n-&pcie0 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC PCIE_B /  M2 Key E */\n-&pcie1 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC I2S0 */\n-&sai3 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC LCD0_BKLT_PWM */\n-&tpm3 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC LCD1_BKLT_PWM */\n-&tpm4 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC GPIO5 as PWM */\n-&tpm5 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC USB0 */\n-&usb2 {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC USB1..4 */\n-&usb3 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_dwc3 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb3_phy {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC SDIO */\n-&usdhc2 {\n-\tstatus = \"okay\";\n-};\ndiff --git a/arch/arm/dts/imx95-toradex-smarc.dtsi b/arch/arm/dts/imx95-toradex-smarc.dtsi\ndeleted file mode 100644\nindex e99f1a57af8..00000000000\n--- a/arch/arm/dts/imx95-toradex-smarc.dtsi\n+++ /dev/null\n@@ -1,1153 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n-/*\n- * Copyright (C) 2025 Toradex\n- *\n- * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95\n- */\n-\n-#include <dt-bindings/input/input.h>\n-#include <dt-bindings/net/ti-dp83867.h>\n-#include \"imx95.dtsi\"\n-\n-/ {\n-\taliases {\n-\t\tcan0 = &flexcan1;\n-\t\tcan1 = &flexcan2;\n-\t\tethernet0 = &enetc_port0;\n-\t\tethernet1 = &enetc_port1;\n-\t\tmmc0 = &usdhc1;\n-\t\tmmc1 = &usdhc2;\n-\t\tmmc2 = &usdhc3;\n-\t\trtc0 = &rtc_i2c;\n-\t\trtc1 = &scmi_bbm;\n-\t\tserial0 = &lpuart2;\n-\t\tserial1 = &lpuart1;\n-\t\tserial3 = &lpuart3;\n-\t};\n-\n-\tchosen {\n-\t\tstdout-path = \"serial1:115200n8\";\n-\t};\n-\n-\tclk_dsi2dp_bridge: clock-dsi2dp-bridge {\n-\t\tcompatible = \"fixed-clock\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <27000000>;\n-\t};\n-\n-\tclk_serdes_eth_ref: clock-eth-ref {\n-\t\tcompatible = \"gpio-gate-clock\";\n-\t\t#clock-cells = <0>;\n-\t\t/* CTRL_ETH_REF_CLK_STBY# */\n-\t\tenable-gpios = <&som_gpio_expander_1 13 GPIO_ACTIVE_HIGH>;\n-\t};\n-\n-\tconnector {\n-\t\tcompatible = \"gpio-usb-b-connector\", \"usb-b-connector\";\n-\t\t/* SMARC P64 - USB0_OTG_ID */\n-\t\tid-gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>;\n-\t\tlabel = \"USB0\";\n-\t\tself-powered;\n-\t\ttype = \"micro\";\n-\t\tvbus-supply = <&reg_usb0_vbus>;\n-\n-\t\tport {\n-\t\t\tusb_dr_connector: endpoint {\n-\t\t\t\tremote-endpoint = <&usb0_otg_id>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tgpio-keys {\n-\t\tcompatible = \"gpio-keys\";\n-\n-\t\tsmarc_key_sleep: key-sleep {\n-\t\t\tgpios = <&som_ec_gpio_expander 4 GPIO_ACTIVE_LOW>;\n-\t\t\tlabel = \"SMARC_SLEEP#\";\n-\t\t\twakeup-source;\n-\t\t\tlinux,code = <KEY_SLEEP>;\n-\t\t};\n-\n-\t\tsmarc_switch_lid: switch-lid {\n-\t\t\tgpios = <&som_ec_gpio_expander 2 GPIO_ACTIVE_LOW>;\n-\t\t\tlabel = \"SMARC_LID#\";\n-\t\t\tlinux,code = <SW_LID>;\n-\t\t\tlinux,input-type = <EV_SW>;\n-\t\t};\n-\t};\n-\n-\treg_module_1p8v: regulator-module-1p8v {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-max-microvolt = <1800000>;\n-\t\tregulator-min-microvolt = <1800000>;\n-\t\tregulator-name = \"On-module +V1.8\";\n-\t};\n-\n-\t/* Non PMIC On-module Supplies */\n-\treg_module_dp_1p2v: regulator-module-dp-1p2v {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-max-microvolt = <1200000>;\n-\t\tregulator-min-microvolt = <1200000>;\n-\t\tregulator-name = \"On-module +V1.2_DP\";\n-\t\tvin-supply = <&reg_module_1p8v>;\n-\t};\n-\n-\treg_usb0_vbus: regulator-usb0-vbus {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\t/* SMARC P62 - USB0_EN_OC# */\n-\t\tgpios = <&som_gpio_expander_0 4 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t\tregulator-name = \"USB0_EN_OC#\";\n-\t};\n-\n-\treg_usb1_vbus: regulator-usb1-vbus {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\t/* CTRL_V_BUS_USB_HUB or SMARC P71 - USB2_EN_OC# */\n-\t\tgpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t\tregulator-name = \"CTRL_V_BUS_USB_HUB\";\n-\t};\n-\n-\treg_usdhc2_vmmc: regulator-vmmc-usdhc2 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_usdhc2_pwr_en>;\n-\t\tenable-active-high;\n-\t\tgpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;\n-\t\toff-on-delay-us = <100000>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-name = \"SDIO_PWR_EN\";\n-\t\tstartup-delay-us = <20000>;\n-\t};\n-\n-\treg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {\n-\t\tcompatible = \"regulator-gpio\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_usdhc2_vsel>;\n-\t\tgpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-min-microvolt = <1800000>;\n-\t\tstates = <1800000 0x1>,\n-\t\t\t <3300000 0x0>;\n-\t\tregulator-name = \"PMIC_SD2_VSEL\";\n-\t};\n-\n-\treg_wifi_en: regulator-wifi-en {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\t/* CTRL_EN_WIFI */\n-\t\tgpios = <&som_gpio_expander_1 7 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-name = \"CTRL_EN_WIFI\";\n-\t\tstartup-delay-us = <2000>;\n-\t};\n-\n-\treserved-memory {\n-\t\t#address-cells = <2>;\n-\t\t#size-cells = <2>;\n-\t\tranges;\n-\n-\t\tlinux_cma: linux,cma {\n-\t\t\tcompatible = \"shared-dma-pool\";\n-\t\t\treusable;\n-\t\t\tsize = <0 0x3c000000>;\n-\t\t\talloc-ranges = <0 0x80000000 0 0x7F000000>;\n-\t\t\tlinux,cma-default;\n-\t\t};\n-\t};\n-};\n-\n-/* SMARC GBE0 */\n-&enetc_port0 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_enetc0>, <&pinctrl_enetc0_1588_tmr>;\n-\tphy-handle = <&ethphy1>;\n-\tphy-mode = \"rgmii-id\";\n-};\n-\n-/* SMARC GBE1 */\n-&enetc_port1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_enetc1>, <&pinctrl_enetc1_1588_tmr>;\n-\tphy-handle = <&ethphy2>;\n-\tphy-mode = \"rgmii-id\";\n-};\n-\n-/* SMARC CAN0 */\n-&flexcan1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_flexcan1>;\n-};\n-\n-/* SMARC CAN1 */\n-&flexcan2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_flexcan2>;\n-};\n-\n-&gpio1 {\n-\tgpio-line-names = \"\", /* 0 */\n-\t\t\t  \"\",\n-\t\t\t  \"SMARC_I2C_GP_CK\",\n-\t\t\t  \"SMARC_I2C_GP_DAT\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\", /* 10 */\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"CTRL_IO_EXP_INT_B\";\n-\tstatus = \"okay\";\n-};\n-\n-&gpio2 {\n-\tgpio-line-names = \"SMARC_SPI0_CS0#\", /* 0 */\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"SMARC_GPIO5\",\n-\t\t\t  \"\",\n-\t\t\t  \"I2C_CAM_DAT\",\n-\t\t\t  \"I2C_CAM_CK\",\n-\t\t\t  \"SMARC_GPIO12\", /* 10 */\n-\t\t\t  \"SMARC_GPIO13\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"SMARC_SPI1_CS0#\",\n-\t\t\t  \"\",\n-\t\t\t  \"\", /* 20 */\n-\t\t\t  \"\",\n-\t\t\t  \"SMARC_I2C_LCD_DAT\",\n-\t\t\t  \"SMARC_I2C_LCD_CK\",\n-\t\t\t  \"SMARC_SPI0_CS1#\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"SMARC_I2C_PM_DAT\",\n-\t\t\t  \"SMARC_I2C_PM_CK\",\n-\t\t\t  \"I2C_SOM_DAT\", /* 30 */\n-\t\t\t  \"I2C_SOM_CK\";\n-\tstatus = \"okay\";\n-};\n-\n-&gpio3 {\n-\tgpio-line-names = \"SMARC_SDIO_CD#\", /* 0 */\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"SMARC_SDIO_PWR_EN\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\", /* 10 */\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"PMIC_SD2_VSEL\";\n-\tstatus = \"okay\";\n-};\n-\n-&gpio4 {\n-\tgpio-line-names = \"\", /* 0 */\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\", /* 10 */\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"SMARC_GPIO11\",\n-\t\t\t  \"SMARC_GPIO10\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\", /* 20 */\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"SMARC_SMB_ALERT#\";\n-\tstatus = \"okay\";\n-};\n-\n-&gpio5 {\n-\tgpio-line-names = \"SMARC_GPIO2\", /* 0 */\n-\t\t\t  \"SMARC_GPIO3\",\n-\t\t\t  \"SMARC_GPIO4\",\n-\t\t\t  \"SMARC_GPIO6\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"\",\n-\t\t\t  \"SMARC_GPIO9\",\n-\t\t\t  \"SMARC_GPIO7\",\n-\t\t\t  \"SMARC_GPIO8\", /* 10 */\n-\t\t\t  \"SMARC_SPI1_CS1#\",\n-\t\t\t  \"\",\n-\t\t\t  \"SPI1_TPM_CS#\";\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC I2C_GP */\n-&lpi2c2 {\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_lpi2c2>;\n-\tpinctrl-1 = <&pinctrl_lpi2c2_gpio>;\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\tclock-frequency = <400000>;\n-\tscl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-\n-\teeprom@50 {\n-\t\tcompatible = \"st,24c32\", \"atmel,24c32\";\n-\t\treg = <0x50>;\n-\t\tpagesize = <32>;\n-\t};\n-};\n-\n-/* SMARC I2C_PM */\n-&lpi2c3 {\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_lpi2c3>;\n-\tpinctrl-1 = <&pinctrl_lpi2c3_gpio>;\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\tclock-frequency = <400000>;\n-\tscl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-};\n-\n-/* I2C_SOM */\n-&lpi2c4 {\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_lpi2c4>, <&pinctrl_ctrl_io_exp_int_b>;\n-\tpinctrl-1 = <&pinctrl_lpi2c4_gpio>, <&pinctrl_ctrl_io_exp_int_b>;\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\tclock-frequency = <400000>;\n-\tscl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-\n-\tsom_gpio_expander_0: gpio@20 {\n-\t\tcompatible = \"nxp,pcal6408\";\n-\t\treg = <0x20>;\n-\t\t#interrupt-cells = <2>;\n-\t\tinterrupt-controller;\n-\t\tinterrupt-parent = <&gpio1>;\n-\t\tinterrupts = <14 IRQ_TYPE_LEVEL_LOW>;\n-\t\t#gpio-cells = <2>;\n-\t\tgpio-controller;\n-\t\tgpio-line-names =\n-\t\t\t\"SMARC_PCIE_WAKE#\", /* 0 */\n-\t\t\t\"SMARC_PCIE_B_RST#\",\n-\t\t\t\"SMARC_PCIE_A_RST#\",\n-\t\t\t\"SMARC_USB0_OTG_ID\",\n-\t\t\t\"SMARC_USB0_EN\", /* SMARC USB0_EN_OC# - Open Drain Output */\n-\t\t\t\"SMARC_USB0_OC#\", /* SMARC USB0_EN_OC# - Over-Current Sense Input */\n-\t\t\t\"\",\n-\t\t\t\"SMARC_PCIE_C_RST#\";\n-\t};\n-\n-\tsom_gpio_expander_1: gpio@21 {\n-\t\tcompatible = \"nxp,pcal6416\";\n-\t\treg = <0x21>;\n-\t\t#interrupt-cells = <2>;\n-\t\tinterrupt-controller;\n-\t\tinterrupt-parent = <&gpio1>;\n-\t\tinterrupts = <14 IRQ_TYPE_LEVEL_LOW>;\n-\t\t#gpio-cells = <2>;\n-\t\tgpio-controller;\n-\t\tgpio-line-names =\n-\t\t\t\"SMARC_GPIO0\", /* 0 */\n-\t\t\t\"SMARC_GPIO1\",\n-\t\t\t\"SMARC_LCD0_VDD_EN\",\n-\t\t\t\"SMARC_LCD0_BKLT_EN\",\n-\t\t\t\"SMARC_LCD1_VDD_EN\",\n-\t\t\t\"SMARC_LCD1_BKLT_EN\",\n-\t\t\t\"\",\n-\t\t\t\"\",\n-\t\t\t\"\",\n-\t\t\t\"\",\n-\t\t\t\"\", /* 10 */\n-\t\t\t\"\",\n-\t\t\t\"\",\n-\t\t\t\"\",\n-\t\t\t\"\",\n-\t\t\t\"\",\n-\t\t\t\"\",\n-\t\t\t\"SMARC_SDIO_WP\";\n-\t};\n-\n-\tembedded-controller@28 {\n-\t\tcompatible = \"toradex,smarc-imx95-ec\", \"toradex,smarc-ec\";\n-\t\treg = <0x28>;\n-\t};\n-\n-\tsom_ec_gpio_expander: gpio@29 {\n-\t\tcompatible = \"toradex,ecgpiol16\", \"nxp,pcal6416\";\n-\t\treg = <0x29>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_ec_int>;\n-\t\t#interrupt-cells = <2>;\n-\t\tinterrupt-controller;\n-\t\tinterrupt-parent = <&gpio1>;\n-\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n-\t\t#gpio-cells = <2>;\n-\t\tgpio-controller;\n-\t\tgpio-line-names =\n-\t\t\t\"SMARC_CHARGER_PRSNT#\",\n-\t\t\t\"SMARC_CHARGING#\",\n-\t\t\t\"SMARC_LID#\",\n-\t\t\t\"SMARC_BATLOW#\",\n-\t\t\t\"SMARC_SLEEP#\";\n-\t};\n-\n-\t/* SMARC DP0 */\n-\tsom_dsi2dp_bridge: bridge@2c {\n-\t\tcompatible = \"ti,sn65dsi86\";\n-\t\treg = <0x2c>;\n-\t\tclocks = <&clk_dsi2dp_bridge>;\n-\t\tclock-names = \"refclk\";\n-\t\tvcc-supply = <&reg_module_dp_1p2v>;\n-\t\tvcca-supply = <&reg_module_dp_1p2v>;\n-\t\tvccio-supply = <&reg_module_1p8v>;\n-\t\tvpll-supply = <&reg_module_1p8v>;\n-\t\tstatus = \"disabled\";\n-\n-\t\tports {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tport@0 {\n-\t\t\t\treg = <0>;\n-\t\t\t\tsn65dsi86_in: endpoint {\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tport@1 {\n-\t\t\t\treg = <1>;\n-\t\t\t\tsn65dsi86_out: endpoint {\n-\t\t\t\t\tdata-lanes = <3 2 1 0>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\trtc_i2c: rtc@32 {\n-\t\tcompatible = \"epson,rx8130\";\n-\t\treg = <0x32>;\n-\t};\n-\n-\ttemperature-sensor@48 {\n-\t\tcompatible = \"ti,tmp1075\";\n-\t\treg = <0x48>;\n-\t};\n-\n-\teeprom@50 {\n-\t\tcompatible = \"st,24c02\", \"atmel,24c02\";\n-\t\treg = <0x50>;\n-\t\tpagesize = <16>;\n-\t};\n-};\n-\n-/* SMARC I2C_LCD */\n-&lpi2c5 {\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_lpi2c5>;\n-\tpinctrl-1 = <&pinctrl_lpi2c5_gpio>;\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\tclock-frequency = <100000>;\n-\tscl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-};\n-\n-/* I2C_CAM */\n-&lpi2c7 {\n-\tpinctrl-names = \"default\", \"gpio\";\n-\tpinctrl-0 = <&pinctrl_lpi2c7>;\n-\tpinctrl-1 = <&pinctrl_lpi2c7_gpio>;\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\tclock-frequency = <400000>;\n-\tscl-gpios = <&gpio2 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tsda-gpios = <&gpio2 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n-\tstatus = \"okay\";\n-\n-\ti2c-mux@70 {\n-\t\tcompatible = \"nxp,pca9543\";\n-\t\treg = <0x70>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\t/* SMARC I2C_CAM0 */\n-\t\ti2c_cam0: i2c@0 {\n-\t\t\treg = <0>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t};\n-\n-\t\t/* SMARC I2C_CAM1 */\n-\t\ti2c_cam1: i2c@1 {\n-\t\t\treg = <1>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t};\n-\t};\n-};\n-\n-/* SMARC SPI1 */\n-&lpspi4 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_lpspi4>;\n-\tcs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>,\n-\t\t   <&gpio5 11 GPIO_ACTIVE_LOW>,\n-\t\t   <&gpio5 13 GPIO_ACTIVE_LOW>;\n-\tstatus = \"okay\";\n-\n-\tsom_tpm: tpm@2 {\n-\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n-\t\treg = <0x2>;\n-\t\tspi-max-frequency = <18500000>;\n-\t};\n-};\n-\n-/* SMARC SPI0 */\n-&lpspi6 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_lpspi6>;\n-\tcs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>,\n-\t\t   <&gpio2 24 GPIO_ACTIVE_LOW>;\n-};\n-\n-/* SMARC SER1, used as the Linux Console */\n-&lpuart1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart1>;\n-};\n-\n-/* SMARC SER0 */\n-&lpuart2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart2>;\n-\tuart-has-rtscts;\n-};\n-\n-/* SMARC SER3 */\n-&lpuart3 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart3>;\n-};\n-\n-/* SMARC MDIO, shared between all ethernet ports */\n-&netc_emdio {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_emdio>;\n-\n-\tethphy1: ethernet-phy@1 {\n-\t\treg = <1>;\n-\t\tinterrupt-parent = <&som_gpio_expander_1>;\n-\t\tinterrupts = <6 IRQ_TYPE_LEVEL_LOW>;\n-\t\tti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;\n-\t\tti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;\n-\t};\n-\n-\tethphy2: ethernet-phy@2 {\n-\t\treg = <2>;\n-\t\tti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;\n-\t\tti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;\n-\t};\n-};\n-\n-&netcmix_blk_ctrl {\n-\tstatus = \"okay\";\n-};\n-\n-&netc_blk_ctrl {\n-\tstatus = \"okay\";\n-};\n-\n-&netc_timer {\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC PCIE_A */\n-&pcie0 {\n-\tpinctrl-0 = <&pinctrl_pcie0>;\n-\tpinctrl-names = \"default\";\n-\treset-gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_LOW>;\n-};\n-\n-/* SMARC PCIE_B */\n-&pcie1 {\n-\tpinctrl-0 = <&pinctrl_pcie1>;\n-\tpinctrl-names = \"default\";\n-\treset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>;\n-};\n-\n-/* SMARC I2S0 */\n-&sai3 {\n-\t#sound-dai-cells = <0>;\n-\tassigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,\n-\t\t\t  <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,\n-\t\t\t  <&scmi_clk IMX95_CLK_AUDIOPLL1>,\n-\t\t\t  <&scmi_clk IMX95_CLK_AUDIOPLL2>,\n-\t\t\t  <&scmi_clk IMX95_CLK_SAI3>;\n-\tassigned-clock-parents = <0>, <0>, <0>, <0>,\n-\t\t\t\t <&scmi_clk IMX95_CLK_AUDIOPLL1>;\n-\tassigned-clock-rates = <3932160000>,\n-\t\t\t       <3612672000>, <393216000>,\n-\t\t\t       <361267200>, <12288000>;\n-\tfsl,sai-mclk-direction-output;\n-};\n-\n-&thermal_zones {\n-\t/* PF09 Main PMIC */\n-\tpf09-thermal {\n-\t\tpolling-delay = <2000>;\n-\t\tpolling-delay-passive = <250>;\n-\t\tthermal-sensors = <&scmi_sensor 2>;\n-\n-\t\ttrips {\n-\t\t\ttrip0 {\n-\t\t\t\thysteresis = <2000>;\n-\t\t\t\ttemperature = <155000>;\n-\t\t\t\ttype = \"critical\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\t/* PF53 VDD_ARM PMIC */\n-\tpf53-arm-thermal {\n-\t\tpolling-delay = <2000>;\n-\t\tpolling-delay-passive = <250>;\n-\t\tthermal-sensors = <&scmi_sensor 4>;\n-\n-\t\ttrips {\n-\t\t\ttrip0 {\n-\t\t\t\thysteresis = <2000>;\n-\t\t\t\ttemperature = <155000>;\n-\t\t\t\ttype = \"critical\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\t/* PF53 VDD_SOC PMIC */\n-\tpf53-soc-thermal {\n-\t\tpolling-delay = <2000>;\n-\t\tpolling-delay-passive = <250>;\n-\t\tthermal-sensors = <&scmi_sensor 3>;\n-\n-\t\ttrips {\n-\t\t\ttrip0 {\n-\t\t\t\thysteresis = <2000>;\n-\t\t\t\ttemperature = <155000>;\n-\t\t\t\ttype = \"critical\";\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-/* SMARC LCD0_BKLT_PWM */\n-&tpm3 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_lcd0_bklt_pwm>;\n-};\n-\n-/* SMARC LCD1_BKLT_PWM */\n-&tpm4 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_lcd1_bklt_pwm>;\n-};\n-\n-/* SMARC GPIO5 as PWM */\n-&tpm5 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_gpio5_pwm>;\n-};\n-\n-/* SMARC USB0 */\n-&usb2 {\n-\tadp-disable;\n-\tdr_mode = \"otg\";\n-\thnp-disable;\n-\tsrp-disable;\n-\tusb-role-switch;\n-\tvbus-supply = <&reg_usb0_vbus>;\n-\n-\tport {\n-\t\tusb0_otg_id: endpoint {\n-\t\t\tremote-endpoint = <&usb_dr_connector>;\n-\t\t};\n-\t};\n-};\n-\n-&usb3 {\n-\tfsl,disable-port-power-control;\n-};\n-\n-/* SMARC USB1..4  */\n-&usb3_dwc3 {\n-\tdr_mode = \"host\";\n-};\n-\n-&usb3_phy {\n-\tvbus-supply = <&reg_usb1_vbus>;\n-};\n-\n-/* On-module eMMC */\n-&usdhc1 {\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc1>;\n-\tpinctrl-1 = <&pinctrl_usdhc1>;\n-\tpinctrl-2 = <&pinctrl_usdhc1_200mhz>;\n-\tbus-width = <8>;\n-\tnon-removable;\n-\tno-sdio;\n-\tno-sd;\n-\tstatus = \"okay\";\n-};\n-\n-/* SMARC SDIO */\n-&usdhc2 {\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\", \"sleep\";\n-\tpinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;\n-\tpinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;\n-\tpinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>;\n-\tpinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>;\n-\tcd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n-\tvmmc-supply = <&reg_usdhc2_vmmc>;\n-\tvqmmc-supply = <&reg_usdhc2_vqmmc>;\n-\twp-gpios = <&som_gpio_expander_1 15 GPIO_ACTIVE_HIGH>;\n-};\n-\n-/* On-module Wi-Fi */\n-&usdhc3 {\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc3>;\n-\tpinctrl-1 = <&pinctrl_usdhc3>;\n-\tpinctrl-2 = <&pinctrl_usdhc3_200mhz>;\n-\tkeep-power-in-suspend;\n-\tnon-removable;\n-\tvmmc-supply = <&reg_wifi_en>;\n-};\n-\n-&scmi_bbm {\n-\tlinux,code = <KEY_POWER>;\n-};\n-\n-&wdog3 {\n-\tfsl,ext-reset-output;\n-\tstatus = \"okay\";\n-};\n-\n-&scmi_iomuxc {\n-\t/* SMARC CAM_MCK */\n-\tpinctrl_cam_mck: cammckgrp {\n-\t\tfsl,pins = <IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1\t0x51e>; /* SMARC S6 - CAM_MCK */\n-\t};\n-\n-\tpinctrl_ec_int: ecintgrp {\n-\t\tfsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11\t0x31e>; /* SAI1_TXFS - EC_MCU_INT# */\n-\t};\n-\n-\t/* SMARC MDIO, shared between all ethernet ports */\n-\tpinctrl_emdio: emdiogrp {\n-\t\tfsl,pins = <IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC\t\t0x50e>, /* SMARC S45 - MDIO_CLK */\n-\t\t\t   <IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO\t\t0x90e>; /* SMARC S46 - MDIO_DAT */\n-\t};\n-\n-\t/* SMARC GBE0 */\n-\tpinctrl_enetc0: enetc0grp {\n-\t\tfsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL\t0x57e>, /* ENET1_TX_CTL */\n-\t\t\t   <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK\t\t0x58e>, /* ENET1_TXC    */\n-\t\t\t   <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0\t\t0x50e>, /* ENET1_TDO    */\n-\t\t\t   <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1\t\t0x50e>, /* ENET1_TD1    */\n-\t\t\t   <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2\t\t0x50e>, /* ENET1_TD2    */\n-\t\t\t   <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3\t\t0x50e>, /* ENET1_TD3    */\n-\t\t\t   <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL\t0x57e>, /* ENET1_RX_CTL */\n-\t\t\t   <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK\t\t0x58e>, /* ENET1_RXC    */\n-\t\t\t   <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0\t\t0x57e>, /* ENET1_RD0    */\n-\t\t\t   <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1\t\t0x57e>, /* ENET1_RD1    */\n-\t\t\t   <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2\t\t0x57e>, /* ENET1_RD2    */\n-\t\t\t   <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3\t\t0x57e>; /* ENET1_RD3    */\n-\t};\n-\n-\t/* SMARC GBE0_SDP */\n-\tpinctrl_enetc0_1588_tmr: enetc01588tmrgrp {\n-\t\tfsl,pins = <IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1\t0x51e>; /* SMARC P6 - GBE0_SDP */\n-\t};\n-\n-\t/* SMARC GBE1 */\n-\tpinctrl_enetc1: enetc1grp {\n-\t\tfsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL\t0x57e>, /* ENET2_TX_CTL */\n-\t\t\t   <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK\t\t0x58e>, /* ENET2_TXC    */\n-\t\t\t   <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0\t\t0x50e>, /* ENET2_TD0    */\n-\t\t\t   <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1\t\t0x50e>, /* ENET2_TD1    */\n-\t\t\t   <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2\t\t0x50e>, /* ENET2_TD2    */\n-\t\t\t   <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3\t\t0x50e>, /* ENET2_TD3    */\n-\t\t\t   <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL\t0x57e>, /* ENET2_RX_CTL */\n-\t\t\t   <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK\t\t0x58e>, /* ENET2_RXC    */\n-\t\t\t   <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0\t\t0x57e>, /* ENET2_RD0    */\n-\t\t\t   <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1\t\t0x57e>, /* ENET2_RD1    */\n-\t\t\t   <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2\t\t0x57e>, /* ENET2_RD2    */\n-\t\t\t   <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3\t\t0x57e>; /* ENET2_RD3    */\n-\t};\n-\n-\t/* SMARC GBE1_SDP */\n-\tpinctrl_enetc1_1588_tmr: enetc11588tmrgrp {\n-\t\tfsl,pins = <IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2\t0x51e>; /* SMARC P5 - GBE1_SDP */\n-\t};\n-\n-\t/* SMARC CAN0 */\n-\tpinctrl_flexcan1: flexcan1grp {\n-\t\tfsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX\t\t0x39e>, /* SMARC P143 - CAN0_TX */\n-\t\t\t   <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX\t0x39e>; /* SMARC P144 - CAN0_RX */\n-\t};\n-\n-\t/* SMARC CAN1 */\n-\tpinctrl_flexcan2: flexcan2grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX\t0x39e>, /* SMARC P145 - CAN1_TX */\n-\t\t\t   <IMX95_PAD_GPIO_IO27__CAN2_RX\t0x39e>; /* SMARC P146 - CAN1_RX */\n-\t};\n-\n-\t/* SMARC GPIO2 */\n-\tpinctrl_gpio2: gpio2grp {\n-\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0\t0x31e>; /* SMARC P110 - GPIO2 */\n-\t};\n-\n-\t/* SMARC GPIO3 */\n-\tpinctrl_gpio3: gpio3grp {\n-\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1\t0x31e>; /* SMARC P111 - GPIO3 */\n-\t};\n-\n-\t/* SMARC GPIO4 */\n-\tpinctrl_gpio4: gpio4grp {\n-\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2\t0x31e>; /* SMARC P112 - GPIO4 */\n-\t};\n-\n-\t/* SMARC GPIO5 */\n-\tpinctrl_gpio5: gpio5grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6\t0x31e>; /* SMARC P113 - GPIO5 */\n-\t};\n-\n-\t/* SMARC GPIO5 as PWM */\n-\tpinctrl_gpio5_pwm: gpio5pwmgrp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0\t0x11e>; /* SMARC P113 - PWM_OUT */\n-\t};\n-\n-\t/* SMARC GPIO6 */\n-\tpinctrl_gpio6: gpio6grp {\n-\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3\t0x31e>; /* SMARC P114 - GPIO6 */\n-\t};\n-\n-\t/* SMARC GPIO7 */\n-\tpinctrl_gpio7: gpio7grp {\n-\t\tfsl,pins = <IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e>; /* SMARC P115 - GPIO7 */\n-\t};\n-\n-\t/* SMARC GPIO8 */\n-\tpinctrl_gpio8: gpio8grp {\n-\t\tfsl,pins = <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10\t0x31e>; /* SMARC P116 - GPIO8 */\n-\t};\n-\n-\t/* SMARC GPIO9 */\n-\tpinctrl_gpio9: gpio9grp {\n-\t\tfsl,pins = <IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8\t0x31e>; /* SMARC P117 - GPIO9 */\n-\t};\n-\n-\t/* SMARC GPIO10 */\n-\tpinctrl_gpio10: gpio10grp {\n-\t\tfsl,pins = <IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15\t0x31e>; /* SMARC P118 - GPIO10 */\n-\t};\n-\n-\t/* SMARC GPIO11 */\n-\tpinctrl_gpio11: gpio11grp {\n-\t\tfsl,pins = <IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14\t0x31e>; /* SMARC P119 - GPIO11 */\n-\t};\n-\n-\t/* SMARC GPIO12 */\n-\tpinctrl_gpio12: gpio12grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10\t0x31e>; /* SMARC S142 - GPIO12 */\n-\t};\n-\n-\t/* SMARC GPIO13 */\n-\tpinctrl_gpio13: gpio13grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11\t0x31e>; /* SMARC S123 - GPIO13 */\n-\t};\n-\n-\tpinctrl_ctrl_io_exp_int_b: ioexpintgrp {\n-\t\tfsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e>; /* CTRL_IO_EXP_INT_B */\n-\t};\n-\n-\t/* SMARC LCD0_BKLT_PWM */\n-\tpinctrl_lcd0_bklt_pwm: lcd0bkltpwmgrp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO12__TPM3_CH2\t0x51e>; /* SMARC S141 - LCD0_BKLT_PWM */\n-\t};\n-\n-\t/* SMARC LCD1_BKLT_PWM */\n-\tpinctrl_lcd1_bklt_pwm: lcd1bkltpwmgrp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO13__TPM4_CH2\t0x51e>; /* SMARC S122 - LCD1_BKLT_PWM */\n-\t};\n-\n-\t/* SMARC I2C_GP */\n-\tpinctrl_lpi2c2: lpi2c2grp {\n-\t\tfsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL\t0x40001b9e>, /* SMARC S48 - I2C_GP_CK  */\n-\t\t\t   <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA\t0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */\n-\t};\n-\n-\t/* SMARC I2C_GP as GPIOs */\n-\tpinctrl_lpi2c2_gpio: lpi2c2gpiogrp {\n-\t\tfsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2\t0x40001b9e>, /* SMARC S48 - I2C_GP_CK  */\n-\t\t\t   <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3\t0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */\n-\t};\n-\n-\t/* SMARC I2C_PM */\n-\tpinctrl_lpi2c3: lpi2c3grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA\t0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */\n-\t\t\t   <IMX95_PAD_GPIO_IO29__LPI2C3_SCL\t0x40001b9e>; /* SMARC P121 - I2C_PM_CK  */\n-\t};\n-\n-\t/* SMARC I2C_PM as GPIOs */\n-\tpinctrl_lpi2c3_gpio: lpi2c3gpiogrp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28\t0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */\n-\t\t\t   <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29\t0x40001b9e>; /* SMARC P121 - I2C_PM_CK  */\n-\t};\n-\n-\t/* I2C_SOM */\n-\tpinctrl_lpi2c4: lpi2c4grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO31__LPI2C4_SCL\t0x40001b9e>, /* I2C_SOM_CK  */\n-\t\t\t   <IMX95_PAD_GPIO_IO30__LPI2C4_SDA\t0x40001b9e>; /* I2C_SOM_DAT */\n-\t};\n-\n-\t/* I2C_SOM as GPIOs */\n-\tpinctrl_lpi2c4_gpio: lpi2c4gpiogrp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31\t0x40001b9e>, /* I2C_SOM_CK  */\n-\t\t\t   <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30\t0x40001b9e>; /* I2C_SOM_DAT */\n-\t};\n-\n-\t/* SMARC I2C_LCD */\n-\tpinctrl_lpi2c5: lpi2c5grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA\t0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */\n-\t\t\t   <IMX95_PAD_GPIO_IO23__LPI2C5_SCL\t0x40001b9e>; /* SMARC S139 - I2C_LCD_CK  */\n-\t};\n-\n-\t/* SMARC I2C_LCD as GPIOs */\n-\tpinctrl_lpi2c5_gpio: lpi2c5gpiogrp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22\t0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */\n-\t\t\t   <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23\t0x40001b9e>; /* SMARC S139 - I2C_LCD_CK  */\n-\t};\n-\n-\t/* I2C_CAM */\n-\tpinctrl_lpi2c7: lpi2c7grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO08__LPI2C7_SDA\t0x40001b9e>, /* I2C_CAM_DAT */\n-\t\t\t   <IMX95_PAD_GPIO_IO09__LPI2C7_SCL\t0x40001b9e>; /* I2C_CAM_CK  */\n-\t};\n-\n-\t/* I2C_CAM as GPIOs */\n-\tpinctrl_lpi2c7_gpio: lpi2c7gpiogrp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8\t0x40001b9e>, /* I2C_CAM_DAT */\n-\t\t\t   <IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9\t0x40001b9e>; /* I2C_CAM_CK  */\n-\t};\n-\n-\t/* SMARC SPI1 */\n-\tpinctrl_lpspi4: lpspi4grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO37__LPSPI4_SCK\t\t0x3fe>, /* SMARC P56 - SPI1_CK   */\n-\t\t\t   <IMX95_PAD_GPIO_IO36__LPSPI4_SOUT\t\t0x3fe>, /* SMARC P58 - SPI1_DO   */\n-\t\t\t   <IMX95_PAD_GPIO_IO19__LPSPI4_SIN\t\t0x3fe>, /* SMARC P57 - SPI1_DIN  */\n-\t\t\t   <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13\t\t0x3fe>, /* SPI1_TPM_CS#          */\n-\t\t\t   <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18\t\t0x3fe>, /* SMARC P54 - SPI1_CS0# */\n-\t\t\t   <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11\t0x3fe>; /* SMARC P55 - SPI1_CS1# */\n-\t};\n-\n-\t/* SMARC SPI0 */\n-\tpinctrl_lpspi6: lpspi6grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0\t\t0x3fe>, /* SMARC P43 - SPI0_CS0# */\n-\t\t\t   <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24\t\t0x3fe>, /* SMARC P31 - SPI0_CS1# */\n-\t\t\t   <IMX95_PAD_GPIO_IO01__LPSPI6_SIN\t\t0x3fe>, /* SMARC P45 - SPI0_DIN  */\n-\t\t\t   <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT\t\t0x3fe>, /* SMARC P46 - SPI0_DO   */\n-\t\t\t   <IMX95_PAD_GPIO_IO03__LPSPI6_SCK\t\t0x3fe>; /* SMARC P44 - SPI0_CK   */\n-\t};\n-\n-\t/* SMARC PCIE_A */\n-\tpinctrl_pcie0: pcie0grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B\t0x40001b1e>; /* SMARC P78 - PCIE_A_CKREQ# */\n-\t};\n-\n-\t/* SMARC PCIE_B */\n-\tpinctrl_pcie1: pcie1grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B\t0x40001b1e>; /* SMARC P77 - PCIE_B_CKREQ# */\n-\t};\n-\n-\t/* SMARC I2S0 */\n-\tpinctrl_sai3: sai3grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK\t\t0x11e>, /* SMARC S38 - I2S0_CK */\n-\t\t\t   <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0\t0x11e>, /* SMARC S41 - I2S0_SDIN */\n-\t\t\t   <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0\t0x11e>, /* SMARC S40 - I2S0_SDOUT */\n-\t\t\t   <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC\t\t0x11e>; /* SMARC S39 - I2S0_LRCK */\n-\t};\n-\n-\t/* SMARC AUDIO_MCK */\n-\tpinctrl_sai3_mclk: sai3mclkgrp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO17__SAI3_MCLK\t0x31e>; /* SMARC S42 - AUDIO_MCK */\n-\t};\n-\n-\t/* SMARC I2S2 */\n-\tpinctrl_sai5: sai5grp {\n-\t\tfsl,pins = <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK\t\t0x11e>, /* SMARC S53 - I2S2_CK */\n-\t\t\t   <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0\t0x11e>, /* SMARC S51 - I2S2_SDOUT */\n-\t\t\t   <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0\t0x11e>, /* SMARC S52 - I2S2_SDIN */\n-\t\t\t   <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC\t\t0x11e>; /* SMARC S50 - I2S2_LRCK */\n-\t};\n-\n-\t/* SMARC SMB_ALERT# */\n-\tpinctrl_smb_alert_gpio: smbalertgrp {\n-\t\tfsl,pins = <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28\t0x31e>; /* SMARC P1 - SMB_ALERT# */\n-\t};\n-\n-\t/* SMARC SER1, used as the Linux Console */\n-\tpinctrl_uart1: uart1grp {\n-\t\tfsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX\t0x31e>, /* SMARC P134 - SER1_TX */\n-\t\t\t   <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX\t0x31e>; /* SMARC P135 - SER1_RX */\n-\t};\n-\n-\t/* SMARC SER0 */\n-\tpinctrl_uart2: uart2grp {\n-\t\tfsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B\t0x31e>, /* SMARC P132 - SER0_CTS# */\n-\t\t\t   <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B\t0x31e>, /* SMARC P131 - SER0_RTS# */\n-\t\t\t   <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX\t\t0x31e>, /* SMARC P130 - SER0_RX   */\n-\t\t\t   <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX\t\t0x31e>; /* SMARC P129 - SER0_TX   */\n-\t};\n-\n-\t/* SMARC SER3 */\n-\tpinctrl_uart3: uart3grp {\n-\t\tfsl,pins = <IMX95_PAD_GPIO_IO14__LPUART3_TX\t0x31e>, /* SMARC P140 - SER3_TX */\n-\t\t\t   <IMX95_PAD_GPIO_IO15__LPUART3_RX\t0x31e>; /* SMARC P141 - SER3_RX */\n-\t};\n-\n-\t/* On-module eMMC */\n-\tpinctrl_usdhc1: usdhc1grp {\n-\t\tfsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK\t0x158e>, /* SD1_CLK    */\n-\t\t\t   <IMX95_PAD_SD1_CMD__USDHC1_CMD\t0x138e>, /* SD1_CMD    */\n-\t\t\t   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0\t0x138e>, /* SD1_DATA0  */\n-\t\t\t   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1\t0x138e>, /* SD1_DATA1  */\n-\t\t\t   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2\t0x138e>, /* SD1_DATA2  */\n-\t\t\t   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3\t0x138e>, /* SD1_DATA3  */\n-\t\t\t   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4\t0x138e>, /* SD1_DATA4  */\n-\t\t\t   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5\t0x138e>, /* SD1_DATA5  */\n-\t\t\t   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6\t0x138e>, /* SD1_DATA6  */\n-\t\t\t   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7\t0x138e>, /* SD1_DATA7  */\n-\t\t\t   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE\t0x158e>; /* SD1_STROBE */\n-\t};\n-\n-\tpinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {\n-\t\tfsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK\t0x15fe>, /* SD1_CLK    */\n-\t\t\t   <IMX95_PAD_SD1_CMD__USDHC1_CMD\t0x13fe>, /* SD1_CMD    */\n-\t\t\t   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0\t0x13fe>, /* SD1_DATA0  */\n-\t\t\t   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1\t0x13fe>, /* SD1_DATA1  */\n-\t\t\t   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2\t0x13fe>, /* SD1_DATA2  */\n-\t\t\t   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3\t0x13fe>, /* SD1_DATA3  */\n-\t\t\t   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4\t0x13fe>, /* SD1_DATA4  */\n-\t\t\t   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5\t0x13fe>, /* SD1_DATA5  */\n-\t\t\t   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6\t0x13fe>, /* SD1_DATA6  */\n-\t\t\t   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7\t0x13fe>, /* SD1_DATA7  */\n-\t\t\t   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE\t0x15fe>; /* SD1_STROBE */\n-\t};\n-\n-\t/* SMARC SDIO */\n-\tpinctrl_usdhc2: usdhc2grp {\n-\t\tfsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK\t\t0x158e>, /* SMARC P36 - SDIO_CK  */\n-\t\t\t   <IMX95_PAD_SD2_CMD__USDHC2_CMD\t\t0x138e>, /* SMARC P34 - SDIO_CMD */\n-\t\t\t   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0\t\t0x138e>, /* SMARC P39 - SDIO_D0  */\n-\t\t\t   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1\t\t0x138e>, /* SMARC P40 - SDIO_D1  */\n-\t\t\t   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2\t\t0x138e>, /* SMARC P41 - SDIO_D2  */\n-\t\t\t   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3\t\t0x138e>; /* SMARC P42 - SDIO_D3  */\n-\t};\n-\n-\t/* SMARC SDIO */\n-\tpinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {\n-\t\tfsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK\t\t0x15fe>, /* SMARC P36 - SDIO_CK  */\n-\t\t\t   <IMX95_PAD_SD2_CMD__USDHC2_CMD\t\t0x13fe>, /* SMARC P34 - SDIO_CMD */\n-\t\t\t   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0\t\t0x13fe>, /* SMARC P39 - SDIO_D0  */\n-\t\t\t   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1\t\t0x13fe>, /* SMARC P40 - SDIO_D1  */\n-\t\t\t   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2\t\t0x13fe>, /* SMARC P41 - SDIO_D2  */\n-\t\t\t   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3\t\t0x13fe>; /* SMARC P42 - SDIO_D3  */\n-\t};\n-\n-\t/* SMARC SDIO */\n-\tpinctrl_usdhc2_sleep: usdhc2-sleepgrp {\n-\t\tfsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK\t\t0x400>, /* SMARC P36 - SDIO_CK  */\n-\t\t\t   <IMX95_PAD_SD2_CMD__USDHC2_CMD\t\t0x400>, /* SMARC P34 - SDIO_CMD */\n-\t\t\t   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0\t\t0x400>, /* SMARC P39 - SDIO_D0  */\n-\t\t\t   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1\t\t0x400>, /* SMARC P40 - SDIO_D1  */\n-\t\t\t   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2\t\t0x400>, /* SMARC P41 - SDIO_D2  */\n-\t\t\t   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3\t\t0x400>; /* SMARC P42 - SDIO_D3  */\n-\t};\n-\n-\t/* SMARC SDIO_CD# */\n-\tpinctrl_usdhc2_cd: usdhc2-cdgrp {\n-\t\tfsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0\t0x1100>; /* SMARC P35 - SDIO_CD# */\n-\t};\n-\n-\t/* SMARC SDIO_PWR_EN */\n-\tpinctrl_usdhc2_pwr_en: usdhc2-pwrengrp {\n-\t\tfsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7\t0x11e>; /* SMARC P37 - SDIO_PWR_EN */\n-\t};\n-\n-\tpinctrl_usdhc2_vsel: usdhc2-vselgrp {\n-\t\tfsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19\t0x4>; /* PMIC_SD2_VSEL */\n-\t};\n-\n-\t/* On-module Wi-Fi */\n-\tpinctrl_usdhc3: usdhc3grp {\n-\t\tfsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK\t0x158e>, /* SD3_CLK   */\n-\t\t\t   <IMX95_PAD_SD3_CMD__USDHC3_CMD\t0x138e>, /* SD3_CMD   */\n-\t\t\t   <IMX95_PAD_SD3_DATA0__USDHC3_DATA0\t0x138e>, /* SD3_DATA0 */\n-\t\t\t   <IMX95_PAD_SD3_DATA1__USDHC3_DATA1\t0x138e>, /* SD3_DATA1 */\n-\t\t\t   <IMX95_PAD_SD3_DATA2__USDHC3_DATA2\t0x138e>, /* SD3_DATA2 */\n-\t\t\t   <IMX95_PAD_SD3_DATA3__USDHC3_DATA3\t0x138e>; /* SD3_DATA3 */\n-\t};\n-\n-\t/* On-module Wi-Fi */\n-\tpinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {\n-\t\tfsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK\t0x15fe>, /* SD3_CLK   */\n-\t\t\t   <IMX95_PAD_SD3_CMD__USDHC3_CMD\t0x13fe>, /* SD3_CMD   */\n-\t\t\t   <IMX95_PAD_SD3_DATA0__USDHC3_DATA0\t0x13fe>, /* SD3_DATA1 */\n-\t\t\t   <IMX95_PAD_SD3_DATA1__USDHC3_DATA1\t0x13fe>, /* SD3_DATA2 */\n-\t\t\t   <IMX95_PAD_SD3_DATA2__USDHC3_DATA2\t0x13fe>, /* SD3_DATA3 */\n-\t\t\t   <IMX95_PAD_SD3_DATA3__USDHC3_DATA3\t0x13fe>; /* SD3_DATA4 */\n-\t};\n-};\ndiff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig\nindex 6e0958c0842..145747f7585 100644\n--- a/arch/arm/mach-imx/imx9/Kconfig\n+++ b/arch/arm/mach-imx/imx9/Kconfig\n@@ -161,6 +161,7 @@ config TARGET_IMX943_EVK\n config TARGET_TORADEX_SMARC_IMX95\n \tbool \"Support Toradex SMARC iMX95\"\n \tselect IMX95\n+\timply OF_UPSTREAM\n \n config TARGET_IMX952_EVK\n \tbool \"imx952_evk\"\ndiff --git a/board/toradex/smarc-imx95/MAINTAINERS b/board/toradex/smarc-imx95/MAINTAINERS\nindex 73517d36f1f..96d349c06b2 100644\n--- a/board/toradex/smarc-imx95/MAINTAINERS\n+++ b/board/toradex/smarc-imx95/MAINTAINERS\n@@ -1,6 +1,4 @@\n Toradex SMARC iMX95\n-F:\tarch/arm/dts/imx95-toradex-smarc.dtsi\n-F:\tarch/arm/dts/imx95-toradex-smarc-dev.dts\n F:\tarch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi\n F:\tboard/toradex/smarc-imx95/\n F:\tconfigs/toradex-smarc-imx95_defconfig\ndiff --git a/configs/toradex-smarc-imx95_defconfig b/configs/toradex-smarc-imx95_defconfig\nindex ad908949b59..c8da431d1c7 100644\n--- a/configs/toradex-smarc-imx95_defconfig\n+++ b/configs/toradex-smarc-imx95_defconfig\n@@ -10,7 +10,7 @@ CONFIG_NR_DRAM_BANKS=3\n CONFIG_ENV_SIZE=0x2000\n CONFIG_ENV_OFFSET=0xFFFFDE00\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx95-toradex-smarc-dev\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx95-toradex-smarc-dev\"\n CONFIG_TARGET_TORADEX_SMARC_IMX95=y\n CONFIG_OF_LIBFDT_OVERLAY=y\n CONFIG_SYS_MONITOR_LEN=524288\n",
    "prefixes": [
        "1/2"
    ]
}