Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2217596/?format=api
{ "id": 2217596, "url": "http://patchwork.ozlabs.org/api/patches/2217596/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260330-t264-pwm-v3-7-5714427d5976@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330-t264-pwm-v3-7-5714427d5976@nvidia.com>", "list_archive_url": null, "date": "2026-03-30T08:53:56", "name": "[v3,7/7] arm64: tegra: Add PWM controllers on Tegra264", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "693c4a9359127c4ba47e096aa76a1e41da82f3a9", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260330-t264-pwm-v3-7-5714427d5976@nvidia.com/mbox/", "series": [ { "id": 497977, "url": "http://patchwork.ozlabs.org/api/series/497977/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497977", "date": "2026-03-30T08:53:52", "name": "Tegra264 PWM support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497977/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217596/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217596/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13410-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=fDEn/68/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-tegra+bounces-13410-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"fDEn/68/\"", "smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.93.201.40", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com", "smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com", "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nvidia.com;" ], "Received": [ "from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fklRp43qqz1yG8\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 30 Mar 2026 19:54:30 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sto.lore.kernel.org (Postfix) with ESMTP id F3147300C0D9\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 30 Mar 2026 08:54:20 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id A20B73B5319;\n\tMon, 30 Mar 2026 08:54:20 +0000 (UTC)", "from CY3PR05CU001.outbound.protection.outlook.com\n (mail-westcentralusazon11013040.outbound.protection.outlook.com\n [40.93.201.40])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FCBF3B52E7;\n\tMon, 30 Mar 2026 08:54:19 +0000 (UTC)", "from SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20)\n by PH8PR12MB7207.namprd12.prod.outlook.com (2603:10b6:510:225::14) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9769.10; Mon, 30 Mar\n 2026 08:54:15 +0000", "from SJ2PR12MB9161.namprd12.prod.outlook.com\n ([fe80::d9d1:8c49:a703:b017]) by SJ2PR12MB9161.namprd12.prod.outlook.com\n ([fe80::d9d1:8c49:a703:b017%4]) with mapi id 15.20.9769.006; Mon, 30 Mar 2026\n 08:54:15 +0000" ], "ARC-Seal": [ "i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774860860; cv=fail;\n b=m/UlYa6XExwSRld7/Eh6CPpzKw24afbBMBfa7dWG48zmQPnwjxYm70XnnYlVYwkAjDttqBGBwfvDOVuddkLQ7rmzq0d09/qlGFmEB36JLTAUY4CfNJ2X2xwaR81jwQ2ZB1k3FrRrVx7TgyiGL08LDTkcc5CxutvcDAztsgShJBg=", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=eaCw6ch08UFZFDitQpHfVPsF16/us8NQb+qZlid7r6hqb8gjACE2tkCopKQXCrk2d9N2j7tcpcWvz07VU7zjhTuIIHdqARtxhc+wJCF/c6B6jDdToB/KrnltiGP7f1jv5CxYgXTGTQZenrUReTc8K8pG4y94KKzODFMJwsVfizrf9a21kBXsELojTLHzLnTifXgBryXdBwbemIIS9eciGuLXbPwHBxso9W6v7znYMofkndfWPM6bNuLDlxYsuC8LAALpbSCFMv9DoFRPgtRkZuTS7lFvJ6EU3QTkyqCyckz2VTe3N6sja7nUdf0AOt4ONlPFrahts7sd46J8Hg5blw==" ], "ARC-Message-Signature": [ "i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774860860; c=relaxed/simple;\n\tbh=furNPDXZTeGLEC7MAFEiX7UOWt4MEGKhoi99hd8j7Jc=;\n\th=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To:\n\t To:Cc:MIME-Version;\n b=dU31IFTJnJnJGfBXn1aUjXb+pT/enmy6Z4Sq872m0IBuJX3+OIuN3QehebHGtRlalSE+lsUTvTWo1Ia0crhFqztqAwIrXRa/arTiKdQ67hCUdIvgehSKEhfvkJ0iFWy0fWVV5PcJUvHubDgaMhkmeUAXZ2Gv92/wh5SX0pYMjrc=", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=V4e3T8/wHGH1MGCYChzTeTntjX5tt56SeqPBDudJ3NY=;\n b=VrKEPAKULzR7ucg3txvy1uPk13ExXe1Z8knZKoBNtZ2WUv7XMyw0mcr+odROKoOzURr7cb2vtyDxWx5RCFF3bRfEU+yWnK5YRUjQQFRYLUA24LjkdA97OMy48eZp8WL2Wt5dkDApkRiIKyovZ44nptF76TXhzCHE/t1tyRJ8lZOeZ4NFCcbG6v0+c9nYz4BNEpppakx2ml95cnAIu+I8AImHCbUO5Zat4OYDfcnzmCAapZj/5WFlqxf3kgajoA2AlWQJ2aI0uwFKNFI3XTK4fQlWiFDsUh/17arB9DVMYwBhQg7yC523wqB9Jjxn2g+hHz8AfLeS/h4EZVXo+sEf+A==" ], "ARC-Authentication-Results": [ "i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=fDEn/68/; arc=fail smtp.client-ip=40.93.201.40", "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=V4e3T8/wHGH1MGCYChzTeTntjX5tt56SeqPBDudJ3NY=;\n b=fDEn/68/XSiFWvWeXB7Yp1wWsPDj8rKaFWwPyULZojPBr87+XjERGAVAevr3yEvZ9h7DqJsYRmqfz0bufcRsHuevY9s9SD/DrUMR9UuM2YYBdsB/rrbaqvg4u0eV5YlaPr/cxMhxygatclBHcIQFcB7ILW40XLbyKi7bWfDAcsZiQmS8RjPIALQQSQwjjTxP0NyZbCog/Kp0jKiLvtMcsNBqlShMHjL88kEjCDZoUroAbyb4maHbw0LUTpiV8/49F4fv/w0mx95AbOm3gVYyhmMCuOU27sk8iXBvKbWVUHpcs3fsvfdf/jvfhMFhTykxHE233IdZKe2o0F5wfk0/Vg==", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "Date": "Mon, 30 Mar 2026 17:53:56 +0900", "Subject": "[PATCH v3 7/7] arm64: tegra: Add PWM controllers on Tegra264", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260330-t264-pwm-v3-7-5714427d5976@nvidia.com>", "References": "<20260330-t264-pwm-v3-0-5714427d5976@nvidia.com>", "In-Reply-To": "<20260330-t264-pwm-v3-0-5714427d5976@nvidia.com>", "To": "Thierry Reding <thierry.reding@gmail.com>, =?utf-8?q?Uwe_Kleine-K=C3=B6n?=\n\t=?utf-8?q?ig?= <ukleinek@kernel.org>,\n Jonathan Hunter <jonathanh@nvidia.com>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n Thierry Reding <treding@nvidia.com>,\n Mikko Perttunen <mperttunen@nvidia.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": "MW4PR03CA0159.namprd03.prod.outlook.com\n (2603:10b6:303:8d::14) To SJ2PR12MB9161.namprd12.prod.outlook.com\n (2603:10b6:a03:566::20)", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ2PR12MB9161:EE_|PH8PR12MB7207:EE_", "X-MS-Office365-Filtering-Correlation-Id": "9600f592-fc5b-4f73-fb59-08de8e39ebb8", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|376014|366016|10070799003|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n\thW8FUb1lGSGi6N3EZrVFzr/Zd52KIhf/2gjXHsPTAy1eml2Oxi95IhWxtYqCpnp34JD6YvfcIyX0/MCDDy1mgs307GRLhqwzBEK/5759sSHj9UhqamkVF561wbT8lQtpB0mxXZZPcgHZq7u8DgcxlAG/jefMGs6D1WG6BvZTTY42SAIY3uXFiqqEBk2WPr9LSVebid3aS2GdMlck7nZTMr0fGbbajhb7IZ/x/TCaZWgrYbyElEpqW3/2W69AKQOlkftFSAMnJj1sx9SXdpvmw3bY+BCYmQGrHpdqudMuR7NeX9r3S6t0OUaU3QSUCTZZMJ0kDa9DhnOLruhFNkGcGRKIHQ3U/I2Ga78AQOzChHH/Ne5tMYD4QodWu0E9FvZtJ7/wrudJ1PF7twdTdaZ6VOUoCFNJysAXEunRQODQvlSh24mSMcCdUuDkBZ0OWR4Xher5OBWWbonAGuN4AyENaZbPfdrZwERFhDBarrrC3VaA4QjXEYDzCQeBAYUH48sxFxYnCULrvwwL1bXBGc3mI9GqWBvb9zqVSfjkFET/wPGeQ1nL8CbyRN3y94NOmxltQ275Wr6ONzo67MGGzpEnZnOqftovIDFOR+vmcr7RXLTkc0r9WGUEpI6c1ORoUc6U9+TylDpqwxQvK3AHQ17MGKQpxlmeu3+6drGC8Wgri4taMAT5HAqCbIFA05simH9LYPkepvLv4rrsZjqb2Lzm6nyuUuaSNKg75IfhbHPPePc=", "X-Forefront-Antispam-Report": "\n\tCIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SJ2PR12MB9161.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016)(10070799003)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "2", "X-MS-Exchange-AntiSpam-MessageData-0": "=?utf-8?q?vjKpjjkL8JDWiROlZWE1G5KCDdZd?=\n\t=?utf-8?q?u7UZuanRAskzsfCs/PXnfeRygL/PAhKkQEnjJ93XnPvwlw7drvJDU6GXIMZqO2TCG?=\n\t=?utf-8?q?db602Z1KN0g/H54Ok1stTRwOmQROCdmUoo2Qf379a4hk/Tzd0tTyyRiiGMgbm+q1G?=\n\t=?utf-8?q?e19N4xoBLsxmpxfTB7bQFJ0sjWFEbL8jhDfF2g4Jg+SZg2E5CkyV2Ppl5VorZzTrG?=\n\t=?utf-8?q?xOK46JLahas5CGj7OQe0vCz2ZiMUx2oZajioNDPwQ8IiKgne3E3ZrVuvcQJgEg7wv?=\n\t=?utf-8?q?LoUtL7ADo6I1qbAz7BjLe2/MCF7ZlFl/ltDilhggASkGzoboluO/4dwob6dJLWph5?=\n\t=?utf-8?q?VPLedVLV8EuLSOspHagppJNvKmn1WcglPYqyn/6ULzJm9tAnmt76e3Ju5+ThMwliC?=\n\t=?utf-8?q?Vmhd6RAjus1bDrrFrngkc7pcJPDdiuVVseyfdkX0DVYsb/w15lsBNHWvsZk3Dlz7a?=\n\t=?utf-8?q?v4kQOZUImFutyAhcQzi3wJnJAVZWMlsqnWxYCh6o+akyzcz0UOQkIASBwVWPLkbyR?=\n\t=?utf-8?q?EO97bq6/e7xsGFgDSgkizoXqArRSh2n6p3LCO78+R/b5luTLywjrCtxjdJMKKKZt/?=\n\t=?utf-8?q?+K8C0TPaWu77YChxiKAXGyw8VZhk2fDgwi5Om4SZdyJJMhZyerxfFzBOoQJG1rqe6?=\n\t=?utf-8?q?LGJp5lshMXeaOzxxClmEeM1vVSagJ1LMQfT9QOiYuTnQx6TO4dSsQgDaLbtd4kyMP?=\n\t=?utf-8?q?mKhbhhYaMt6sYPxHbeaVGdD4azfS9z5BxEy7kiAwNGMv46ZHRjVdQBg2c96XntH8G?=\n\t=?utf-8?q?nbzxQD5B8978vtw6BAImVNES0ouVpIDXV0pe3E368Y5Sx7SM6gQldljA/HqAmOIue?=\n\t=?utf-8?q?wiqUV5be7etZUtq2LLC8Vr+TK3wVxcK6xsyOxlxiz72HWsC1tdW7idGdAZhu93XOe?=\n\t=?utf-8?q?0X4iMODOjczjzviiq+8FJtxt6J4Wtt1+E68tw8n88p4grhkSmyDJlw8sq42ekEQtl?=\n\t=?utf-8?q?YyNFktoDYxLBqNWKuLlyQmzQccXYxPM1fTCM9fGRKDBEP5I/saTiSGeoe1XmeSyWC?=\n\t=?utf-8?q?j5RhPEYuJe7PNPtbGA1jF+8elYNisdXTByrs0ybbw3L0Q+wknRZIcnx2cedfrqlR9?=\n\t=?utf-8?q?klOiEbtnH6iz/2hQLiDvy6/kvhSnOaVNuxA5BhvDdfP0yPxEp67e0At58tsjKKKzb?=\n\t=?utf-8?q?b521CEIc+/BsUnuiPJdgddY+mNucjlMQbXV9Pcc3jvruzbVVkFAHSN6wDGF3smlrU?=\n\t=?utf-8?q?+ymmntMNuFBN7lD5mijtsBzW5jDJt4JldUXA7IVHGRlM4pteVLR3seIjMuUggeC56?=\n\t=?utf-8?q?NqqGpNOUCX5ztqSPxo/Z529HlNJuzAz8ZLmsiCBnFEJcFUweXggNk944CwkZA0NQT?=\n\t=?utf-8?q?H8RAUnrmw3zOotTEY/KKB3Kut2XG5TGXRJyfGwdshM0fuzvKwUosxW/+KwU7qSSSG?=\n\t=?utf-8?q?dVGlW9offTD5GRNNJaRBJNWad44AbzJqsFPhspSVl1b4aVrWsnMaQvU44W9XbUvZ5?=\n\t=?utf-8?q?+q+mFs+z8puYeAdUdbzgQ2BbXtAECaYkfEgN3d5PCRNmZKLWOxMndxm9tt8s0RnQW?=\n\t=?utf-8?q?qqmTXH0ksTs+rdihOgwtNT1WClpRS4VGK+O9cpqKzb8go2UHzR54E/rsT+7c8Szxg?=\n\t=?utf-8?q?FEn9lAd2Y1QCv8UqmQPN+aUnLlQ2NC8OG4yrNJr9dP6bc35iPALpaTTzsfBbaDfyR?=\n\t=?utf-8?q?CL/mnuY9FAh/zNFYDWXp6VAnBnkjFB+t3h05a+pmTrXN+oq2Q/NXeJaiBwadAyuhr?=\n\t=?utf-8?q?XAqWHVdrCoIa90bsY?=", "X-MS-Exchange-AntiSpam-MessageData-1": "FUcX/PfnO3r2ZJxwUrVoDvJ9C7VEdOnvHeU=", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9600f592-fc5b-4f73-fb59-08de8e39ebb8", "X-MS-Exchange-CrossTenant-AuthSource": "SJ2PR12MB9161.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Mar 2026 08:54:15.4079\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n XCwVzKgbNQtvhQFwAoaU16YJmxyZvKZisF5V9b88VMl3ZOAZ2KmZeaDvy7PYW+xhSxqzS1TgFFSoRVJKQjtBeQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH8PR12MB7207" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nTegra264 has a number of PWM controllers that are similar but\nincompatible with those found on earlier chips.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n[mperttunen: Adjust commit message]\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\n arch/arm64/boot/dts/nvidia/tegra264.dtsi | 72 ++++++++++++++++++++++++++++++++\n 1 file changed, 72 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi\nindex 7644a41d5f72..13fd04068016 100644\n--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi\n+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi\n@@ -3336,6 +3336,18 @@ i2c3: i2c@c610000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tpwm4: pwm@c6a0000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc6a0000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM4>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM4>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n \t\tpmc: pmc@c800000 {\n \t\t\tcompatible = \"nvidia,tegra264-pmc\";\n \t\t\treg = <0x0 0x0c800000 0x0 0x100000>,\n@@ -3538,6 +3550,66 @@ i2c16: i2c@c430000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tpwm2: pwm@c5e0000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc5e0000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM2>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM2>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n+\t\tpwm3: pwm@c5f0000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc5f0000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM3>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM3>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n+\t\tpwm5: pwm@c600000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc600000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM5>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM5>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n+\t\tpwm9: pwm@c610000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc610000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM9>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM9>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n+\t\tpwm10: pwm@c620000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc620000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM10>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM10>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n \t\ti2c0: i2c@c630000 {\n \t\t\tcompatible = \"nvidia,tegra264-i2c\";\n \t\t\treg = <0x00 0x0c630000 0x0 0x10000>;\n", "prefixes": [ "v3", "7/7" ] }