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GET /api/patches/2217595/?format=api
{ "id": 2217595, "url": "http://patchwork.ozlabs.org/api/patches/2217595/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260330-t264-pwm-v3-6-5714427d5976@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330-t264-pwm-v3-6-5714427d5976@nvidia.com>", "list_archive_url": null, "date": "2026-03-30T08:53:55", "name": "[v3,6/7] pwm: tegra: Add support for Tegra264", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2b4b091067139932ae074d98953a4b7862163ae7", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260330-t264-pwm-v3-6-5714427d5976@nvidia.com/mbox/", "series": [ { "id": 497977, "url": "http://patchwork.ozlabs.org/api/series/497977/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497977", "date": "2026-03-30T08:53:52", "name": "Tegra264 PWM support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497977/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217595/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217595/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13409-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit 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header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=6lI5vCtTJRWEYYBs6iFamPe8E0USN1Uctqb9jRn6Rgs=;\n b=MD9IokRx9agPQ3LU9grOhxa7XM08LKTrJ+jvF2K7D3m37tKO2VNg3pkDfc2atdi2v8IparfFuOBucSsDc/C3/FOFAoYJ5dfSL/xX4q5Q88ABAmlVxDI1W51vmt7781+mKi3SZ+I1WAINhR8z9Fm1bSQVBliegpgQk3m+qBoztaYpoPULk8n88pDxUArgrEnDzrXMlSO4O9tKKy82OKPlUri9+/L+aiALr63gwKmfacftY21gq+K4ylR6caIygcYfMDDU9EkF5PchpmH7jhX9GUK9ycrSX02ibeCAHPdrt3hORwlXJkOW6YldX24QDFBU45Y8M5nMtMocJPELEKaJzQ==", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "Date": "Mon, 30 Mar 2026 17:53:55 +0900", "Subject": "[PATCH v3 6/7] pwm: tegra: Add support for Tegra264", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Message-Id": "<20260330-t264-pwm-v3-6-5714427d5976@nvidia.com>", "References": "<20260330-t264-pwm-v3-0-5714427d5976@nvidia.com>", "In-Reply-To": "<20260330-t264-pwm-v3-0-5714427d5976@nvidia.com>", "To": "Thierry Reding <thierry.reding@gmail.com>, =?utf-8?q?Uwe_Kleine-K=C3=B6n?=\n\t=?utf-8?q?ig?= <ukleinek@kernel.org>,\n Jonathan Hunter <jonathanh@nvidia.com>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n Yi-Wei Wang <yiweiw@nvidia.com>, Mikko Perttunen <mperttunen@nvidia.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": "MW4PR04CA0335.namprd04.prod.outlook.com\n (2603:10b6:303:8a::10) To SJ2PR12MB9161.namprd12.prod.outlook.com\n (2603:10b6:a03:566::20)", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": 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"X-MS-Exchange-AntiSpam-MessageData-1": "Kdrzx7lwAMcGIQ==", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 14356628-7557-4f67-a385-08de8e39ea16", "X-MS-Exchange-CrossTenant-AuthSource": "SJ2PR12MB9161.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Mar 2026 08:54:12.7193\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n k9Fnmyi38LzZIZS5VWfBffQSiOP5ngKTDuxH6PZS8Svm2cw4JW1hnpR4a3kYbnwL5G/salQg7KnQWfXQqg7Nsg==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH8PR12MB7207" }, "content": "Tegra264 changes the register layout to accommodate wider fields\nfor duty and scale, and adds configurable depth which will be\nsupported in a later patch.\n\nAdd SoC data and update top comment to describe register layout\nin more detail.\n\nCo-developed-by: Yi-Wei Wang <yiweiw@nvidia.com>\nSigned-off-by: Yi-Wei Wang <yiweiw@nvidia.com>\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\n drivers/pwm/pwm-tegra.c | 75 ++++++++++++++++++++++++++++++++++++++++---------\n 1 file changed, 61 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c\nindex 857301baad51..c1e8a804d783 100644\n--- a/drivers/pwm/pwm-tegra.c\n+++ b/drivers/pwm/pwm-tegra.c\n@@ -7,22 +7,60 @@\n * Copyright (c) 2010-2020, NVIDIA Corporation.\n * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>\n *\n- * Overview of Tegra Pulse Width Modulator Register:\n- * 1. 13-bit: Frequency division (SCALE)\n- * 2. 8-bit : Pulse division (DUTY)\n- * 3. 1-bit : Enable bit\n+ * Overview of Tegra Pulse Width Modulator Register\n+ * CSR_0 of Tegra20, Tegra186, and Tegra194:\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | Bit | Field | Description |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 31 | ENB | Enable Pulse width modulator. |\n+ * | | | 0 = DISABLE, 1 = ENABLE. |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 30:16 | PWM_0 | Pulse width that needs to be programmed. |\n+ * | | | 0 = Always low. |\n+ * | | | 1 = 1 / 256 pulse high. |\n+ * | | | 2 = 2 / 256 pulse high. |\n+ * | | | N = N / 256 pulse high. |\n+ * | | | Only 8 bits are usable [23:16]. |\n+ * | | | Bit[24] can be programmed to 1 to achieve 100% duty |\n+ * | | | cycle. In this case the other bits [23:16] are set to |\n+ * | | | don’t care. |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 12:0 | PFM_0 | Frequency divider that needs to be programmed, also known |\n+ * | | | as SCALE. Division by (1 + PFM_0). |\n+ * +-------+-------+-----------------------------------------------------------+\n *\n- * The PWM clock frequency is divided by 256 before subdividing it based\n- * on the programmable frequency division value to generate the required\n- * frequency for PWM output. The maximum output frequency that can be\n- * achieved is (max rate of source clock) / 256.\n- * e.g. if source clock rate is 408 MHz, maximum output frequency can be:\n- * 408 MHz/256 = 1.6 MHz.\n- * This 1.6 MHz frequency can further be divided using SCALE value in PWM.\n+ * CSR_0 of Tegra264:\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | Bit | Field | Description |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 31:16 | PWM_0 | Pulse width that needs to be programmed. |\n+ * | | | 0 = Always low. |\n+ * | | | 1 = 1 / (1 + CSR_1.DEPTH) pulse high. |\n+ * | | | 2 = 2 / (1 + CSR_1.DEPTH) pulse high. |\n+ * | | | N = N / (1 + CSR_1.DEPTH) pulse high. |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 15:0 | PFM_0 | Frequency divider that needs to be programmed, also known |\n+ * | | | as SCALE. Division by (1 + PFM_0). |\n+ * +-------+-------+-----------------------------------------------------------+\n+ *\n+ * CSR_1 of Tegra264:\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | Bit | Field | Description |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 31 | ENB | Enable Pulse width modulator. |\n+ * | | | 0 = DISABLE, 1 = ENABLE. |\n+ * +-------+-------+-----------------------------------------------------------+\n+ * | 30:15 | DEPTH | Depth for pulse width modulator. This controls the pulse |\n+ * | | | time generated. Division by (1 + CSR_1.DEPTH). |\n+ * +-------+-------+-----------------------------------------------------------+\n *\n- * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.\n- * To achieve 100% duty cycle, program Bit [24] of this register to\n- * 1’b1. In which case the other bits [23:16] are set to don't care.\n+ * The PWM clock frequency is divided by DEPTH = (1 + CSR_1.DEPTH) before subdividing it\n+ * based on the programmable frequency division value to generate the required frequency\n+ * for PWM output. DEPTH is fixed to 256 before Tegra264. The maximum output frequency\n+ * that can be achieved is (max rate of source clock) / DEPTH.\n+ * e.g. if source clock rate is 408 MHz, and DEPTH = 256, maximum output frequency can be:\n+ * 408 MHz / 256 ~= 1.6 MHz.\n+ * This 1.6 MHz frequency can further be divided using SCALE value in PWM.\n *\n * Limitations:\n * -\tWhen PWM is disabled, the output is driven to inactive.\n@@ -56,6 +94,7 @@\n #define PWM_SCALE_SHIFT\t0\n \n #define PWM_CSR_0\t0\n+#define PWM_CSR_1\t4\n \n #define PWM_DEPTH\t256\n \n@@ -418,10 +457,18 @@ static const struct tegra_pwm_soc tegra186_pwm_soc = {\n \t.scale_width = 13,\n };\n \n+static const struct tegra_pwm_soc tegra264_pwm_soc = {\n+\t.num_channels = 1,\n+\t.enable_reg = PWM_CSR_1,\n+\t.duty_width = 16,\n+\t.scale_width = 16,\n+};\n+\n static const struct of_device_id tegra_pwm_of_match[] = {\n \t{ .compatible = \"nvidia,tegra20-pwm\", .data = &tegra20_pwm_soc },\n \t{ .compatible = \"nvidia,tegra186-pwm\", .data = &tegra186_pwm_soc },\n \t{ .compatible = \"nvidia,tegra194-pwm\", .data = &tegra186_pwm_soc },\n+\t{ .compatible = \"nvidia,tegra264-pwm\", .data = &tegra264_pwm_soc },\n \t{ }\n };\n MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);\n", "prefixes": [ "v3", "6/7" ] }