Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2217589/?format=api
{ "id": 2217589, "url": "http://patchwork.ozlabs.org/api/patches/2217589/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260330083429.359819-8-l.scorcia@gmail.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330083429.359819-8-l.scorcia@gmail.com>", "list_archive_url": null, "date": "2026-03-30T08:29:41", "name": "[v4,7/9] regulator: Add MediaTek MT6392 regulator", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8bd77e6769a785f57feb8f489c771b49b5c71449", "submitter": { "id": 92693, "url": "http://patchwork.ozlabs.org/api/people/92693/?format=api", "name": "Luca Leonardo Scorcia", "email": "l.scorcia@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260330083429.359819-8-l.scorcia@gmail.com/mbox/", "series": [ { "id": 497975, "url": "http://patchwork.ozlabs.org/api/series/497975/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=497975", "date": "2026-03-30T08:29:34", "name": "Add support for mt6392 PMIC", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/497975/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217589/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217589/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-34398-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=esE1jc8V;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-gpio+bounces-34398-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"esE1jc8V\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.128.45", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fklF55JyCz1y1q\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 30 Mar 2026 19:45:13 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 148A03037E78\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 30 Mar 2026 08:36:39 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 79BA23AEF55;\n\tMon, 30 Mar 2026 08:36:15 +0000 (UTC)", "from mail-wm1-f45.google.com (mail-wm1-f45.google.com\n [209.85.128.45])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 376243B0AC8\n\tfor <linux-gpio@vger.kernel.org>; Mon, 30 Mar 2026 08:36:11 +0000 (UTC)", "by mail-wm1-f45.google.com with SMTP id\n 5b1f17b1804b1-486fc4725f0so40830055e9.1\n for <linux-gpio@vger.kernel.org>;\n Mon, 30 Mar 2026 01:36:10 -0700 (PDT)", "from luca-vm.lan ([154.61.61.58])\n by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-48722c6b495sm508329995e9.2.2026.03.30.01.36.07\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 30 Mar 2026 01:36:08 -0700 (PDT)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774859775; cv=none;\n b=jdZV7Y4fMwmbUfuzAJBdDQXqDEqHZ9JNeTkQkTXfOBAq8KDOx5f4whk08UCZlBFEEuwLKuyezZCfWQ/7UbtFZIO55Ku+W8hX46QWcoFqWWL9PdjzcfC8G7vZICFFBNGR8uo45B7DZM1Oipgt8/vVAUe5cIpDWUoKCQrvk/CH3mc=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774859775; c=relaxed/simple;\n\tbh=P1N32Wn/m+68J/pQCf+kYVy6DdFESma8pQOvArDEn0w=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=TbJME3mNZP6l8luJJqNPbfISrI5DdG6Sh+TI5bcQBJ9cdudQ4YFhV3I8bf9irY8z7oVhMu8nP0UrdXN3Z/j8i0SfiVTBLN1PCxKgpteBlwpgjFxaBX7Vq87+me9XgJp4yBgjw8cICAPDqUsGXiN8qqcZRDJyu75RKwidSpJCaXw=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com;\n spf=pass smtp.mailfrom=gmail.com;\n dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=esE1jc8V; arc=none smtp.client-ip=209.85.128.45", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1774859769; x=1775464569;\n darn=vger.kernel.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=PRgmbcJ3AXb+74vYgoE0faR1L0KpIWMIXJ5aAz85EHE=;\n b=esE1jc8VAwwOCR3Oz2yc++mqc5qpb4fs2Hr7njNil0fLKb8pffZ42LprefBggKvTYJ\n 6l0soWTRTLoR2/+VhX7Ii6XQupSMulpZesdMp5OfkKmSglqmR15sWaqTsEfjQ6lMycnH\n qeuulFDndbFPIV0KW7d7myxB5RosTyzZWfYrqMkrAITiFpRpI+Wbw6SajYSqYLkQZEk2\n QM2ZyrVwlNCDj1TpX+j60rj2I/GvR4zZl+FfprvFTbfr0szah7xuJnmgl3k3Cav5ZUCz\n gQ0/t0tW+eVIwBlOBGBfl4JZC7TwHrVhhld+gimMpuZnPviBRWPByCeruaqhY7h2YQtM\n MHqQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774859769; x=1775464569;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=PRgmbcJ3AXb+74vYgoE0faR1L0KpIWMIXJ5aAz85EHE=;\n b=JFs9EKNxLY6C3bK+NIB8zcatfxEpyhCPqCjHwq8Fzk/8681lLRiPxujyh63a1l959C\n LIczzpOVwTycxPGS4owZTJletq16Ttv1g3xB7gu5iVUiSJTVc8jPCI6JjaAnx+b0Dka1\n npxipx1h8hgdf2ui4z3mAJXqkK5i2OhKEBRZWm0sA+4jguRJCvHordEXxo6QsMtHwJi6\n ip7dIq+55UI6kh0qHx/6o1A1jgydSyQJRYrA1MdlnkZUirOD81zBJhZv453M5lE1uEol\n UoEjJAGnrQRInZqTswbn1QKvIS97eWi9KwGzJHt+2Cqc4jLcST+uNF72zf6JcA6ZTYq5\n ubQw==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCXQGvOKGsLRF1BTMCmn4L6LRGVVonlyStIjbx8HN9tgnAVcwaBLNGk8vL1a1FX0pIFauUjQCG9bI4Mk@vger.kernel.org", "X-Gm-Message-State": "AOJu0YwhZJ0PsMyUwk7h/36Yx9SviAAQPH2PNRPOP2EPw/4Vfliu1WsV\n\tqiJkPRDIADEazM0hQu3oX8UqRp9/Xw7xQZa5J+6CPOtirasIUD2Z8ixg", "X-Gm-Gg": "ATEYQzwjAKWssCqxF0wh+J33Lnywthf1KHgWrKKyAIKCnjGWXwuzGtKatBF2JF1Eb8i\n\tv/+7RwD0XgLR1hm92nmSBPIMi3YVr+vyQDRMQlhBfAY8UNQNLvRevYUDxyO0DXp2HznoLqSVZy0\n\twsafH8C3Q516ty4rw2Lk2AHVvkIlF+PsYjaDxETNK+v4qSR6nMxXiBxqqKqrP4zM4E/aUKBncyi\n\tASUIPyuuyeR2M5X/HchOt8bGTMcCS7bAwh9b2IyseBKhV8v/2b176sR1q1MjxMs/qgS/yaXFoM8\n\tk5OHTSzGabGSYU1nw4zrwSM2fCRDhLrFrRzD/tpntTrKVavWot1wY5a1bGbT3tgUwws2F7UE5jh\n\tmoeMuumCL2VZS4luG7ICUMYwgXuSAQqMDZ4j5LzdSr6xox5l0f7c9ClRjwTrFmv2eEMWsJgMYSN\n\tfBxMiqQqylCyvXvYnNyTs=", "X-Received": "by 2002:a05:600c:8b66:b0:46e:59bd:f7e2 with SMTP id\n 5b1f17b1804b1-48739547940mr66003685e9.11.1774859768827;\n Mon, 30 Mar 2026 01:36:08 -0700 (PDT)", "From": "Luca Leonardo Scorcia <l.scorcia@gmail.com>", "To": "linux-mediatek@lists.infradead.org", "Cc": "Fabien Parent <parent.f@gmail.com>,\n\tVal Packett <val@packett.cool>,\n\tLuca Leonardo Scorcia <l.scorcia@gmail.com>,\n\tAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,\n\tDmitry Torokhov <dmitry.torokhov@gmail.com>,\n\tRob Herring <robh@kernel.org>,\n\tKrzysztof Kozlowski <krzk+dt@kernel.org>,\n\tConor Dooley <conor+dt@kernel.org>,\n\tSen Chu <sen.chu@mediatek.com>,\n\tSean Wang <sean.wang@mediatek.com>,\n\tMacpaul Lin <macpaul.lin@mediatek.com>,\n\tLee Jones <lee@kernel.org>,\n\tMatthias Brugger <matthias.bgg@gmail.com>,\n\tLinus Walleij <linusw@kernel.org>,\n\tLiam Girdwood <lgirdwood@gmail.com>,\n\tMark Brown <broonie@kernel.org>,\n\tJulien Massot <julien.massot@collabora.com>,\n\tLouis-Alexis Eyraud <louisalexis.eyraud@collabora.com>,\n\tGary Bisson <bisson.gary@gmail.com>,\n\tChen Zhong <chen.zhong@mediatek.com>,\n\tlinux-input@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-pm@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-gpio@vger.kernel.org", "Subject": "[PATCH v4 7/9] regulator: Add MediaTek MT6392 regulator", "Date": "Mon, 30 Mar 2026 09:29:41 +0100", "Message-ID": "<20260330083429.359819-8-l.scorcia@gmail.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260330083429.359819-1-l.scorcia@gmail.com>", "References": "<20260330083429.359819-1-l.scorcia@gmail.com>", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Fabien Parent <parent.f@gmail.com>\n\nThe MT6392 is a regulator found on boards based on the MediaTek\nMT8167, MT8516, and probably other SoCs. It is a so called PMIC and\nconnects as a slave to a SoC using SPI, wrapped inside PWRAP.\n\nSigned-off-by: Fabien Parent <parent.f@gmail.com>\nCo-developed-by: Val Packett <val@packett.cool>\nSigned-off-by: Val Packett <val@packett.cool>\nSigned-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>\nReviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>\n---\n drivers/regulator/Kconfig | 9 +\n drivers/regulator/Makefile | 1 +\n drivers/regulator/mt6392-regulator.c | 509 +++++++++++++++++++++\n include/linux/regulator/mt6392-regulator.h | 42 ++\n 4 files changed, 561 insertions(+)\n create mode 100644 drivers/regulator/mt6392-regulator.c\n create mode 100644 include/linux/regulator/mt6392-regulator.h", "diff": "diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig\nindex d10b6f9243d5..7ae06634a12b 100644\n--- a/drivers/regulator/Kconfig\n+++ b/drivers/regulator/Kconfig\n@@ -1000,6 +1000,15 @@ config REGULATOR_MT6380\n \t This driver supports the control of different power rails of device\n \t through regulator interface.\n \n+config REGULATOR_MT6392\n+\ttristate \"MediaTek MT6392 PMIC\"\n+\tdepends on MFD_MT6397\n+\thelp\n+\t Say y here to select this option to enable the power regulator of\n+\t MediaTek MT6392 PMIC.\n+\t This driver supports the control of different power rails of device\n+\t through regulator interface.\n+\n config REGULATOR_MT6397\n \ttristate \"MediaTek MT6397 PMIC\"\n \tdepends on MFD_MT6397\ndiff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile\nindex 35639f3115fd..e5f1fa91b967 100644\n--- a/drivers/regulator/Makefile\n+++ b/drivers/regulator/Makefile\n@@ -118,6 +118,7 @@ obj-$(CONFIG_REGULATOR_MT6360) += mt6360-regulator.o\n obj-$(CONFIG_REGULATOR_MT6363) += mt6363-regulator.o\n obj-$(CONFIG_REGULATOR_MT6370) += mt6370-regulator.o\n obj-$(CONFIG_REGULATOR_MT6380)\t+= mt6380-regulator.o\n+obj-$(CONFIG_REGULATOR_MT6392)\t+= mt6392-regulator.o\n obj-$(CONFIG_REGULATOR_MT6397)\t+= mt6397-regulator.o\n obj-$(CONFIG_REGULATOR_MTK_DVFSRC) += mtk-dvfsrc-regulator.o\n obj-$(CONFIG_REGULATOR_QCOM_LABIBB) += qcom-labibb-regulator.o\ndiff --git a/drivers/regulator/mt6392-regulator.c b/drivers/regulator/mt6392-regulator.c\nnew file mode 100644\nindex 000000000000..6e0278bded92\n--- /dev/null\n+++ b/drivers/regulator/mt6392-regulator.c\n@@ -0,0 +1,509 @@\n+// SPDX-License-Identifier: GPL-2.0\n+//\n+// Copyright (c) 2020 MediaTek Inc.\n+// Copyright (c) 2020 BayLibre, SAS.\n+// Author: Chen Zhong <chen.zhong@mediatek.com>\n+// Author: Fabien Parent <fparent@baylibre.com>\n+//\n+// Based on mt6397-regulator.c\n+\n+#include <linux/module.h>\n+#include <linux/linear_range.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+#include <linux/mfd/mt6397/core.h>\n+#include <linux/mfd/mt6392/registers.h>\n+#include <linux/regulator/driver.h>\n+#include <linux/regulator/machine.h>\n+#include <linux/regulator/mt6392-regulator.h>\n+#include <linux/regulator/of_regulator.h>\n+#include <dt-bindings/regulator/mediatek,mt6392-regulator.h>\n+\n+/*\n+ * MT6392 regulators' information\n+ *\n+ * @desc: standard fields of regulator description.\n+ * @qi: Mask for query enable signal status of regulators\n+ * @vselon_reg: Register sections for hardware control mode of bucks\n+ * @vselctrl_reg: Register for controlling the buck control mode.\n+ * @vselctrl_mask: Mask for query buck's voltage control mode.\n+ */\n+struct mt6392_regulator_info {\n+\tstruct regulator_desc desc;\n+\tu32 qi;\n+\tu32 vselon_reg;\n+\tu32 vselctrl_reg;\n+\tu32 vselctrl_mask;\n+\tu32 modeset_reg;\n+\tu32 modeset_mask;\n+};\n+\n+#define MT6392_BUCK(match, vreg, supply, min, max, step, volt_ranges,\t\\\n+\t\tenreg, vosel_reg, vosel_mask, voselon_reg, vosel_ctrl,\t\\\n+\t\t_modeset_reg, _modeset_mask, rampdelay)\t\t\t\\\n+[MT6392_ID_##vreg] = {\t\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\t\\\n+\t\t.name = #vreg,\t\t\t\t\t\t\\\n+\t\t.supply_name = supply,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\t\\\n+\t\t.ops = &mt6392_volt_range_ops,\t\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\t\\\n+\t\t.id = MT6392_ID_##vreg,\t\t\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\t\\\n+\t\t.n_voltages = ((max) - (min)) / (step) + 1,\t\t\\\n+\t\t.linear_ranges = volt_ranges,\t\t\t\t\\\n+\t\t.n_linear_ranges = ARRAY_SIZE(volt_ranges),\t\t\\\n+\t\t.vsel_reg = vosel_reg,\t\t\t\t\t\\\n+\t\t.vsel_mask = vosel_mask,\t\t\t\t\\\n+\t\t.enable_reg = enreg,\t\t\t\t\t\\\n+\t\t.enable_mask = BIT(0),\t\t\t\t\t\\\n+\t\t.ramp_delay = rampdelay,\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t.qi = BIT(13),\t\t\t\t\t\t\t\\\n+\t.vselon_reg = voselon_reg,\t\t\t\t\t\\\n+\t.vselctrl_reg = vosel_ctrl,\t\t\t\t\t\\\n+\t.vselctrl_mask = BIT(1),\t\t\t\t\t\\\n+\t.modeset_reg = _modeset_reg,\t\t\t\t\t\\\n+\t.modeset_mask = _modeset_mask,\t\t\t\t\t\\\n+}\n+\n+#define MT6392_LDO(match, vreg, supply, ldo_volt_table, enreg, enbit,\t\\\n+\t\tvosel_reg, vosel_mask, _modeset_reg, _modeset_mask,\t\\\n+\t\tentime)\t\t\t\t\t\t\t\\\n+[MT6392_ID_##vreg] = {\t\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\t\\\n+\t\t.name = #vreg,\t\t\t\t\t\t\\\n+\t\t.supply_name = supply,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\t\\\n+\t\t.ops = &mt6392_volt_table_ops,\t\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\t\\\n+\t\t.id = MT6392_ID_##vreg,\t\t\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\t\\\n+\t\t.n_voltages = ARRAY_SIZE(ldo_volt_table),\t\t\\\n+\t\t.volt_table = ldo_volt_table,\t\t\t\t\\\n+\t\t.vsel_reg = vosel_reg,\t\t\t\t\t\\\n+\t\t.vsel_mask = vosel_mask,\t\t\t\t\\\n+\t\t.enable_reg = enreg,\t\t\t\t\t\\\n+\t\t.enable_mask = BIT(enbit),\t\t\t\t\\\n+\t\t.enable_time = entime,\t\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t.qi = BIT(15),\t\t\t\t\t\t\t\\\n+\t.modeset_reg = _modeset_reg,\t\t\t\t\t\\\n+\t.modeset_mask = _modeset_mask,\t\t\t\t\t\\\n+}\n+\n+#define MT6392_LDO_LINEAR(match, vreg, supply, min, max, step,\t\t\\\n+\t\tvolt_ranges, enreg, enbit, vosel_reg, vosel_mask,\t\\\n+\t\t_modeset_reg, _modeset_mask, entime)\t\t\t\\\n+[MT6392_ID_##vreg] = {\t\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\t\\\n+\t\t.name = #vreg,\t\t\t\t\t\t\\\n+\t\t.supply_name = supply,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\t\\\n+\t\t.ops = &mt6392_volt_ldo_range_ops,\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\t\\\n+\t\t.id = MT6392_ID_##vreg,\t\t\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\t\\\n+\t\t.n_voltages = ((max) - (min)) / (step) + 1,\t\t\\\n+\t\t.linear_ranges = volt_ranges,\t\t\t\t\\\n+\t\t.n_linear_ranges = ARRAY_SIZE(volt_ranges),\t\t\\\n+\t\t.vsel_reg = vosel_reg,\t\t\t\t\t\\\n+\t\t.vsel_mask = vosel_mask,\t\t\t\t\\\n+\t\t.enable_reg = enreg,\t\t\t\t\t\\\n+\t\t.enable_mask = BIT(enbit),\t\t\t\t\\\n+\t\t.enable_time = entime,\t\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t.qi = BIT(15),\t\t\t\t\t\t\t\\\n+\t.modeset_reg = _modeset_reg,\t\t\t\t\t\\\n+\t.modeset_mask = _modeset_mask,\t\t\t\t\t\\\n+}\n+\n+#define MT6392_REG_FIXED(match, vreg, supply, enreg, enbit, volt,\t\\\n+\t\t_modeset_reg, _modeset_mask, entime)\t\t\t\\\n+[MT6392_ID_##vreg] = {\t\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\t\\\n+\t\t.name = #vreg,\t\t\t\t\t\t\\\n+\t\t.supply_name = supply,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\t\\\n+\t\t.ops = &mt6392_volt_fixed_ops,\t\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\t\\\n+\t\t.id = MT6392_ID_##vreg,\t\t\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\t\\\n+\t\t.n_voltages = 1,\t\t\t\t\t\\\n+\t\t.enable_reg = enreg,\t\t\t\t\t\\\n+\t\t.enable_mask = BIT(enbit),\t\t\t\t\\\n+\t\t.enable_time = entime,\t\t\t\t\t\\\n+\t\t.min_uV = volt,\t\t\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t.qi = BIT(15),\t\t\t\t\t\t\t\\\n+\t.modeset_reg = _modeset_reg,\t\t\t\t\t\\\n+\t.modeset_mask = _modeset_mask,\t\t\t\t\t\\\n+}\n+\n+#define MT6392_REG_FIXED_NO_MODE(match, vreg, supply, enreg, enbit,\t\\\n+\tvolt, entime)\t\t\t\t\t\t\t\\\n+[MT6392_ID_##vreg] = {\t\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\t\\\n+\t\t.name = #vreg,\t\t\t\t\t\t\\\n+\t\t.supply_name = supply,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\t\\\n+\t\t.ops = &mt6392_volt_fixed_no_mode_ops,\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\t\\\n+\t\t.id = MT6392_ID_##vreg,\t\t\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\t\\\n+\t\t.n_voltages = 1,\t\t\t\t\t\\\n+\t\t.enable_reg = enreg,\t\t\t\t\t\\\n+\t\t.enable_mask = BIT(enbit),\t\t\t\t\\\n+\t\t.enable_time = entime,\t\t\t\t\t\\\n+\t\t.min_uV = volt,\t\t\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t.qi = BIT(15),\t\t\t\t\t\t\t\\\n+}\n+\n+static const struct linear_range buck_volt_range1[] = {\n+\tREGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250),\n+};\n+\n+static const struct linear_range buck_volt_range2[] = {\n+\tREGULATOR_LINEAR_RANGE(1400000, 0, 0x7f, 12500),\n+};\n+\n+static const u32 ldo_volt_table1[] = {\n+\t1800000, 1900000, 2000000, 2200000,\n+};\n+\n+static const u32 ldo_volt_table1b[] = {\n+\t1500000, 1800000, 2500000, 2800000,\n+};\n+\n+static const struct linear_range ldo_volt_range2[] = {\n+\tREGULATOR_LINEAR_RANGE(3300000, 0, 3, 100000),\n+};\n+\n+static const u32 ldo_volt_table3[] = {\n+\t1800000, 3300000,\n+};\n+\n+static const u32 ldo_volt_table4[] = {\n+\t3000000, 3300000,\n+};\n+\n+static const u32 ldo_volt_table5[] = {\n+\t1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, 3300000,\n+};\n+\n+static const u32 ldo_volt_table6[] = {\n+\t1240000, 1390000,\n+};\n+\n+static const u32 ldo_volt_table7[] = {\n+\t1200000, 1300000, 1500000, 1800000,\n+};\n+\n+static const u32 ldo_volt_table8[] = {\n+\t1800000, 2000000,\n+};\n+\n+static int mt6392_buck_set_mode(struct regulator_dev *rdev, unsigned int mode)\n+{\n+\tint ret, val = 0;\n+\tstruct mt6392_regulator_info *info = rdev_get_drvdata(rdev);\n+\n+\tswitch (mode) {\n+\tcase REGULATOR_MODE_FAST:\n+\t\tval = MT6392_BUCK_MODE_FORCE_PWM;\n+\t\tbreak;\n+\tcase REGULATOR_MODE_NORMAL:\n+\t\tval = MT6392_BUCK_MODE_AUTO;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tval <<= ffs(info->modeset_mask) - 1;\n+\n+\tret = regmap_update_bits(rdev->regmap, info->modeset_reg,\n+\t\t\t\t info->modeset_mask, val);\n+\n+\treturn ret;\n+}\n+\n+static unsigned int mt6392_buck_get_mode(struct regulator_dev *rdev)\n+{\n+\tunsigned int val;\n+\tunsigned int mode;\n+\tint ret;\n+\tstruct mt6392_regulator_info *info = rdev_get_drvdata(rdev);\n+\n+\tret = regmap_read(rdev->regmap, info->modeset_reg, &val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval &= info->modeset_mask;\n+\tval >>= ffs(info->modeset_mask) - 1;\n+\n+\tif (val & 0x1)\n+\t\tmode = REGULATOR_MODE_FAST;\n+\telse\n+\t\tmode = REGULATOR_MODE_NORMAL;\n+\n+\treturn mode;\n+}\n+\n+static int mt6392_ldo_set_mode(struct regulator_dev *rdev, unsigned int mode)\n+{\n+\tint ret, val = 0;\n+\tstruct mt6392_regulator_info *info = rdev_get_drvdata(rdev);\n+\n+\tswitch (mode) {\n+\tcase REGULATOR_MODE_STANDBY:\n+\t\tval = MT6392_LDO_MODE_LP;\n+\t\tbreak;\n+\tcase REGULATOR_MODE_NORMAL:\n+\t\tval = MT6392_LDO_MODE_NORMAL;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tval <<= ffs(info->modeset_mask) - 1;\n+\n+\tret = regmap_update_bits(rdev->regmap, info->modeset_reg,\n+\t\t\t\t info->modeset_mask, val);\n+\n+\treturn ret;\n+}\n+\n+static unsigned int mt6392_ldo_get_mode(struct regulator_dev *rdev)\n+{\n+\tunsigned int val;\n+\tunsigned int mode;\n+\tint ret;\n+\tstruct mt6392_regulator_info *info = rdev_get_drvdata(rdev);\n+\n+\tret = regmap_read(rdev->regmap, info->modeset_reg, &val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval &= info->modeset_mask;\n+\tval >>= ffs(info->modeset_mask) - 1;\n+\n+\tif (val & 0x1)\n+\t\tmode = REGULATOR_MODE_STANDBY;\n+\telse\n+\t\tmode = REGULATOR_MODE_NORMAL;\n+\n+\treturn mode;\n+}\n+\n+static const struct regulator_ops mt6392_volt_range_ops = {\n+\t.list_voltage = regulator_list_voltage_linear_range,\n+\t.map_voltage = regulator_map_voltage_linear_range,\n+\t.set_voltage_sel = regulator_set_voltage_sel_regmap,\n+\t.get_voltage_sel = regulator_get_voltage_sel_regmap,\n+\t.set_voltage_time_sel = regulator_set_voltage_time_sel,\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+\t.set_mode = mt6392_buck_set_mode,\n+\t.get_mode = mt6392_buck_get_mode,\n+};\n+\n+static const struct regulator_ops mt6392_volt_table_ops = {\n+\t.list_voltage = regulator_list_voltage_table,\n+\t.map_voltage = regulator_map_voltage_iterate,\n+\t.set_voltage_sel = regulator_set_voltage_sel_regmap,\n+\t.get_voltage_sel = regulator_get_voltage_sel_regmap,\n+\t.set_voltage_time_sel = regulator_set_voltage_time_sel,\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+\t.set_mode = mt6392_ldo_set_mode,\n+\t.get_mode = mt6392_ldo_get_mode,\n+};\n+\n+static const struct regulator_ops mt6392_volt_ldo_range_ops = {\n+\t.list_voltage = regulator_list_voltage_linear_range,\n+\t.map_voltage = regulator_map_voltage_linear_range,\n+\t.set_voltage_sel = regulator_set_voltage_sel_regmap,\n+\t.get_voltage_sel = regulator_get_voltage_sel_regmap,\n+\t.set_voltage_time_sel = regulator_set_voltage_time_sel,\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+\t.set_mode = mt6392_ldo_set_mode,\n+\t.get_mode = mt6392_ldo_get_mode,\n+};\n+\n+static const struct regulator_ops mt6392_volt_fixed_ops = {\n+\t.list_voltage = regulator_list_voltage_linear,\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+\t.set_mode = mt6392_ldo_set_mode,\n+\t.get_mode = mt6392_ldo_get_mode,\n+};\n+\n+static const struct regulator_ops mt6392_volt_fixed_no_mode_ops = {\n+\t.list_voltage = regulator_list_voltage_linear,\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+};\n+\n+/* The array is indexed by id(MT6392_ID_XXX) */\n+static struct mt6392_regulator_info mt6392_regulators[] = {\n+\tMT6392_BUCK(\"vproc\", VPROC, \"vproc\", 700000, 1493750, 6250,\n+\t\t buck_volt_range1, MT6392_VPROC_CON7, MT6392_VPROC_CON9, 0x7f,\n+\t\t MT6392_VPROC_CON10, MT6392_VPROC_CON5, MT6392_VPROC_CON2, 0x100,\n+\t\t 12500),\n+\tMT6392_BUCK(\"vsys\", VSYS, \"vsys\", 1400000, 2987500, 12500,\n+\t\t buck_volt_range2, MT6392_VSYS_CON7, MT6392_VSYS_CON9, 0x7f,\n+\t\t MT6392_VSYS_CON10, MT6392_VSYS_CON5, MT6392_VSYS_CON2, 0x100,\n+\t\t 25000),\n+\tMT6392_BUCK(\"vcore\", VCORE, \"vcore\", 700000, 1493750, 6250,\n+\t\t buck_volt_range1, MT6392_VCORE_CON7, MT6392_VCORE_CON9, 0x7f,\n+\t\t MT6392_VCORE_CON10, MT6392_VCORE_CON5, MT6392_VCORE_CON2, 0x100,\n+\t\t 12500),\n+\tMT6392_REG_FIXED(\"vxo22\", VXO22, \"ldo1\", MT6392_ANALDO_CON1, 10, 2200000,\n+\t\t\t MT6392_ANALDO_CON1, 0x2, 110),\n+\tMT6392_LDO(\"vaud22\", VAUD22, \"ldo1\", ldo_volt_table1,\n+\t\t MT6392_ANALDO_CON2, 14, MT6392_ANALDO_CON8, 0x60,\n+\t\t MT6392_ANALDO_CON2, 0x2, 264),\n+\tMT6392_REG_FIXED_NO_MODE(\"vcama\", VCAMA, \"ldo1\", MT6392_ANALDO_CON4, 15,\n+\t\t\t\t 2800000, 264),\n+\tMT6392_REG_FIXED(\"vaud28\", VAUD28, \"ldo1\", MT6392_ANALDO_CON23, 14, 2800000,\n+\t\t\t MT6392_ANALDO_CON23, 0x2, 264),\n+\tMT6392_REG_FIXED(\"vadc18\", VADC18, \"ldo1\", MT6392_ANALDO_CON25, 14, 1800000,\n+\t\t\t MT6392_ANALDO_CON25, 0x2, 264),\n+\tMT6392_LDO_LINEAR(\"vcn35\", VCN35, \"ldo2\", 3300000, 3600000, 100000,\n+\t\t\t ldo_volt_range2, MT6392_ANALDO_CON21, 12,\n+\t\t\t MT6392_ANALDO_CON16, 0xC, MT6392_ANALDO_CON21, 0x2, 264),\n+\tMT6392_REG_FIXED(\"vio28\", VIO28, \"ldo2\", MT6392_DIGLDO_CON0, 14, 2800000,\n+\t\t\t MT6392_DIGLDO_CON0, 0x2, 264),\n+\tMT6392_REG_FIXED(\"vusb\", VUSB, \"ldo3\", MT6392_DIGLDO_CON2, 14, 3300000,\n+\t\t\t MT6392_DIGLDO_CON2, 0x2, 264),\n+\tMT6392_LDO(\"vmc\", VMC, \"ldo2\", ldo_volt_table3,\n+\t\t MT6392_DIGLDO_CON3, 12, MT6392_DIGLDO_CON24, 0x10,\n+\t\t MT6392_DIGLDO_CON3, 0x2, 264),\n+\tMT6392_LDO(\"vmch\", VMCH, \"ldo2\", ldo_volt_table4,\n+\t\t MT6392_DIGLDO_CON5, 14, MT6392_DIGLDO_CON26, 0x80,\n+\t\t MT6392_DIGLDO_CON5, 0x2, 264),\n+\tMT6392_LDO(\"vemc3v3\", VEMC3V3, \"ldo3\", ldo_volt_table4,\n+\t\t MT6392_DIGLDO_CON6, 14, MT6392_DIGLDO_CON27, 0x80,\n+\t\t MT6392_DIGLDO_CON6, 0x2, 264),\n+\tMT6392_LDO(\"vgp1\", VGP1, \"ldo3\", ldo_volt_table5,\n+\t\t MT6392_DIGLDO_CON7, 15, MT6392_DIGLDO_CON28, 0xE0,\n+\t\t MT6392_DIGLDO_CON7, 0x2, 264),\n+\tMT6392_LDO(\"vgp2\", VGP2, \"ldo3\", ldo_volt_table5,\n+\t\t MT6392_DIGLDO_CON8, 15, MT6392_DIGLDO_CON29, 0xE0,\n+\t\t MT6392_DIGLDO_CON8, 0x2, 264),\n+\tMT6392_REG_FIXED(\"vcn18\", VCN18, \"avddldo\", MT6392_DIGLDO_CON11, 14, 1800000,\n+\t\t\t MT6392_DIGLDO_CON11, 0x2, 264),\n+\tMT6392_LDO(\"vcamaf\", VCAMAF, \"ldo3\", ldo_volt_table5,\n+\t\t MT6392_DIGLDO_CON31, 15, MT6392_DIGLDO_CON32, 0xE0,\n+\t\t MT6392_DIGLDO_CON31, 0x2, 264),\n+\tMT6392_LDO(\"vm\", VM, \"avddldo\", ldo_volt_table6,\n+\t\t MT6392_DIGLDO_CON47, 14, MT6392_DIGLDO_CON48, 0x30,\n+\t\t MT6392_DIGLDO_CON47, 0x2, 264),\n+\tMT6392_REG_FIXED(\"vio18\", VIO18, \"avddldo\", MT6392_DIGLDO_CON49, 14, 1800000,\n+\t\t\t MT6392_DIGLDO_CON49, 0x2, 264),\n+\tMT6392_LDO(\"vcamd\", VCAMD, \"avddldo\", ldo_volt_table7,\n+\t\t MT6392_DIGLDO_CON51, 14, MT6392_DIGLDO_CON52, 0x60,\n+\t\t MT6392_DIGLDO_CON51, 0x2, 264),\n+\tMT6392_REG_FIXED(\"vcamio\", VCAMIO, \"avddldo\", MT6392_DIGLDO_CON53, 14, 1800000,\n+\t\t\t MT6392_DIGLDO_CON53, 0x2, 264),\n+\tMT6392_REG_FIXED(\"vm25\", VM25, \"ldo3\", MT6392_DIGLDO_CON55, 14, 2500000,\n+\t\t\t MT6392_DIGLDO_CON55, 0x2, 264),\n+\tMT6392_LDO(\"vefuse\", VEFUSE, \"ldo2\", ldo_volt_table8,\n+\t\t MT6392_DIGLDO_CON57, 14, MT6392_DIGLDO_CON58, 0x10,\n+\t\t MT6392_DIGLDO_CON57, 0x2, 264),\n+\tMT6392_REG_FIXED_NO_MODE(\"vdig18\", VDIG18, \"ldo2\", MT6392_DIGLDO_CON12, 15,\n+\t\t\t\t 1800000, 264),\n+\tMT6392_REG_FIXED_NO_MODE(\"vrtc\", VRTC, \"ldo1\", MT6392_DIGLDO_CON15, 15,\n+\t\t\t\t 2800000, 264)\n+};\n+\n+static int mt6392_set_buck_vosel_reg(struct platform_device *pdev)\n+{\n+\tstruct mt6397_chip *mt6392 = dev_get_drvdata(pdev->dev.parent);\n+\tint i;\n+\tu32 regval;\n+\n+\tfor (i = 0; i < MT6392_MAX_REGULATOR; i++) {\n+\t\tif (mt6392_regulators[i].vselctrl_reg) {\n+\t\t\tif (regmap_read(mt6392->regmap,\n+\t\t\t\t\tmt6392_regulators[i].vselctrl_reg,\n+\t\t\t\t\t®val) < 0) {\n+\t\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\t\"Failed to read buck ctrl\\n\");\n+\t\t\t\treturn -EIO;\n+\t\t\t}\n+\n+\t\t\tif (regval & mt6392_regulators[i].vselctrl_mask) {\n+\t\t\t\tmt6392_regulators[i].desc.vsel_reg =\n+\t\t\t\tmt6392_regulators[i].vselon_reg;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mt6392_regulator_probe(struct platform_device *pdev)\n+{\n+\tstruct mt6397_chip *mt6392 = dev_get_drvdata(pdev->dev.parent);\n+\tstruct regulator_config config = {};\n+\tstruct regulator_dev *rdev;\n+\tint i;\n+\n+\tpdev->dev.of_node = pdev->dev.parent->of_node;\n+\n+\t/* Query buck controller to select activated voltage register part */\n+\tif (mt6392_set_buck_vosel_reg(pdev))\n+\t\treturn -EIO;\n+\n+\tconfig.dev = mt6392->dev;\n+\tconfig.regmap = mt6392->regmap;\n+\tfor (i = 0; i < MT6392_MAX_REGULATOR; i++) {\n+\t\tconfig.driver_data = &mt6392_regulators[i];\n+\n+\t\trdev = devm_regulator_register(&pdev->dev,\n+\t\t\t\t\t &mt6392_regulators[i].desc,\n+\t\t\t\t\t &config);\n+\t\tif (IS_ERR(rdev)) {\n+\t\t\tdev_err(&pdev->dev, \"failed to register %s\\n\",\n+\t\t\t\tmt6392_regulators[i].desc.name);\n+\t\t\treturn PTR_ERR(rdev);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct platform_device_id mt6392_platform_ids[] = {\n+\t{\"mt6392-regulator\", 0},\n+\t{ /* sentinel */ },\n+};\n+MODULE_DEVICE_TABLE(platform, mt6392_platform_ids);\n+\n+static struct platform_driver mt6392_regulator_driver = {\n+\t.driver = {\n+\t\t.name = \"mt6392-regulator\",\n+\t\t.probe_type = PROBE_PREFER_ASYNCHRONOUS,\n+\t},\n+\t.probe = mt6392_regulator_probe,\n+\t.id_table = mt6392_platform_ids,\n+};\n+\n+module_platform_driver(mt6392_regulator_driver);\n+\n+MODULE_AUTHOR(\"Chen Zhong <chen.zhong@mediatek.com>\");\n+MODULE_DESCRIPTION(\"Regulator Driver for MediaTek MT6392 PMIC\");\n+MODULE_LICENSE(\"GPL\");\ndiff --git a/include/linux/regulator/mt6392-regulator.h b/include/linux/regulator/mt6392-regulator.h\nnew file mode 100644\nindex 000000000000..0eccd085b062\n--- /dev/null\n+++ b/include/linux/regulator/mt6392-regulator.h\n@@ -0,0 +1,42 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Copyright (c) 2019 MediaTek Inc.\n+ * Author: Chen Zhong <chen.zhong@mediatek.com>\n+ */\n+\n+#ifndef __LINUX_REGULATOR_MT6392_H\n+#define __LINUX_REGULATOR_MT6392_H\n+\n+enum {\n+\tMT6392_ID_VPROC = 0,\n+\tMT6392_ID_VSYS,\n+\tMT6392_ID_VCORE,\n+\tMT6392_ID_VXO22,\n+\tMT6392_ID_VAUD22,\n+\tMT6392_ID_VCAMA,\n+\tMT6392_ID_VAUD28,\n+\tMT6392_ID_VADC18,\n+\tMT6392_ID_VCN35,\n+\tMT6392_ID_VIO28,\n+\tMT6392_ID_VUSB = 10,\n+\tMT6392_ID_VMC,\n+\tMT6392_ID_VMCH,\n+\tMT6392_ID_VEMC3V3,\n+\tMT6392_ID_VGP1,\n+\tMT6392_ID_VGP2,\n+\tMT6392_ID_VCN18,\n+\tMT6392_ID_VCAMAF,\n+\tMT6392_ID_VM,\n+\tMT6392_ID_VIO18,\n+\tMT6392_ID_VCAMD,\n+\tMT6392_ID_VCAMIO,\n+\tMT6392_ID_VM25,\n+\tMT6392_ID_VEFUSE,\n+\tMT6392_ID_VDIG18,\n+\tMT6392_ID_VRTC,\n+\tMT6392_ID_RG_MAX,\n+};\n+\n+#define MT6392_MAX_REGULATOR\tMT6392_ID_RG_MAX\n+\n+#endif /* __LINUX_REGULATOR_MT6392_H */\n", "prefixes": [ "v4", "7/9" ] }