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GET /api/patches/2217588/?format=api
{ "id": 2217588, "url": "http://patchwork.ozlabs.org/api/patches/2217588/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260330083429.359819-6-l.scorcia@gmail.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330083429.359819-6-l.scorcia@gmail.com>", "list_archive_url": null, "date": "2026-03-30T08:29:39", "name": "[v4,5/9] mfd: mt6397: Add support for MT6392 PMIC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9af458a1f1a62a27c77ec6290de0baf6b0674713", "submitter": { "id": 92693, "url": "http://patchwork.ozlabs.org/api/people/92693/?format=api", "name": "Luca Leonardo Scorcia", "email": "l.scorcia@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260330083429.359819-6-l.scorcia@gmail.com/mbox/", "series": [ { "id": 497975, "url": "http://patchwork.ozlabs.org/api/series/497975/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=497975", "date": "2026-03-30T08:29:34", "name": "Add support for mt6392 PMIC", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/497975/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217588/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217588/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-34396-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit 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<dmitry.torokhov@gmail.com>,\n\tRob Herring <robh@kernel.org>,\n\tKrzysztof Kozlowski <krzk+dt@kernel.org>,\n\tConor Dooley <conor+dt@kernel.org>,\n\tSen Chu <sen.chu@mediatek.com>,\n\tSean Wang <sean.wang@mediatek.com>,\n\tMacpaul Lin <macpaul.lin@mediatek.com>,\n\tLee Jones <lee@kernel.org>,\n\tMatthias Brugger <matthias.bgg@gmail.com>,\n\tLinus Walleij <linusw@kernel.org>,\n\tLiam Girdwood <lgirdwood@gmail.com>,\n\tMark Brown <broonie@kernel.org>,\n\tGary Bisson <bisson.gary@gmail.com>,\n\tJulien Massot <julien.massot@collabora.com>,\n\tLouis-Alexis Eyraud <louisalexis.eyraud@collabora.com>,\n\tChen Zhong <chen.zhong@mediatek.com>,\n\tlinux-input@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-pm@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-gpio@vger.kernel.org", "Subject": "[PATCH v4 5/9] mfd: mt6397: Add support for MT6392 PMIC", "Date": "Mon, 30 Mar 2026 09:29:39 +0100", "Message-ID": "<20260330083429.359819-6-l.scorcia@gmail.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260330083429.359819-1-l.scorcia@gmail.com>", "References": "<20260330083429.359819-1-l.scorcia@gmail.com>", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Fabien Parent <parent.f@gmail.com>\n\nAlign the MT6397 PMIC driver to other MFD drivers by passing only an\nidentifier through mt6397_of_match[*].data and add support for the MT6392\nPMIC.\n\nSigned-off-by: Fabien Parent <parent.f@gmail.com>\nSigned-off-by: Val Packett <val@packett.cool>\nSigned-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>\nReviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>\n---\n drivers/mfd/mt6397-core.c | 118 +++++--\n drivers/mfd/mt6397-irq.c | 8 +\n include/linux/mfd/mt6392/core.h | 42 +++\n include/linux/mfd/mt6392/registers.h | 487 +++++++++++++++++++++++++++\n include/linux/mfd/mt6397/core.h | 1 +\n 5 files changed, 630 insertions(+), 26 deletions(-)\n create mode 100644 include/linux/mfd/mt6392/core.h\n create mode 100644 include/linux/mfd/mt6392/registers.h", "diff": "diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c\nindex 3e58d0764c7e..f141759216cf 100644\n--- a/drivers/mfd/mt6397-core.c\n+++ b/drivers/mfd/mt6397-core.c\n@@ -18,6 +18,7 @@\n #include <linux/mfd/mt6357/core.h>\n #include <linux/mfd/mt6358/core.h>\n #include <linux/mfd/mt6359/core.h>\n+#include <linux/mfd/mt6392/core.h>\n #include <linux/mfd/mt6397/core.h>\n #include <linux/mfd/mt6323/registers.h>\n #include <linux/mfd/mt6328/registers.h>\n@@ -25,8 +26,20 @@\n #include <linux/mfd/mt6357/registers.h>\n #include <linux/mfd/mt6358/registers.h>\n #include <linux/mfd/mt6359/registers.h>\n+#include <linux/mfd/mt6392/registers.h>\n #include <linux/mfd/mt6397/registers.h>\n \n+enum mfd_match_data {\n+\tMATCH_DATA_MT6323 = 23,\n+\tMATCH_DATA_MT6328 = 28,\n+\tMATCH_DATA_MT6331 = 31,\n+\tMATCH_DATA_MT6357 = 57,\n+\tMATCH_DATA_MT6358 = 58,\n+\tMATCH_DATA_MT6359 = 59,\n+\tMATCH_DATA_MT6392 = 92,\n+\tMATCH_DATA_MT6397 = 97,\n+};\n+\n #define MT6323_RTC_BASE\t\t0x8000\n #define MT6323_RTC_SIZE\t\t0x40\n \n@@ -39,6 +52,9 @@\n #define MT6358_RTC_BASE\t\t0x0588\n #define MT6358_RTC_SIZE\t\t0x3c\n \n+#define MT6392_RTC_BASE\t\t0x8000\n+#define MT6392_RTC_SIZE\t\t0x3e\n+\n #define MT6397_RTC_BASE\t\t0xe000\n #define MT6397_RTC_SIZE\t\t0x3e\n \n@@ -65,6 +81,11 @@ static const struct resource mt6358_rtc_resources[] = {\n \tDEFINE_RES_IRQ(MT6358_IRQ_RTC),\n };\n \n+static const struct resource mt6392_rtc_resources[] = {\n+\tDEFINE_RES_MEM(MT6392_RTC_BASE, MT6392_RTC_SIZE),\n+\tDEFINE_RES_IRQ(MT6392_IRQ_RTC),\n+};\n+\n static const struct resource mt6397_rtc_resources[] = {\n \tDEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE),\n \tDEFINE_RES_IRQ(MT6397_IRQ_RTC),\n@@ -114,6 +135,11 @@ static const struct resource mt6331_keys_resources[] = {\n \tDEFINE_RES_IRQ_NAMED(MT6331_IRQ_STATUS_HOMEKEY, \"homekey\"),\n };\n \n+static const struct resource mt6392_keys_resources[] = {\n+\tDEFINE_RES_IRQ_NAMED(MT6392_IRQ_PWRKEY, \"powerkey\"),\n+\tDEFINE_RES_IRQ_NAMED(MT6392_IRQ_FCHRKEY, \"homekey\"),\n+};\n+\n static const struct resource mt6397_keys_resources[] = {\n \tDEFINE_RES_IRQ_NAMED(MT6397_IRQ_PWRKEY, \"powerkey\"),\n \tDEFINE_RES_IRQ_NAMED(MT6397_IRQ_HOMEKEY, \"homekey\"),\n@@ -253,6 +279,25 @@ static const struct mfd_cell mt6359_devs[] = {\n \t},\n };\n \n+static const struct mfd_cell mt6392_devs[] = {\n+\t{\n+\t\t.name = \"mt6392-rtc\",\n+\t\t.num_resources = ARRAY_SIZE(mt6392_rtc_resources),\n+\t\t.resources = mt6392_rtc_resources,\n+\t\t.of_compatible = \"mediatek,mt6392-rtc\",\n+\t}, {\n+\t\t.name = \"mt6392-regulator\",\n+\t}, {\n+\t\t.name = \"mt6392-pinctrl\",\n+\t\t.of_compatible = \"mediatek,mt6392-pinctrl\",\n+\t}, {\n+\t\t.name = \"mt6392-keys\",\n+\t\t.num_resources = ARRAY_SIZE(mt6392_keys_resources),\n+\t\t.resources = mt6392_keys_resources,\n+\t\t.of_compatible = \"mediatek,mt6392-keys\"\n+\t},\n+};\n+\n static const struct mfd_cell mt6397_devs[] = {\n \t{\n \t\t.name = \"mt6397-rtc\",\n@@ -335,6 +380,14 @@ static const struct chip_data mt6359_core = {\n \t.irq_init = mt6358_irq_init,\n };\n \n+static const struct chip_data mt6392_core = {\n+\t.cid_addr = MT6392_CID,\n+\t.cid_shift = 0,\n+\t.cells = mt6392_devs,\n+\t.cell_size = ARRAY_SIZE(mt6392_devs),\n+\t.irq_init = mt6397_irq_init,\n+};\n+\n static const struct chip_data mt6397_core = {\n \t.cid_addr = MT6397_CID,\n \t.cid_shift = 0,\n@@ -349,6 +402,7 @@ static int mt6397_probe(struct platform_device *pdev)\n \tunsigned int id = 0;\n \tstruct mt6397_chip *pmic;\n \tconst struct chip_data *pmic_core;\n+\tenum mfd_match_data device_data;\n \n \tpmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);\n \tif (!pmic)\n@@ -364,9 +418,36 @@ static int mt6397_probe(struct platform_device *pdev)\n \tif (!pmic->regmap)\n \t\treturn -ENODEV;\n \n-\tpmic_core = of_device_get_match_data(&pdev->dev);\n-\tif (!pmic_core)\n+\tdevice_data = (enum mfd_match_data)of_device_get_match_data(&pdev->dev);\n+\tswitch (device_data) {\n+\tcase MATCH_DATA_MT6323:\n+\t\tpmic_core = &mt6323_core;\n+\t\tbreak;\n+\tcase MATCH_DATA_MT6328:\n+\t\tpmic_core = &mt6328_core;\n+\t\tbreak;\n+\tcase MATCH_DATA_MT6331:\n+\t\tpmic_core = &mt6331_mt6332_core;\n+\t\tbreak;\n+\tcase MATCH_DATA_MT6357:\n+\t\tpmic_core = &mt6357_core;\n+\t\tbreak;\n+\tcase MATCH_DATA_MT6358:\n+\t\tpmic_core = &mt6358_core;\n+\t\tbreak;\n+\tcase MATCH_DATA_MT6359:\n+\t\tpmic_core = &mt6359_core;\n+\t\tbreak;\n+\tcase MATCH_DATA_MT6392:\n+\t\tpmic_core = &mt6392_core;\n+\t\tbreak;\n+\tcase MATCH_DATA_MT6397:\n+\t\tpmic_core = &mt6397_core;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(&pdev->dev, \"Unknown device match data %u\\n\", device_data);\n \t\treturn -ENODEV;\n+\t}\n \n \tret = regmap_read(pmic->regmap, pmic_core->cid_addr, &id);\n \tif (ret) {\n@@ -398,30 +479,15 @@ static int mt6397_probe(struct platform_device *pdev)\n }\n \n static const struct of_device_id mt6397_of_match[] = {\n-\t{\n-\t\t.compatible = \"mediatek,mt6323\",\n-\t\t.data = &mt6323_core,\n-\t}, {\n-\t\t.compatible = \"mediatek,mt6328\",\n-\t\t.data = &mt6328_core,\n-\t}, {\n-\t\t.compatible = \"mediatek,mt6331\",\n-\t\t.data = &mt6331_mt6332_core,\n-\t}, {\n-\t\t.compatible = \"mediatek,mt6357\",\n-\t\t.data = &mt6357_core,\n-\t}, {\n-\t\t.compatible = \"mediatek,mt6358\",\n-\t\t.data = &mt6358_core,\n-\t}, {\n-\t\t.compatible = \"mediatek,mt6359\",\n-\t\t.data = &mt6359_core,\n-\t}, {\n-\t\t.compatible = \"mediatek,mt6397\",\n-\t\t.data = &mt6397_core,\n-\t}, {\n-\t\t/* sentinel */\n-\t}\n+\t{ .compatible = \"mediatek,mt6323\", .data = (void *)MATCH_DATA_MT6323, },\n+\t{ .compatible = \"mediatek,mt6328\", .data = (void *)MATCH_DATA_MT6328, },\n+\t{ .compatible = \"mediatek,mt6331\", .data = (void *)MATCH_DATA_MT6331, },\n+\t{ .compatible = \"mediatek,mt6357\", .data = (void *)MATCH_DATA_MT6357, },\n+\t{ .compatible = \"mediatek,mt6358\", .data = (void *)MATCH_DATA_MT6358, },\n+\t{ .compatible = \"mediatek,mt6359\", .data = (void *)MATCH_DATA_MT6359, },\n+\t{ .compatible = \"mediatek,mt6392\", .data = (void *)MATCH_DATA_MT6392, },\n+\t{ .compatible = \"mediatek,mt6397\", .data = (void *)MATCH_DATA_MT6397, },\n+\t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, mt6397_of_match);\n \ndiff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c\nindex 5d2e5459f744..80ea5b92d232 100644\n--- a/drivers/mfd/mt6397-irq.c\n+++ b/drivers/mfd/mt6397-irq.c\n@@ -15,6 +15,8 @@\n #include <linux/mfd/mt6328/registers.h>\n #include <linux/mfd/mt6331/core.h>\n #include <linux/mfd/mt6331/registers.h>\n+#include <linux/mfd/mt6392/core.h>\n+#include <linux/mfd/mt6392/registers.h>\n #include <linux/mfd/mt6397/core.h>\n #include <linux/mfd/mt6397/registers.h>\n \n@@ -203,6 +205,12 @@ int mt6397_irq_init(struct mt6397_chip *chip)\n \t\tchip->int_status[0] = MT6397_INT_STATUS0;\n \t\tchip->int_status[1] = MT6397_INT_STATUS1;\n \t\tbreak;\n+\tcase MT6392_CHIP_ID:\n+\t\tchip->int_con[0] = MT6392_INT_CON0;\n+\t\tchip->int_con[1] = MT6392_INT_CON1;\n+\t\tchip->int_status[0] = MT6392_INT_STATUS0;\n+\t\tchip->int_status[1] = MT6392_INT_STATUS1;\n+\t\tbreak;\n \n \tdefault:\n \t\tdev_err(chip->dev, \"unsupported chip: 0x%x\\n\", chip->chip_id);\ndiff --git a/include/linux/mfd/mt6392/core.h b/include/linux/mfd/mt6392/core.h\nnew file mode 100644\nindex 000000000000..4780dab4da92\n--- /dev/null\n+++ b/include/linux/mfd/mt6392/core.h\n@@ -0,0 +1,42 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2020 MediaTek Inc.\n+ * Author: Chen Zhong <chen.zhong@mediatek.com>\n+ */\n+\n+#ifndef __MFD_MT6392_CORE_H__\n+#define __MFD_MT6392_CORE_H__\n+\n+enum mt6392_irq_numbers {\n+\tMT6392_IRQ_SPKL_AB = 0,\n+\tMT6392_IRQ_SPKL,\n+\tMT6392_IRQ_BAT_L,\n+\tMT6392_IRQ_BAT_H,\n+\tMT6392_IRQ_WATCHDOG,\n+\tMT6392_IRQ_PWRKEY,\n+\tMT6392_IRQ_THR_L,\n+\tMT6392_IRQ_THR_H,\n+\tMT6392_IRQ_VBATON_UNDET,\n+\tMT6392_IRQ_BVALID_DET,\n+\tMT6392_IRQ_CHRDET,\n+\tMT6392_IRQ_OV,\n+\tMT6392_IRQ_LDO = 16,\n+\tMT6392_IRQ_FCHRKEY,\n+\tMT6392_IRQ_RELEASE_PWRKEY,\n+\tMT6392_IRQ_RELEASE_FCHRKEY,\n+\tMT6392_IRQ_RTC,\n+\tMT6392_IRQ_VPROC,\n+\tMT6392_IRQ_VSYS,\n+\tMT6392_IRQ_VCORE,\n+\tMT6392_IRQ_TYPE_C_CC,\n+\tMT6392_IRQ_TYPEC_H_MAX,\n+\tMT6392_IRQ_TYPEC_H_MIN,\n+\tMT6392_IRQ_TYPEC_L_MAX,\n+\tMT6392_IRQ_TYPEC_L_MIN,\n+\tMT6392_IRQ_THR_MAX,\n+\tMT6392_IRQ_THR_MIN,\n+\tMT6392_IRQ_NAG_C_DLTV,\n+\tMT6392_IRQ_NR,\n+};\n+\n+#endif /* __MFD_MT6392_CORE_H__ */\ndiff --git a/include/linux/mfd/mt6392/registers.h b/include/linux/mfd/mt6392/registers.h\nnew file mode 100644\nindex 000000000000..4f3a6db830d1\n--- /dev/null\n+++ b/include/linux/mfd/mt6392/registers.h\n@@ -0,0 +1,487 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2020 MediaTek Inc.\n+ * Author: Chen Zhong <chen.zhong@mediatek.com>\n+ */\n+\n+#ifndef __MFD_MT6392_REGISTERS_H__\n+#define __MFD_MT6392_REGISTERS_H__\n+\n+/* PMIC Registers */\n+#define MT6392_CHR_CON0 0x0000\n+#define MT6392_CHR_CON1 0x0002\n+#define MT6392_CHR_CON2 0x0004\n+#define MT6392_CHR_CON3 0x0006\n+#define MT6392_CHR_CON4 0x0008\n+#define MT6392_CHR_CON5 0x000A\n+#define MT6392_CHR_CON6 0x000C\n+#define MT6392_CHR_CON7 0x000E\n+#define MT6392_CHR_CON8 0x0010\n+#define MT6392_CHR_CON9 0x0012\n+#define MT6392_CHR_CON10 0x0014\n+#define MT6392_CHR_CON11 0x0016\n+#define MT6392_CHR_CON12 0x0018\n+#define MT6392_CHR_CON13 0x001A\n+#define MT6392_CHR_CON14 0x001C\n+#define MT6392_CHR_CON15 0x001E\n+#define MT6392_CHR_CON16 0x0020\n+#define MT6392_CHR_CON17 0x0022\n+#define MT6392_CHR_CON18 0x0024\n+#define MT6392_CHR_CON19 0x0026\n+#define MT6392_CHR_CON20 0x0028\n+#define MT6392_CHR_CON21 0x002A\n+#define MT6392_CHR_CON22 0x002C\n+#define MT6392_CHR_CON23 0x002E\n+#define MT6392_CHR_CON24 0x0030\n+#define MT6392_CHR_CON25 0x0032\n+#define MT6392_CHR_CON26 0x0034\n+#define MT6392_CHR_CON27 0x0036\n+#define MT6392_CHR_CON28 0x0038\n+#define MT6392_CHR_CON29 0x003A\n+#define MT6392_STRUP_CON0 0x003C\n+#define MT6392_STRUP_CON2 0x003E\n+#define MT6392_STRUP_CON3 0x0040\n+#define MT6392_STRUP_CON4 0x0042\n+#define MT6392_STRUP_CON5 0x0044\n+#define MT6392_STRUP_CON6 0x0046\n+#define MT6392_STRUP_CON7 0x0048\n+#define MT6392_STRUP_CON8 0x004A\n+#define MT6392_STRUP_CON9 0x004C\n+#define MT6392_STRUP_CON10 0x004E\n+#define MT6392_STRUP_CON11 0x0050\n+#define MT6392_SPK_CON0 0x0052\n+#define MT6392_SPK_CON1 0x0054\n+#define MT6392_SPK_CON2 0x0056\n+#define MT6392_SPK_CON6 0x005E\n+#define MT6392_SPK_CON7 0x0060\n+#define MT6392_SPK_CON8 0x0062\n+#define MT6392_SPK_CON9 0x0064\n+#define MT6392_SPK_CON10 0x0066\n+#define MT6392_SPK_CON11 0x0068\n+#define MT6392_SPK_CON12 0x006A\n+#define MT6392_STRUP_CON12 0x006E\n+#define MT6392_STRUP_CON13 0x0070\n+#define MT6392_STRUP_CON14 0x0072\n+#define MT6392_STRUP_CON15 0x0074\n+#define MT6392_STRUP_CON16 0x0076\n+#define MT6392_STRUP_CON17 0x0078\n+#define MT6392_STRUP_CON18 0x007A\n+#define MT6392_STRUP_CON19 0x007C\n+#define MT6392_STRUP_CON20 0x007E\n+#define MT6392_CID 0x0100\n+#define MT6392_TOP_CKPDN0 0x0102\n+#define MT6392_TOP_CKPDN0_SET 0x0104\n+#define MT6392_TOP_CKPDN0_CLR 0x0106\n+#define MT6392_TOP_CKPDN1 0x0108\n+#define MT6392_TOP_CKPDN1_SET 0x010A\n+#define MT6392_TOP_CKPDN1_CLR 0x010C\n+#define MT6392_TOP_CKPDN2 0x010E\n+#define MT6392_TOP_CKPDN2_SET 0x0110\n+#define MT6392_TOP_CKPDN2_CLR 0x0112\n+#define MT6392_TOP_RST_CON 0x0114\n+#define MT6392_TOP_RST_CON_SET 0x0116\n+#define MT6392_TOP_RST_CON_CLR 0x0118\n+#define MT6392_TOP_RST_MISC 0x011A\n+#define MT6392_TOP_RST_MISC_SET 0x011C\n+#define MT6392_TOP_RST_MISC_CLR 0x011E\n+#define MT6392_TOP_CKCON0 0x0120\n+#define MT6392_TOP_CKCON0_SET 0x0122\n+#define MT6392_TOP_CKCON0_CLR 0x0124\n+#define MT6392_TOP_CKCON1 0x0126\n+#define MT6392_TOP_CKCON1_SET 0x0128\n+#define MT6392_TOP_CKCON1_CLR 0x012A\n+#define MT6392_TOP_CKTST0 0x012C\n+#define MT6392_TOP_CKTST1 0x012E\n+#define MT6392_TOP_CKTST2 0x0130\n+#define MT6392_TEST_OUT 0x0132\n+#define MT6392_TEST_CON0 0x0134\n+#define MT6392_TEST_CON1 0x0136\n+#define MT6392_EN_STATUS0 0x0138\n+#define MT6392_EN_STATUS1 0x013A\n+#define MT6392_OCSTATUS0 0x013C\n+#define MT6392_OCSTATUS1 0x013E\n+#define MT6392_PGSTATUS 0x0140\n+#define MT6392_CHRSTATUS 0x0142\n+#define MT6392_TDSEL_CON 0x0144\n+#define MT6392_RDSEL_CON 0x0146\n+#define MT6392_SMT_CON0 0x0148\n+#define MT6392_SMT_CON1 0x014A\n+#define MT6392_DRV_CON0 0x0152\n+#define MT6392_DRV_CON1 0x0154\n+#define MT6392_INT_CON0 0x0160\n+#define MT6392_INT_CON0_SET 0x0162\n+#define MT6392_INT_CON0_CLR 0x0164\n+#define MT6392_INT_CON1 0x0166\n+#define MT6392_INT_CON1_SET 0x0168\n+#define MT6392_INT_CON1_CLR 0x016A\n+#define MT6392_INT_MISC_CON 0x016C\n+#define MT6392_INT_MISC_CON_SET 0x016E\n+#define MT6392_INT_MISC_CON_CLR 0x0170\n+#define MT6392_INT_STATUS0 0x0172\n+#define MT6392_INT_STATUS1 0x0174\n+#define MT6392_OC_GEAR_0 0x0176\n+#define MT6392_OC_GEAR_1 0x0178\n+#define MT6392_OC_GEAR_2 0x017A\n+#define MT6392_OC_CTL_VPROC 0x017C\n+#define MT6392_OC_CTL_VSYS 0x017E\n+#define MT6392_OC_CTL_VCORE 0x0180\n+#define MT6392_FQMTR_CON0 0x0182\n+#define MT6392_FQMTR_CON1 0x0184\n+#define MT6392_FQMTR_CON2 0x0186\n+#define MT6392_RG_SPI_CON 0x0188\n+#define MT6392_DEW_DIO_EN 0x018A\n+#define MT6392_DEW_READ_TEST 0x018C\n+#define MT6392_DEW_WRITE_TEST 0x018E\n+#define MT6392_DEW_CRC_SWRST 0x0190\n+#define MT6392_DEW_CRC_EN 0x0192\n+#define MT6392_DEW_CRC_VAL 0x0194\n+#define MT6392_DEW_DBG_MON_SEL 0x0196\n+#define MT6392_DEW_CIPHER_KEY_SEL 0x0198\n+#define MT6392_DEW_CIPHER_IV_SEL 0x019A\n+#define MT6392_DEW_CIPHER_EN 0x019C\n+#define MT6392_DEW_CIPHER_RDY 0x019E\n+#define MT6392_DEW_CIPHER_MODE 0x01A0\n+#define MT6392_DEW_CIPHER_SWRST 0x01A2\n+#define MT6392_DEW_RDDMY_NO 0x01A4\n+#define MT6392_DEW_RDATA_DLY_SEL 0x01A6\n+#define MT6392_CLK_TRIM_CON0 0x01A8\n+#define MT6392_BUCK_CON0 0x0200\n+#define MT6392_BUCK_CON1 0x0202\n+#define MT6392_BUCK_CON2 0x0204\n+#define MT6392_BUCK_CON3 0x0206\n+#define MT6392_BUCK_CON4 0x0208\n+#define MT6392_BUCK_CON5 0x020A\n+#define MT6392_VPROC_CON0 0x020C\n+#define MT6392_VPROC_CON1 0x020E\n+#define MT6392_VPROC_CON2 0x0210\n+#define MT6392_VPROC_CON3 0x0212\n+#define MT6392_VPROC_CON4 0x0214\n+#define MT6392_VPROC_CON5 0x0216\n+#define MT6392_VPROC_CON7 0x021A\n+#define MT6392_VPROC_CON8 0x021C\n+#define MT6392_VPROC_CON9 0x021E\n+#define MT6392_VPROC_CON10 0x0220\n+#define MT6392_VPROC_CON11 0x0222\n+#define MT6392_VPROC_CON12 0x0224\n+#define MT6392_VPROC_CON13 0x0226\n+#define MT6392_VPROC_CON14 0x0228\n+#define MT6392_VPROC_CON15 0x022A\n+#define MT6392_VPROC_CON18 0x0230\n+#define MT6392_VSYS_CON0 0x0232\n+#define MT6392_VSYS_CON1 0x0234\n+#define MT6392_VSYS_CON2 0x0236\n+#define MT6392_VSYS_CON3 0x0238\n+#define MT6392_VSYS_CON4 0x023A\n+#define MT6392_VSYS_CON5 0x023C\n+#define MT6392_VSYS_CON7 0x0240\n+#define MT6392_VSYS_CON8 0x0242\n+#define MT6392_VSYS_CON9 0x0244\n+#define MT6392_VSYS_CON10 0x0246\n+#define MT6392_VSYS_CON11 0x0248\n+#define MT6392_VSYS_CON12 0x024A\n+#define MT6392_VSYS_CON13 0x024C\n+#define MT6392_VSYS_CON14 0x024E\n+#define MT6392_VSYS_CON15 0x0250\n+#define MT6392_VSYS_CON18 0x0256\n+#define MT6392_BUCK_OC_CON0 0x0258\n+#define MT6392_BUCK_OC_CON1 0x025A\n+#define MT6392_BUCK_OC_CON2 0x025C\n+#define MT6392_BUCK_OC_CON3 0x025E\n+#define MT6392_BUCK_OC_CON4 0x0260\n+#define MT6392_BUCK_OC_VPROC_CON0 0x0262\n+#define MT6392_BUCK_OC_VCORE_CON0 0x0264\n+#define MT6392_BUCK_OC_VSYS_CON0 0x0266\n+#define MT6392_BUCK_ANA_MON_CON0 0x0268\n+#define MT6392_BUCK_EFUSE_OC_CON0 0x026A\n+#define MT6392_VCORE_CON0 0x0300\n+#define MT6392_VCORE_CON1 0x0302\n+#define MT6392_VCORE_CON2 0x0304\n+#define MT6392_VCORE_CON3 0x0306\n+#define MT6392_VCORE_CON4 0x0308\n+#define MT6392_VCORE_CON5 0x030A\n+#define MT6392_VCORE_CON7 0x030E\n+#define MT6392_VCORE_CON8 0x0310\n+#define MT6392_VCORE_CON9 0x0312\n+#define MT6392_VCORE_CON10 0x0314\n+#define MT6392_VCORE_CON11 0x0316\n+#define MT6392_VCORE_CON12 0x0318\n+#define MT6392_VCORE_CON13 0x031A\n+#define MT6392_VCORE_CON14 0x031C\n+#define MT6392_VCORE_CON15 0x031E\n+#define MT6392_VCORE_CON18 0x0324\n+#define MT6392_BUCK_K_CON0 0x032A\n+#define MT6392_BUCK_K_CON1 0x032C\n+#define MT6392_BUCK_K_CON2 0x032E\n+#define MT6392_ANALDO_CON0 0x0400\n+#define MT6392_ANALDO_CON1 0x0402\n+#define MT6392_ANALDO_CON2 0x0404\n+#define MT6392_ANALDO_CON3 0x0406\n+#define MT6392_ANALDO_CON4 0x0408\n+#define MT6392_ANALDO_CON6 0x040C\n+#define MT6392_ANALDO_CON7 0x040E\n+#define MT6392_ANALDO_CON8 0x0410\n+#define MT6392_ANALDO_CON10 0x0412\n+#define MT6392_ANALDO_CON15 0x0414\n+#define MT6392_ANALDO_CON16 0x0416\n+#define MT6392_ANALDO_CON17 0x0418\n+#define MT6392_ANALDO_CON21 0x0420\n+#define MT6392_ANALDO_CON22 0x0422\n+#define MT6392_ANALDO_CON23 0x0424\n+#define MT6392_ANALDO_CON24 0x0426\n+#define MT6392_ANALDO_CON25 0x0428\n+#define MT6392_ANALDO_CON26 0x042A\n+#define MT6392_ANALDO_CON27 0x042C\n+#define MT6392_ANALDO_CON28 0x042E\n+#define MT6392_ANALDO_CON29 0x0430\n+#define MT6392_DIGLDO_CON0 0x0500\n+#define MT6392_DIGLDO_CON2 0x0502\n+#define MT6392_DIGLDO_CON3 0x0504\n+#define MT6392_DIGLDO_CON5 0x0506\n+#define MT6392_DIGLDO_CON6 0x0508\n+#define MT6392_DIGLDO_CON7 0x050A\n+#define MT6392_DIGLDO_CON8 0x050C\n+#define MT6392_DIGLDO_CON10 0x0510\n+#define MT6392_DIGLDO_CON11 0x0512\n+#define MT6392_DIGLDO_CON12 0x0514\n+#define MT6392_DIGLDO_CON15 0x051A\n+#define MT6392_DIGLDO_CON20 0x0524\n+#define MT6392_DIGLDO_CON21 0x0526\n+#define MT6392_DIGLDO_CON23 0x0528\n+#define MT6392_DIGLDO_CON24 0x052A\n+#define MT6392_DIGLDO_CON26 0x052C\n+#define MT6392_DIGLDO_CON27 0x052E\n+#define MT6392_DIGLDO_CON28 0x0530\n+#define MT6392_DIGLDO_CON29 0x0532\n+#define MT6392_DIGLDO_CON30 0x0534\n+#define MT6392_DIGLDO_CON31 0x0536\n+#define MT6392_DIGLDO_CON32 0x0538\n+#define MT6392_DIGLDO_CON33 0x053A\n+#define MT6392_DIGLDO_CON36 0x0540\n+#define MT6392_DIGLDO_CON41 0x0546\n+#define MT6392_DIGLDO_CON44 0x054C\n+#define MT6392_DIGLDO_CON47 0x0552\n+#define MT6392_DIGLDO_CON48 0x0554\n+#define MT6392_DIGLDO_CON49 0x0556\n+#define MT6392_DIGLDO_CON50 0x0558\n+#define MT6392_DIGLDO_CON51 0x055A\n+#define MT6392_DIGLDO_CON52 0x055C\n+#define MT6392_DIGLDO_CON53 0x055E\n+#define MT6392_DIGLDO_CON54 0x0560\n+#define MT6392_DIGLDO_CON55 0x0562\n+#define MT6392_DIGLDO_CON56 0x0564\n+#define MT6392_DIGLDO_CON57 0x0566\n+#define MT6392_DIGLDO_CON58 0x0568\n+#define MT6392_DIGLDO_CON59 0x056A\n+#define MT6392_DIGLDO_CON60 0x056C\n+#define MT6392_DIGLDO_CON61 0x056E\n+#define MT6392_DIGLDO_CON62 0x0570\n+#define MT6392_DIGLDO_CON63 0x0572\n+#define MT6392_EFUSE_CON0 0x0600\n+#define MT6392_EFUSE_CON1 0x0602\n+#define MT6392_EFUSE_CON2 0x0604\n+#define MT6392_EFUSE_CON3 0x0606\n+#define MT6392_EFUSE_CON4 0x0608\n+#define MT6392_EFUSE_CON5 0x060A\n+#define MT6392_EFUSE_CON6 0x060C\n+#define MT6392_EFUSE_VAL_0_15 0x060E\n+#define MT6392_EFUSE_VAL_16_31 0x0610\n+#define MT6392_EFUSE_VAL_32_47 0x0612\n+#define MT6392_EFUSE_VAL_48_63 0x0614\n+#define MT6392_EFUSE_VAL_64_79 0x0616\n+#define MT6392_EFUSE_VAL_80_95 0x0618\n+#define MT6392_EFUSE_VAL_96_111 0x061A\n+#define MT6392_EFUSE_VAL_112_127 0x061C\n+#define MT6392_EFUSE_VAL_128_143 0x061E\n+#define MT6392_EFUSE_VAL_144_159 0x0620\n+#define MT6392_EFUSE_VAL_160_175 0x0622\n+#define MT6392_EFUSE_VAL_176_191 0x0624\n+#define MT6392_EFUSE_VAL_192_207 0x0626\n+#define MT6392_EFUSE_VAL_208_223 0x0628\n+#define MT6392_EFUSE_VAL_224_239 0x062A\n+#define MT6392_EFUSE_VAL_240_255 0x062C\n+#define MT6392_EFUSE_VAL_256_271 0x062E\n+#define MT6392_EFUSE_VAL_272_287 0x0630\n+#define MT6392_EFUSE_VAL_288_303 0x0632\n+#define MT6392_EFUSE_VAL_304_319 0x0634\n+#define MT6392_EFUSE_VAL_320_335 0x0636\n+#define MT6392_EFUSE_VAL_336_351 0x0638\n+#define MT6392_EFUSE_VAL_352_367 0x063A\n+#define MT6392_EFUSE_VAL_368_383 0x063C\n+#define MT6392_EFUSE_VAL_384_399 0x063E\n+#define MT6392_EFUSE_VAL_400_415 0x0640\n+#define MT6392_EFUSE_VAL_416_431 0x0642\n+#define MT6392_RTC_MIX_CON0 0x0644\n+#define MT6392_RTC_MIX_CON1 0x0646\n+#define MT6392_EFUSE_VAL_432_447 0x0648\n+#define MT6392_EFUSE_VAL_448_463 0x064A\n+#define MT6392_EFUSE_VAL_464_479 0x064C\n+#define MT6392_EFUSE_VAL_480_495 0x064E\n+#define MT6392_EFUSE_VAL_496_511 0x0650\n+#define MT6392_EFUSE_DOUT_0_15 0x0652\n+#define MT6392_EFUSE_DOUT_16_31 0x0654\n+#define MT6392_EFUSE_DOUT_32_47 0x0656\n+#define MT6392_EFUSE_DOUT_48_63 0x0658\n+#define MT6392_EFUSE_DOUT_64_79 0x065A\n+#define MT6392_EFUSE_DOUT_80_95 0x065C\n+#define MT6392_EFUSE_DOUT_96_111 0x065E\n+#define MT6392_EFUSE_DOUT_112_127 0x0660\n+#define MT6392_EFUSE_DOUT_128_143 0x0662\n+#define MT6392_EFUSE_DOUT_144_159 0x0664\n+#define MT6392_EFUSE_DOUT_160_175 0x0666\n+#define MT6392_EFUSE_DOUT_176_191 0x0668\n+#define MT6392_EFUSE_DOUT_192_207 0x066A\n+#define MT6392_EFUSE_DOUT_208_223 0x066C\n+#define MT6392_EFUSE_DOUT_224_239 0x066E\n+#define MT6392_EFUSE_DOUT_240_255 0x0670\n+#define MT6392_EFUSE_DOUT_256_271 0x0672\n+#define MT6392_EFUSE_DOUT_272_287 0x0674\n+#define MT6392_EFUSE_DOUT_288_303 0x0676\n+#define MT6392_EFUSE_DOUT_304_319 0x0678\n+#define MT6392_EFUSE_DOUT_320_335 0x067A\n+#define MT6392_EFUSE_DOUT_336_351 0x067C\n+#define MT6392_EFUSE_DOUT_352_367 0x067E\n+#define MT6392_EFUSE_DOUT_368_383 0x0680\n+#define MT6392_EFUSE_DOUT_384_399 0x0682\n+#define MT6392_EFUSE_DOUT_400_415 0x0684\n+#define MT6392_EFUSE_DOUT_416_431 0x0686\n+#define MT6392_EFUSE_DOUT_432_447 0x0688\n+#define MT6392_EFUSE_DOUT_448_463 0x068A\n+#define MT6392_EFUSE_DOUT_464_479 0x068C\n+#define MT6392_EFUSE_DOUT_480_495 0x068E\n+#define MT6392_EFUSE_DOUT_496_511 0x0690\n+#define MT6392_EFUSE_CON7 0x0692\n+#define MT6392_EFUSE_CON8 0x0694\n+#define MT6392_EFUSE_CON9 0x0696\n+#define MT6392_AUXADC_ADC0 0x0700\n+#define MT6392_AUXADC_ADC1 0x0702\n+#define MT6392_AUXADC_ADC2 0x0704\n+#define MT6392_AUXADC_ADC3 0x0706\n+#define MT6392_AUXADC_ADC4 0x0708\n+#define MT6392_AUXADC_ADC5 0x070A\n+#define MT6392_AUXADC_ADC6 0x070C\n+#define MT6392_AUXADC_ADC7 0x070E\n+#define MT6392_AUXADC_ADC8 0x0710\n+#define MT6392_AUXADC_ADC9 0x0712\n+#define MT6392_AUXADC_ADC10 0x0714\n+#define MT6392_AUXADC_ADC11 0x0716\n+#define MT6392_AUXADC_ADC12 0x0718\n+#define MT6392_AUXADC_ADC13 0x071A\n+#define MT6392_AUXADC_ADC14 0x071C\n+#define MT6392_AUXADC_ADC15 0x071E\n+#define MT6392_AUXADC_ADC16 0x0720\n+#define MT6392_AUXADC_ADC17 0x0722\n+#define MT6392_AUXADC_ADC18 0x0724\n+#define MT6392_AUXADC_ADC19 0x0726\n+#define MT6392_AUXADC_ADC20 0x0728\n+#define MT6392_AUXADC_ADC21 0x072A\n+#define MT6392_AUXADC_ADC22 0x072C\n+#define MT6392_AUXADC_STA0 0x072E\n+#define MT6392_AUXADC_STA1 0x0730\n+#define MT6392_AUXADC_RQST0 0x0732\n+#define MT6392_AUXADC_RQST0_SET 0x0734\n+#define MT6392_AUXADC_RQST0_CLR 0x0736\n+#define MT6392_AUXADC_CON0 0x0738\n+#define MT6392_AUXADC_CON0_SET 0x073A\n+#define MT6392_AUXADC_CON0_CLR 0x073C\n+#define MT6392_AUXADC_CON1 0x073E\n+#define MT6392_AUXADC_CON2 0x0740\n+#define MT6392_AUXADC_CON3 0x0742\n+#define MT6392_AUXADC_CON4 0x0744\n+#define MT6392_AUXADC_CON5 0x0746\n+#define MT6392_AUXADC_CON6 0x0748\n+#define MT6392_AUXADC_CON7 0x074A\n+#define MT6392_AUXADC_CON8 0x074C\n+#define MT6392_AUXADC_CON9 0x074E\n+#define MT6392_AUXADC_CON10 0x0750\n+#define MT6392_AUXADC_CON11 0x0752\n+#define MT6392_AUXADC_CON12 0x0754\n+#define MT6392_AUXADC_CON13 0x0756\n+#define MT6392_AUXADC_CON14 0x0758\n+#define MT6392_AUXADC_CON15 0x075A\n+#define MT6392_AUXADC_CON16 0x075C\n+#define MT6392_AUXADC_AUTORPT0 0x075E\n+#define MT6392_AUXADC_LBAT0 0x0760\n+#define MT6392_AUXADC_LBAT1 0x0762\n+#define MT6392_AUXADC_LBAT2 0x0764\n+#define MT6392_AUXADC_LBAT3 0x0766\n+#define MT6392_AUXADC_LBAT4 0x0768\n+#define MT6392_AUXADC_LBAT5 0x076A\n+#define MT6392_AUXADC_LBAT6 0x076C\n+#define MT6392_AUXADC_THR0 0x076E\n+#define MT6392_AUXADC_THR1 0x0770\n+#define MT6392_AUXADC_THR2 0x0772\n+#define MT6392_AUXADC_THR3 0x0774\n+#define MT6392_AUXADC_THR4 0x0776\n+#define MT6392_AUXADC_THR5 0x0778\n+#define MT6392_AUXADC_THR6 0x077A\n+#define MT6392_AUXADC_EFUSE0 0x077C\n+#define MT6392_AUXADC_EFUSE1 0x077E\n+#define MT6392_AUXADC_EFUSE2 0x0780\n+#define MT6392_AUXADC_EFUSE3 0x0782\n+#define MT6392_AUXADC_EFUSE4 0x0784\n+#define MT6392_AUXADC_EFUSE5 0x0786\n+#define MT6392_AUXADC_NAG_0 0x0788\n+#define MT6392_AUXADC_NAG_1 0x078A\n+#define MT6392_AUXADC_NAG_2 0x078C\n+#define MT6392_AUXADC_NAG_3 0x078E\n+#define MT6392_AUXADC_NAG_4 0x0790\n+#define MT6392_AUXADC_NAG_5 0x0792\n+#define MT6392_AUXADC_NAG_6 0x0794\n+#define MT6392_AUXADC_NAG_7 0x0796\n+#define MT6392_AUXADC_NAG_8 0x0798\n+#define MT6392_AUXADC_TYPEC_H_1 0x079A\n+#define MT6392_AUXADC_TYPEC_H_2 0x079C\n+#define MT6392_AUXADC_TYPEC_H_3 0x079E\n+#define MT6392_AUXADC_TYPEC_H_4 0x07A0\n+#define MT6392_AUXADC_TYPEC_H_5 0x07A2\n+#define MT6392_AUXADC_TYPEC_H_6 0x07A4\n+#define MT6392_AUXADC_TYPEC_H_7 0x07A6\n+#define MT6392_AUXADC_TYPEC_L_1 0x07A8\n+#define MT6392_AUXADC_TYPEC_L_2 0x07AA\n+#define MT6392_AUXADC_TYPEC_L_3 0x07AC\n+#define MT6392_AUXADC_TYPEC_L_4 0x07AE\n+#define MT6392_AUXADC_TYPEC_L_5 0x07B0\n+#define MT6392_AUXADC_TYPEC_L_6 0x07B2\n+#define MT6392_AUXADC_TYPEC_L_7 0x07B4\n+#define MT6392_AUXADC_NAG_9 0x07B6\n+#define MT6392_TYPE_C_PHY_RG_0 0x0800\n+#define MT6392_TYPE_C_PHY_RG_CC_RESERVE_CSR 0x0802\n+#define MT6392_TYPE_C_VCMP_CTRL 0x0804\n+#define MT6392_TYPE_C_CTRL 0x0806\n+#define MT6392_TYPE_C_CC_SW_CTRL 0x080a\n+#define MT6392_TYPE_C_CC_VOL_PERIODIC_MEAS_VAL 0x080c\n+#define MT6392_TYPE_C_CC_VOL_DEBOUNCE_CNT_VAL 0x080e\n+#define MT6392_TYPE_C_DRP_SRC_CNT_VAL_0 0x0810\n+#define MT6392_TYPE_C_DRP_SNK_CNT_VAL_0 0x0814\n+#define MT6392_TYPE_C_DRP_TRY_CNT_VAL_0 0x0818\n+#define MT6392_TYPE_C_CC_SRC_DEFAULT_DAC_VAL 0x0820\n+#define MT6392_TYPE_C_CC_SRC_15_DAC_VAL 0x0822\n+#define MT6392_TYPE_C_CC_SRC_30_DAC_VAL 0x0824\n+#define MT6392_TYPE_C_CC_SNK_DAC_VAL_0 0x0828\n+#define MT6392_TYPE_C_CC_SNK_DAC_VAL_1 0x082a\n+#define MT6392_TYPE_C_INTR_EN_0 0x0830\n+#define MT6392_TYPE_C_INTR_EN_2 0x0834\n+#define MT6392_TYPE_C_INTR_0 0x0838\n+#define MT6392_TYPE_C_INTR_2 0x083C\n+#define MT6392_TYPE_C_CC_STATUS 0x0840\n+#define MT6392_TYPE_C_PWR_STATUS 0x0842\n+#define MT6392_TYPE_C_PHY_RG_CC1_RESISTENCE_0 0x0844\n+#define MT6392_TYPE_C_PHY_RG_CC1_RESISTENCE_1 0x0846\n+#define MT6392_TYPE_C_PHY_RG_CC2_RESISTENCE_0 0x0848\n+#define MT6392_TYPE_C_PHY_RG_CC2_RESISTENCE_1 0x084a\n+#define MT6392_TYPE_C_CC_SW_FORCE_MODE_ENABLE_0 0x0860\n+#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_0 0x0864\n+#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_1 0x0866\n+#define MT6392_TYPE_C_CC_SW_FORCE_MODE_ENABLE_1 0x0868\n+#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_2 0x086c\n+#define MT6392_TYPE_C_CC_DAC_CALI_CTRL 0x0870\n+#define MT6392_TYPE_C_CC_DAC_CALI_RESULT 0x0872\n+#define MT6392_TYPE_C_DEBUG_PORT_SELECT_0 0x0880\n+#define MT6392_TYPE_C_DEBUG_PORT_SELECT_1 0x0882\n+#define MT6392_TYPE_C_DEBUG_MODE_SELECT 0x0884\n+#define MT6392_TYPE_C_DEBUG_OUT_READ_0 0x0888\n+#define MT6392_TYPE_C_DEBUG_OUT_READ_1 0x088a\n+#define MT6392_TYPE_C_SW_DEBUG_PORT_0 0x088c\n+#define MT6392_TYPE_C_SW_DEBUG_PORT_1 0x088e\n+\n+#endif /* __MFD_MT6392_REGISTERS_H__ */\ndiff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h\nindex b774c3a4bb62..d665d0777065 100644\n--- a/include/linux/mfd/mt6397/core.h\n+++ b/include/linux/mfd/mt6397/core.h\n@@ -20,6 +20,7 @@ enum chip_id {\n \tMT6359_CHIP_ID = 0x59,\n \tMT6366_CHIP_ID = 0x66,\n \tMT6391_CHIP_ID = 0x91,\n+\tMT6392_CHIP_ID = 0x92,\n \tMT6397_CHIP_ID = 0x97,\n };\n \n", "prefixes": [ "v4", "5/9" ] }