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GET /api/patches/2217559/?format=api
{ "id": 2217559, "url": "http://patchwork.ozlabs.org/api/patches/2217559/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260330-andes-pwm-v5-1-01c59a659d2c@andestech.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330-andes-pwm-v5-1-01c59a659d2c@andestech.com>", "list_archive_url": null, "date": "2026-03-30T07:45:43", "name": "[v5,1/3] dt-bindings: pwm: add support for AE350 PWM controller", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "39047d65467cd0fc62fbcb4d03eafc3df8d1d5a1", "submitter": { "id": 92477, "url": "http://patchwork.ozlabs.org/api/people/92477/?format=api", "name": "Ben Zong-You Xie via B4 Relay", "email": "devnull+ben717.andestech.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260330-andes-pwm-v5-1-01c59a659d2c@andestech.com/mbox/", "series": [ { "id": 497968, "url": "http://patchwork.ozlabs.org/api/series/497968/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=497968", "date": "2026-03-30T07:45:42", "name": "pwm: add support for Andes platform", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/497968/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217559/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217559/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pwm+bounces-8406-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=GqAhYRol;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8406-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"GqAhYRol\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fkjx43s0gz1y1q\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 30 Mar 2026 18:46:16 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id C5B3E3008A79\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 30 Mar 2026 07:45:47 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 5A9383A7595;\n\tMon, 30 Mar 2026 07:45:46 +0000 (UTC)", "from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id A63123A6B93;\n\tMon, 30 Mar 2026 07:45:45 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPS id 455D0C2BCB1;\n\tMon, 30 Mar 2026 07:45:45 +0000 (UTC)", "from aws-us-west-2-korg-lkml-1.web.codeaurora.org\n (localhost.localdomain [127.0.0.1])\n\tby smtp.lore.kernel.org (Postfix) with ESMTP id 329F0FF495D;\n\tMon, 30 Mar 2026 07:45:45 +0000 (UTC)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774856745; cv=none;\n b=X2gP8rFyo+kYz+DgIQQeqjY7wEgaiSPvgGnXY18HYvHPRo1A+VYtY/HxoLdhWyWPcZECHe0xmn5rV29IG9uWG+2Akovra3ywZ5eZ5PVQrUlg//7fpnUHrLdjeeS7atLpQWFDxWJij17JV62hZn0MrFharhHp8TFwV44whx00raI=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774856745; c=relaxed/simple;\n\tbh=kgoSJfCQHW0+Dg62ei7S7n3mzCu8wyzu0Bm2onZRb/E=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=YcU/UU3cHeY1FQlYsj2oVq1amN2HxE5gYVopnHD9Qx6KH8NsEvZZX65K/IwJCa8CDFSCmoAyb+MLVDOdgkO+D1undX50+WaJwueASXoO2jeJ6NJF72ImlmGpH7sKwDFqI+7UcrokAVz8gGcSxrEvrSqetN8QCxOAGfsq3MylRcs=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=GqAhYRol; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1774856745;\n\tbh=kgoSJfCQHW0+Dg62ei7S7n3mzCu8wyzu0Bm2onZRb/E=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=GqAhYRolWpytfcV1zWzmDgJNplfJgUGPaXMaSZJATUbC3L6JQ4ySGzqQ1PSY+rg9N\n\t hU2eUKozyIHqdXxHXrl8Lpq63LFmQq1dZ8JzOAGUUNMGPohrtc4BEaLDGN9dHEI8nQ\n\t NRLV7vepGWoCsHvD7y8chNJ1w9eBJ3W7bomSb/gi755SV7JhjaOO0MBqovBh1s66Sy\n\t dN0NEcdl25qDxCICsl7jYtGsx9QXeEBT1ulxisPrPVYTHLffH4ME/osMtabJ6N/GPV\n\t 14PC5kwKeHkT+bOAl7Ov7LS048uv0z5nQ6JDiBy3aijIkq+E06lh7kzzebq7Nwzg/7\n\t bbXf1MiOePmjA==", "From": "Ben Zong-You Xie via B4 Relay <devnull+ben717.andestech.com@kernel.org>", "Date": "Mon, 30 Mar 2026 15:45:43 +0800", "Subject": "[PATCH v5 1/3] dt-bindings: pwm: add support for AE350 PWM\n controller", "Precedence": "bulk", "X-Mailing-List": "linux-pwm@vger.kernel.org", "List-Id": "<linux-pwm.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pwm+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pwm+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260330-andes-pwm-v5-1-01c59a659d2c@andestech.com>", "References": "<20260330-andes-pwm-v5-0-01c59a659d2c@andestech.com>", "In-Reply-To": "<20260330-andes-pwm-v5-0-01c59a659d2c@andestech.com>", "To": "=?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, Ben Zong-You Xie <ben717@andestech.com>", "X-Mailer": "b4 0.15-dev-47773", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1774856744; l=2621;\n i=ben717@andestech.com; s=20260120; h=from:subject:message-id;\n bh=AlnVaPc7CqtbKonPziakNqedexQPh0xwvAlumniDgw0=;\n b=NQOyVYcjYUUSVeYI2PvV/eVJCV2abYR/Dv3E4X9Vto8KYnm3pmMWXddT4V6zIj4HtOCkXvEAa\n NMToDQFCh0GAnZYmD+QV3FoBoAgsGFan3Tu1QFNl8+MZ7LPrsT3tjN+", "X-Developer-Key": "i=ben717@andestech.com; a=ed25519;\n pk=nb8L7zQKGJpYk0yvrYKjViOZ34A36g1ZIsCmCsP518s=", "X-Endpoint-Received": "by B4 Relay for ben717@andestech.com/20260120 with\n auth_id=610", "X-Original-From": "Ben Zong-You Xie <ben717@andestech.com>", "Reply-To": "ben717@andestech.com" }, "content": "From: Ben Zong-You Xie <ben717@andestech.com>\n\nThe ATCPIT100 is a set of compact multi-function timers, which can be\nused as pulse width modulators (PWM) as well as simple timers.\nATCPIT100 supports up to 4 PIT channels, and each PIT channel may be\nconfigured as a simple timer or PWM, or a combination of the timer and\nthe PWM. This IP block is a core component of the Andes AE350 platform,\nwhich serves as a reference architecture for SoC designs. The QiLai SoC\nalso integrates this controller.\n\nThe binding introduces the following compatible strings:\n- \"andestech,qilai-pwm\": For the implementation integrated into the\n Andes QiLai SoC.\n- \"andestech,ae350-pwm\": As a fallback compatible string representing\n the base IP design used across the AE350 platform architecture.\n\nReviewed-by: Rob Herring (Arm) <robh@kernel.org>\nSigned-off-by: Ben Zong-You Xie <ben717@andestech.com>\n---\n .../bindings/pwm/andestech,ae350-pwm.yaml | 61 ++++++++++++++++++++++\n 1 file changed, 61 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml b/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml\nnew file mode 100644\nindex 000000000000..287f3c62965f\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml\n@@ -0,0 +1,61 @@\n+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pwm/andestech,ae350-pwm.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Andes PWM controller on AE350 platform\n+\n+description:\n+ This controller has 4 channels and two clock sources. Each channel can\n+ switch the clock source by programming the corresponding register.\n+\n+maintainers:\n+ - Ben Zong-You Xie <ben717@andestech.com>\n+\n+allOf:\n+ - $ref: pwm.yaml#\n+\n+properties:\n+ compatible:\n+ oneOf:\n+ - items:\n+ - enum:\n+ - andestech,qilai-pwm\n+ - const: andestech,ae350-pwm\n+ - const: andestech,ae350-pwm\n+\n+ reg:\n+ maxItems: 1\n+\n+ \"#pwm-cells\":\n+ const: 3\n+\n+ clocks:\n+ items:\n+ - description: APB bus clock\n+ - description: External clock\n+\n+ clock-names:\n+ items:\n+ - const: pclk\n+ - const: extclk\n+\n+required:\n+ - compatible\n+ - reg\n+ - \"#pwm-cells\"\n+ - clocks\n+ - clock-names\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ pwm@f0400000 {\n+ compatible = \"andestech,ae350-pwm\";\n+ reg = <0xf0400000 0x100000>;\n+ #pwm-cells = <3>;\n+ clocks = <&pclk>, <&extclk>;\n+ clock-names = \"pclk\", \"extclk\";\n+ };\n", "prefixes": [ "v5", "1/3" ] }