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GET /api/patches/2217548/?format=api
{ "id": 2217548, "url": "http://patchwork.ozlabs.org/api/patches/2217548/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20260330-irqchip-v4-4-3c0f1620cc06@aspeedtech.com/", "project": { "id": 57, "url": "http://patchwork.ozlabs.org/api/projects/57/?format=api", "name": "Linux ASPEED SoC development", "link_name": "linux-aspeed", "list_id": "linux-aspeed.lists.ozlabs.org", "list_email": "linux-aspeed@lists.ozlabs.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330-irqchip-v4-4-3c0f1620cc06@aspeedtech.com>", "list_archive_url": null, "date": "2026-03-30T06:32:13", "name": "[v4,4/4] irqchip/aspeed-intc: Remove AST2700-A0 support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8c252a00a3ad8b24b1470dd6a7e2dda3b7661364", "submitter": { "id": 71489, "url": "http://patchwork.ozlabs.org/api/people/71489/?format=api", "name": "Ryan Chen", "email": "ryan_chen@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20260330-irqchip-v4-4-3c0f1620cc06@aspeedtech.com/mbox/", "series": [ { "id": 497963, "url": "http://patchwork.ozlabs.org/api/series/497963/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/list/?series=497963", "date": "2026-03-30T06:32:10", "name": "AST2700-A2 interrupt controller hierarchy and route support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/497963/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217548/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217548/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-aspeed+bounces-3801-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; helo=lists.ozlabs.org;\n envelope-from=linux-aspeed+bounces-3801-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)", "lists.ozlabs.org;\n arc=none smtp.remote-ip=211.20.114.72", "lists.ozlabs.org;\n dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com", "lists.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com\n (client-ip=211.20.114.72; helo=twmbx01.aspeed.com;\n envelope-from=ryan_chen@aspeedtech.com; receiver=lists.ozlabs.org)" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org\n [IPv6:2404:9400:21b9:f100::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fkhJ43Yq6z1y1q\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 30 Mar 2026 17:32:36 +1100 (AEDT)", "from boromir.ozlabs.org (localhost [127.0.0.1])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4fkhJ32vqJz2ygf;\n\tMon, 30 Mar 2026 17:32:35 +1100 (AEDT)", "from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 4fkhJ23n7pz2xT6\n\tfor <linux-aspeed@lists.ozlabs.org>; Mon, 30 Mar 2026 17:32:34 +1100 (AEDT)", "from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 30 Mar\n 2026 14:32:11 +0800", "from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend\n Transport; Mon, 30 Mar 2026 14:32:11 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1774852355;\n\tcv=none;\n b=ZAh0MYlXJAv5VHY7/sH/iVK/wGRN1l61dRDEajfPLtLCMwqlM83hhYpvGwWStNyBFeTxyO6bpbnITRhjMmMIl108H+QHWyYm+Zf9m8VXlbA7Qdkf4yHtAXp+DMfF8My/sO9vphNxuc8nJy5VpaSeACuf8ivPMuPjF8iZ/z2npBQkSCculVZ+6S0fyl2JbvW9+RAXs2NZd0YMm1Y2ClW4evXQ9mcVDVU5yt31b8Xnr2VkUQKE5nSJqH6g53+mDMV87kt2ak6ij4wKMqXH6tY1yvOjMwEyABKQn7KUkvSb4QL2+3B/4IKbAoKik2Fik2XW4kY9TnpDrJAt55PeRvXoFA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707;\n\tt=1774852355; c=relaxed/relaxed;\n\tbh=D+c1qdcTxTsOTTYgUvUzO1k2tuphITL/5mx7UqECEuI=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References:\n\t In-Reply-To:To:CC;\n b=Ark6JRFwEFYIdQvMhJ4pNBhBDVWies7RHQuJu4trdnMlrdDbkxOCoqB1z5NF3NlcUOHjzpkjx7zx8fgLGLHEY6WYdyH55wXoPLiPUkRGAUt1uLqCd11tXfBBBOU4Yjf9JsDd/To0/me9yqmnk+t74oWkTSLk3zD6P40preWKFfrJEk5munD2/Lbis3qp829WMAj+J6uhM/MmK7PCReXbK5x9Zv7/GQUr7MaEC+QcM7DIYwuurF/4B4oejciQacaoZROFp5x3jLDca0GqTEhYZd4ImA9ovVCwHLBHaWT/2EufVcvgR8DqAxRViNvbubsmOLKvxx6s6oJeQBe8k8w1bg==", "ARC-Authentication-Results": "i=1; lists.ozlabs.org;\n dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com;\n spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeed.com;\n envelope-from=ryan_chen@aspeedtech.com;\n receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com", "From": "Ryan Chen <ryan_chen@aspeedtech.com>", "Date": "Mon, 30 Mar 2026 14:32:13 +0800", "Subject": "[PATCH v4 4/4] irqchip/aspeed-intc: Remove AST2700-A0 support", "X-Mailing-List": "linux-aspeed@lists.ozlabs.org", "List-Id": "<linux-aspeed.lists.ozlabs.org>", "List-Help": "<mailto:linux-aspeed+help@lists.ozlabs.org>", "List-Owner": "<mailto:linux-aspeed+owner@lists.ozlabs.org>", "List-Post": "<mailto:linux-aspeed@lists.ozlabs.org>", "List-Archive": "<https://lore.kernel.org/linux-aspeed/>,\n <https://lists.ozlabs.org/pipermail/linux-aspeed/>", "List-Subscribe": "<mailto:linux-aspeed+subscribe@lists.ozlabs.org>,\n <mailto:linux-aspeed+subscribe-digest@lists.ozlabs.org>,\n <mailto:linux-aspeed+subscribe-nomail@lists.ozlabs.org>", "List-Unsubscribe": "<mailto:linux-aspeed+unsubscribe@lists.ozlabs.org>", "Precedence": "list", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-ID": "<20260330-irqchip-v4-4-3c0f1620cc06@aspeedtech.com>", "References": "<20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com>", "In-Reply-To": "<20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com>", "To": "Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n\tConor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>, \"Andrew\n Jeffery\" <andrew@codeconstruct.com.au>, Paul Walmsley <pjw@kernel.org>,\n\t\"Palmer Dabbelt\" <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>,\n\t\"Alexandre Ghiti\" <alex@ghiti.fr>, Thomas Gleixner <tglx@kernel.org>, Thomas\n Gleixner <tglx@kernel.org>", "CC": "<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>, <linux-aspeed@lists.ozlabs.org>,\n\t<linux-riscv@lists.infradead.org>, Ryan Chen <ryan_chen@aspeedtech.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1774852330; l=5800;\n i=ryan_chen@aspeedtech.com; s=20251126; h=from:subject:message-id;\n bh=dDHK26Pv3om1nVVi9t4wNhYIZIKE7ffity4S2AcBKdE=;\n b=xcVlBcqWDoLrSv7zDQxLudTGqsYv9nGiPqMSGDAnUQk9iwdLNXt8pdbYnxcVyhlGGRtRLG9z2\n izzl076YyejAR3X4wsT0KVZMGmDQYcuQlguDA5651cJq9HXtaED4K81", "X-Developer-Key": "i=ryan_chen@aspeedtech.com; a=ed25519;\n pk=Xe73xY6tcnkuRjjbVAB/oU30KdB3FvG4nuJuILj7ZVc=", "X-Spam-Status": "No, score=0.0 required=5.0 tests=SPF_HELO_FAIL,SPF_PASS\n\tautolearn=disabled version=4.0.1", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org" }, "content": "The existing AST2700 interrupt controller driver\n(\"aspeed,ast2700-intc-ic\") was written against the A0 pre-production\ndesign.\n\nFrom A1 onwards (retained in the A2 production silicon), the interrupt\nfabric was re-architected: interrupt routing is programmable and\ninterrupt outputs can be directed to multiple upstream controllers\n(PSP GIC, Secondary Service Processor (SSP) NVIC, Tertiary Service\nProcessor (TSP) NVIC, and Boot MCU interrupt controller). This design\nrequires route resolution and a controller hierarchy model which the\nA0 driver cannot represent.\n\nRemove driver support for A0 in favour of the driver for the A2\nproduction design.\n\nSigned-off-by: Ryan Chen <ryan_chen@aspeedtech.com>\n---\n drivers/irqchip/Makefile | 1 -\n drivers/irqchip/irq-aspeed-intc.c | 139 --------------------------------------\n 2 files changed, 140 deletions(-)", "diff": "diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile\nindex ac04a4b97797..3d02441b3ee6 100644\n--- a/drivers/irqchip/Makefile\n+++ b/drivers/irqchip/Makefile\n@@ -92,7 +92,6 @@ obj-$(CONFIG_LS_SCFG_MSI)\t\t+= irq-ls-scfg-msi.o\n obj-$(CONFIG_ASPEED_AST2700_INTC)\t+= irq-ast2700.o irq-ast2700-intc0.o irq-ast2700-intc1.o\n obj-$(CONFIG_ASPEED_AST2700_INTC_TEST)\t+= irq-ast2700-intc0-test.o\n obj-$(CONFIG_ARCH_ASPEED)\t\t+= irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o\n-obj-$(CONFIG_ARCH_ASPEED)\t\t+= irq-aspeed-intc.o\n obj-$(CONFIG_STM32MP_EXTI)\t\t+= irq-stm32mp-exti.o\n obj-$(CONFIG_STM32_EXTI) \t\t+= irq-stm32-exti.o\n obj-$(CONFIG_QCOM_IRQ_COMBINER)\t\t+= qcom-irq-combiner.o\ndiff --git a/drivers/irqchip/irq-aspeed-intc.c b/drivers/irqchip/irq-aspeed-intc.c\ndeleted file mode 100644\nindex 4fb0dd8349da..000000000000\n--- a/drivers/irqchip/irq-aspeed-intc.c\n+++ /dev/null\n@@ -1,139 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Aspeed Interrupt Controller.\n- *\n- * Copyright (C) 2023 ASPEED Technology Inc.\n- */\n-\n-#include <linux/bitops.h>\n-#include <linux/irq.h>\n-#include <linux/irqchip.h>\n-#include <linux/irqchip/chained_irq.h>\n-#include <linux/irqdomain.h>\n-#include <linux/of_address.h>\n-#include <linux/of_irq.h>\n-#include <linux/io.h>\n-#include <linux/spinlock.h>\n-\n-#define INTC_INT_ENABLE_REG\t0x00\n-#define INTC_INT_STATUS_REG\t0x04\n-#define INTC_IRQS_PER_WORD\t32\n-\n-struct aspeed_intc_ic {\n-\tvoid __iomem\t\t*base;\n-\traw_spinlock_t\t\tgic_lock;\n-\traw_spinlock_t\t\tintc_lock;\n-\tstruct irq_domain\t*irq_domain;\n-};\n-\n-static void aspeed_intc_ic_irq_handler(struct irq_desc *desc)\n-{\n-\tstruct aspeed_intc_ic *intc_ic = irq_desc_get_handler_data(desc);\n-\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n-\n-\tchained_irq_enter(chip, desc);\n-\n-\tscoped_guard(raw_spinlock, &intc_ic->gic_lock) {\n-\t\tunsigned long bit, status;\n-\n-\t\tstatus = readl(intc_ic->base + INTC_INT_STATUS_REG);\n-\t\tfor_each_set_bit(bit, &status, INTC_IRQS_PER_WORD) {\n-\t\t\tgeneric_handle_domain_irq(intc_ic->irq_domain, bit);\n-\t\t\twritel(BIT(bit), intc_ic->base + INTC_INT_STATUS_REG);\n-\t\t}\n-\t}\n-\n-\tchained_irq_exit(chip, desc);\n-}\n-\n-static void aspeed_intc_irq_mask(struct irq_data *data)\n-{\n-\tstruct aspeed_intc_ic *intc_ic = irq_data_get_irq_chip_data(data);\n-\tunsigned int mask = readl(intc_ic->base + INTC_INT_ENABLE_REG) & ~BIT(data->hwirq);\n-\n-\tguard(raw_spinlock)(&intc_ic->intc_lock);\n-\twritel(mask, intc_ic->base + INTC_INT_ENABLE_REG);\n-}\n-\n-static void aspeed_intc_irq_unmask(struct irq_data *data)\n-{\n-\tstruct aspeed_intc_ic *intc_ic = irq_data_get_irq_chip_data(data);\n-\tunsigned int unmask = readl(intc_ic->base + INTC_INT_ENABLE_REG) | BIT(data->hwirq);\n-\n-\tguard(raw_spinlock)(&intc_ic->intc_lock);\n-\twritel(unmask, intc_ic->base + INTC_INT_ENABLE_REG);\n-}\n-\n-static struct irq_chip aspeed_intc_chip = {\n-\t.name\t\t\t= \"ASPEED INTC\",\n-\t.irq_mask\t\t= aspeed_intc_irq_mask,\n-\t.irq_unmask\t\t= aspeed_intc_irq_unmask,\n-};\n-\n-static int aspeed_intc_ic_map_irq_domain(struct irq_domain *domain, unsigned int irq,\n-\t\t\t\t\t irq_hw_number_t hwirq)\n-{\n-\tirq_set_chip_and_handler(irq, &aspeed_intc_chip, handle_level_irq);\n-\tirq_set_chip_data(irq, domain->host_data);\n-\n-\treturn 0;\n-}\n-\n-static const struct irq_domain_ops aspeed_intc_ic_irq_domain_ops = {\n-\t.map = aspeed_intc_ic_map_irq_domain,\n-};\n-\n-static int __init aspeed_intc_ic_of_init(struct device_node *node,\n-\t\t\t\t\t struct device_node *parent)\n-{\n-\tstruct aspeed_intc_ic *intc_ic;\n-\tint irq, i, ret = 0;\n-\n-\tintc_ic = kzalloc_obj(*intc_ic);\n-\tif (!intc_ic)\n-\t\treturn -ENOMEM;\n-\n-\tintc_ic->base = of_iomap(node, 0);\n-\tif (!intc_ic->base) {\n-\t\tpr_err(\"Failed to iomap intc_ic base\\n\");\n-\t\tret = -ENOMEM;\n-\t\tgoto err_free_ic;\n-\t}\n-\twritel(0xffffffff, intc_ic->base + INTC_INT_STATUS_REG);\n-\twritel(0x0, intc_ic->base + INTC_INT_ENABLE_REG);\n-\n-\tintc_ic->irq_domain = irq_domain_create_linear(of_fwnode_handle(node), INTC_IRQS_PER_WORD,\n-\t\t\t\t\t\t &aspeed_intc_ic_irq_domain_ops, intc_ic);\n-\tif (!intc_ic->irq_domain) {\n-\t\tret = -ENOMEM;\n-\t\tgoto err_iounmap;\n-\t}\n-\n-\traw_spin_lock_init(&intc_ic->gic_lock);\n-\traw_spin_lock_init(&intc_ic->intc_lock);\n-\n-\t/* Check all the irq numbers valid. If not, unmaps all the base and frees the data. */\n-\tfor (i = 0; i < of_irq_count(node); i++) {\n-\t\tirq = irq_of_parse_and_map(node, i);\n-\t\tif (!irq) {\n-\t\t\tpr_err(\"Failed to get irq number\\n\");\n-\t\t\tret = -EINVAL;\n-\t\t\tgoto err_iounmap;\n-\t\t}\n-\t}\n-\n-\tfor (i = 0; i < of_irq_count(node); i++) {\n-\t\tirq = irq_of_parse_and_map(node, i);\n-\t\tirq_set_chained_handler_and_data(irq, aspeed_intc_ic_irq_handler, intc_ic);\n-\t}\n-\n-\treturn 0;\n-\n-err_iounmap:\n-\tiounmap(intc_ic->base);\n-err_free_ic:\n-\tkfree(intc_ic);\n-\treturn ret;\n-}\n-\n-IRQCHIP_DECLARE(ast2700_intc_ic, \"aspeed,ast2700-intc-ic\", aspeed_intc_ic_of_init);\n", "prefixes": [ "v4", "4/4" ] }