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GET /api/patches/2217512/?format=api
{ "id": 2217512, "url": "http://patchwork.ozlabs.org/api/patches/2217512/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260330020934.3501247-1-ziyue.zhang@oss.qualcomm.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330020934.3501247-1-ziyue.zhang@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-03-30T02:09:34", "name": "[v2,1/1] arm64: dts: qcom: hamoa: Fix incomplete Root Port property migration", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3553137ad2420bcbb327b02b8098b2f06239a085", "submitter": { "id": 91191, "url": "http://patchwork.ozlabs.org/api/people/91191/?format=api", "name": "Ziyue Zhang", "email": "ziyue.zhang@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260330020934.3501247-1-ziyue.zhang@oss.qualcomm.com/mbox/", "series": [ { "id": 497944, "url": "http://patchwork.ozlabs.org/api/series/497944/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497944", "date": "2026-03-30T02:09:34", "name": "[v2,1/1] arm64: dts: qcom: hamoa: Fix incomplete Root Port property migration", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497944/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217512/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217512/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51403-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=mOHtsRE/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n\tcc:content-transfer-encoding:date:from:message-id:mime-version\n\t:subject:to; s=qcppdkim1; bh=U20/O7FgYWbVX6Icc/eYMwWZH+0hpW+d8RW\n\t7/eBPhSo=; b=mOHtsRE/3huQwSVPdvMm1CNAh5Sjo/MaBeXffrHLK4AZrHX5wOT\n\tS78E/qLg76usHnyu7SMrCXAo4hvi0cP/21FuBu3gXxBddDhayi+J6aT/gVcQg3V2\n\txhPHXgVyiQSftdJtTZNgX5LHZpBW22ck3wgX8Q4yAiYDhdEpRqwg8uw8IEaHdbfI\n\tJAPoTkfIiYIsVQRA2usoIjsREIWXNTUSAs6jkZhu6v8BA9CWSW50FfLSE6YgXBNf\n\t6aZq3NfAArQ3mMHYZ5gUBAebwO9q/iGfzIwxlcaQKBILNPzIMbapQ3+VSuWGFCSS\n\tt1jMrfiFS3tERuwuuhKe62pmQWOqUcKE1TQ==", "From": "Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>", "To": "andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org,\n krzk+dt@kernel.org, conor+dt@kernel.org, ziyue.zhang@oss.qualcomm.com,\n jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org,\n kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org,\n vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org,\n abel.vesa@linaro.org, kw@linux.com", "Cc": "linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com,\n quic_krichai@quicinc.com, quic_vbadigan@quicinc.com", "Subject": "[PATCH v2 1/1] arm64: dts: qcom: hamoa: Fix incomplete Root Port\n property migration", "Date": "Mon, 30 Mar 2026 10:09:34 +0800", "Message-ID": "<20260330020934.3501247-1-ziyue.zhang@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.43.0", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QCInternal": [ "smtphost", "smtphost" ], "X-Authority-Analysis": "v=2.4 cv=I8dohdgg c=1 sm=1 tr=0 ts=69c9db6d cx=c_pps\n a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17\n a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22\n a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=7D783TuBx9djJqFGgd4A:9", "X-Proofpoint-GUID": "xSGPe6w8x8W8ck63q69wFA7nWFHBUdC2", "X-Proofpoint-ORIG-GUID": "xSGPe6w8x8W8ck63q69wFA7nWFHBUdC2", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMzMwMDAxNCBTYWx0ZWRfXzBMN4ssi8hbZ\n S14UIsbpTMcnUjj23Em0QjUW37g5lxrc2+SfMiasauqLSRKA9BCSmeZLUiiKlsnvYaxvgaPX9iK\n xyN2bqtsy9QVNBPR1HcHhK64Ey2pTN6Ajc7h9J1PEHQAfJO2T0f0PhNkUqrIGGSjyFwMcB4qImg\n 212tgGwG7iXmj5FG1AlKc9Ozdh4x/CdFRGP0mAM4ikms1NDxDBkH5ysZrGMeA2sOFbsmPYHvKw3\n gkXJhuUS9jYCBQ4NWLYEohsa9yc8vpqa/PDGVPo2Sm1obvl5raFIhVl/x47k2lr0GEhZr+KhBos\n QYsPSXKH4Mv71yNi5kkAg5ASxuAwYdfeheKEfdAm0gFOSIe+g9FzTBZBg8zWgS9Vi8NjDtwygOf\n mx+p7Deeroif4+1pH4xVjKis1+ETLUFYrmibHOqNvKP1WXBbbEVJ5/4myL0K0JGCiyW6HTom4fH\n 5w/fpaSgF6U0icPmzlQ==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-03-29_05,2026-03-28_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 suspectscore=0\n malwarescore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 phishscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603300014" }, "content": "Historically, the Qualcomm PCIe controller node (Host bridge) described\nall Root Port properties, such as PHY, PERST#, and WAKE#. But to provide\na more accurate hardware description and to support future multi-Root Port\ncontrollers, these properties were moved to the Root Port node in the\ndevicetree bindings.\n\nCommit 960609b22be5 (\"arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake\nGPIOs to PCIe port nodes and add port Nodes for all PCIe ports\")\ninitiated this transition for the Hamoa platform by moving the PHY\nproperty to the Root Port node in hamoa.dtsi. However, it only updated\nsome platform specific DTS files for PERST# and WAKE#, leaving others in\na \"mixed\" binding state.\n\nWhile the PCIe controller driver supports both legacy and Root Port\nbindings, It cannot correctly handle a mix of both. In these cases, the\ndriver parses the PHY from the Root Port node, but fails to find the\nPERST# property (which it then assumes is not present, as it is optional).\nConsequently, the controller probe succeeds, but PERST# remains\nuncontrolled, preventing PCIe endpoints from functioning.\n\nSo, fix the incomplete migration by moving the PERST# and WAKE# properties\nfrom the controller node to the Root Port node in all remaining Hamoa\nplatform DTS files.\n\nFixes: 960609b22be5 (\"arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake GPIOs to PCIe port nodes and add port Nodes for all PCIe ports\")\nSigned-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>\n---\n .../boot/dts/qcom/x1-asus-zenbook-a14.dtsi | 16 ++++++++-----\n arch/arm64/boot/dts/qcom/x1-crd.dtsi | 24 ++++++++++++-------\n arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi | 14 ++++++-----\n .../boot/dts/qcom/x1-hp-omnibook-x14.dtsi | 14 ++++++-----\n .../boot/dts/qcom/x1-microsoft-denali.dtsi | 8 ++++---\n .../dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 6 ++---\n .../qcom/x1e80100-medion-sprchrgd-14-s1.dts | 14 +++++------\n .../dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 14 ++++++-----\n 8 files changed, 64 insertions(+), 46 deletions(-)", "diff": "diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi\nindex cd062f844b2d..66d566808f58 100644\n--- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi\n+++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi\n@@ -1079,9 +1079,6 @@ &mdss_dp3_phy {\n };\n \n &pcie4 {\n-\tperst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n-\n \tpinctrl-0 = <&pcie4_default>;\n \tpinctrl-names = \"default\";\n \n@@ -1095,10 +1092,12 @@ &pcie4_phy {\n \tstatus = \"okay\";\n };\n \n-&pcie6a {\n-\tperst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n+&pcie4_port0 {\n+\treset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n+};\n \n+&pcie6a {\n \tvddpe-3v3-supply = <&vreg_nvme>;\n \n \tpinctrl-0 = <&pcie6a_default>;\n@@ -1114,6 +1113,11 @@ &pcie6a_phy {\n \tstatus = \"okay\";\n };\n \n+&pcie6a_port0 {\n+\treset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n+};\n+\n &pm8550_gpios {\n \trtmr0_default: rtmr0-reset-n-active-state {\n \t\tpins = \"gpio10\";\ndiff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi\nindex 485dcd946757..a9c5c523575e 100644\n--- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi\n+++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi\n@@ -1248,15 +1248,17 @@ &mdss_dp3_phy {\n };\n \n &pcie4 {\n-\tperst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n-\n \tpinctrl-0 = <&pcie4_default>;\n \tpinctrl-names = \"default\";\n \n \tstatus = \"okay\";\n };\n \n+&pcie4_port0 {\n+\treset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n+};\n+\n &pcie4_phy {\n \tvdda-phy-supply = <&vreg_l3i_0p8>;\n \tvdda-pll-supply = <&vreg_l3e_1p2>;\n@@ -1265,9 +1267,6 @@ &pcie4_phy {\n };\n \n &pcie5 {\n-\tperst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;\n-\n \tvddpe-3v3-supply = <&vreg_wwan>;\n \n \tpinctrl-0 = <&pcie5_default>;\n@@ -1283,10 +1282,12 @@ &pcie5_phy {\n \tstatus = \"okay\";\n };\n \n-&pcie6a {\n-\tperst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n+&pcie5_port0 {\n+\treset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;\n+};\n \n+&pcie6a {\n \tvddpe-3v3-supply = <&vreg_nvme>;\n \n \tpinctrl-names = \"default\";\n@@ -1302,6 +1303,11 @@ &pcie6a_phy {\n \tstatus = \"okay\";\n };\n \n+&pcie6a_port0 {\n+\treset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n+};\n+\n &pm8550_gpios {\n \tkypd_vol_up_n: kypd-vol-up-n-state {\n \t\tpins = \"gpio6\";\ndiff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi\nindex 343844cc62f2..0d9a324cc6cc 100644\n--- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi\n+++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi\n@@ -1081,9 +1081,6 @@ &mdss_dp3_phy {\n };\n \n &pcie4 {\n-\tperst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n-\n \tpinctrl-0 = <&pcie4_default>;\n \tpinctrl-names = \"default\";\n \n@@ -1098,6 +1095,9 @@ &pcie4_phy {\n };\n \n &pcie4_port0 {\n+\treset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n+\n \twifi@0 {\n \t\tcompatible = \"pci17cb,1107\";\n \t\treg = <0x10000 0x0 0x0 0x0 0x0>;\n@@ -1115,9 +1115,6 @@ wifi@0 {\n };\n \n &pcie6a {\n-\tperst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n-\n \tvddpe-3v3-supply = <&vreg_nvme>;\n \n \tpinctrl-0 = <&pcie6a_default>;\n@@ -1126,6 +1123,11 @@ &pcie6a {\n \tstatus = \"okay\";\n };\n \n+&pcie6a_port0 {\n+\treset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n+};\n+\n &pcie6a_phy {\n \tvdda-phy-supply = <&vreg_l1d_0p8>;\n \tvdda-pll-supply = <&vreg_l2j_1p2>;\ndiff --git a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi\nindex 16437139d336..b773a4976d1b 100644\n--- a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi\n+++ b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi\n@@ -1065,9 +1065,6 @@ &mdss_dp3_phy {\n };\n \n &pcie4 {\n-\tperst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n-\n \tpinctrl-0 = <&pcie4_default>;\n \tpinctrl-names = \"default\";\n \n@@ -1082,6 +1079,9 @@ &pcie4_phy {\n };\n \n &pcie4_port0 {\n+\treset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n+\n \twifi@0 {\n \t\tcompatible = \"pci17cb,1107\";\n \t\treg = <0x10000 0x0 0x0 0x0 0x0>;\n@@ -1099,9 +1099,6 @@ wifi@0 {\n };\n \n &pcie6a {\n-\tperst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n-\n \tvddpe-3v3-supply = <&vreg_nvme>;\n \n \tpinctrl-0 = <&pcie6a_default>;\n@@ -1110,6 +1107,11 @@ &pcie6a {\n \tstatus = \"okay\";\n };\n \n+&pcie6a_port0 {\n+\treset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n+};\n+\n &pcie6a_phy {\n \tvdda-phy-supply = <&vreg_l1d_0p8>;\n \tvdda-pll-supply = <&vreg_l2j_1p2>;\ndiff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi\nindex 6ab595b6ea30..dd2de1f723b0 100644\n--- a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi\n+++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi\n@@ -964,9 +964,6 @@ wifi@0 {\n };\n \n &pcie6a {\n-\tperst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n-\n \tvddpe-3v3-supply = <&vreg_nvme>;\n \n \tpinctrl-0 = <&pcie6a_default>;\n@@ -982,6 +979,11 @@ &pcie6a_phy {\n \tstatus = \"okay\";\n };\n \n+&pcie6a_port0 {\n+\treset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n+};\n+\n &pm8550_gpios {\n \trtmr0_default: rtmr0-reset-n-active-state {\n \t\tpins = \"gpio10\";\ndiff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts\nindex bd0e3009fb41..beb1475d7fa0 100644\n--- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts\n+++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts\n@@ -1126,9 +1126,6 @@ &mdss_dp3_phy {\n };\n \n &pcie4 {\n-\tperst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n-\n \tpinctrl-0 = <&pcie4_default>;\n \tpinctrl-names = \"default\";\n \n@@ -1143,6 +1140,9 @@ &pcie4_phy {\n };\n \n &pcie4_port0 {\n+\treset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n+\n \twifi@0 {\n \t\tcompatible = \"pci17cb,1107\";\n \t\treg = <0x10000 0x0 0x0 0x0 0x0>;\ndiff --git a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts\nindex 763efb9e070d..23a298248a29 100644\n--- a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts\n+++ b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts\n@@ -1033,9 +1033,6 @@ &mdss_dp3_phy {\n };\n \n &pcie4 {\n-\tperst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n-\n \tpinctrl-0 = <&pcie4_default>;\n \tpinctrl-names = \"default\";\n \n@@ -1050,6 +1047,8 @@ &pcie4_phy {\n };\n \n &pcie4_port0 {\n+\treset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n \twifi@0 {\n \t\tcompatible = \"pci17cb,1107\";\n \t\treg = <0x10000 0x0 0x0 0x0 0x0>;\n@@ -1067,10 +1066,6 @@ wifi@0 {\n };\n \n &pcie6a {\n-\tperst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n-\n-\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n-\n \tvddpe-3v3-supply = <&vreg_nvme>;\n \n \tpinctrl-0 = <&pcie6a_default>;\n@@ -1086,6 +1081,11 @@ &pcie6a_phy {\n \tstatus = \"okay\";\n };\n \n+&pcie6a_port0 {\n+\treset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n+};\n+\n &pm8550_gpios {\n \trtmr0_default: rtmr0-reset-n-active-state {\n \t\tpins = \"gpio10\";\ndiff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts\nindex ab309d547ed5..500809772097 100644\n--- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts\n+++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts\n@@ -1131,9 +1131,6 @@ &mdss_dp3_phy {\n };\n \n &pcie4 {\n-\tperst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n-\n \tpinctrl-0 = <&pcie4_default>;\n \tpinctrl-names = \"default\";\n \n@@ -1148,6 +1145,9 @@ &pcie4_phy {\n };\n \n &pcie4_port0 {\n+\treset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;\n+\n \twifi@0 {\n \t\tcompatible = \"pci17cb,1107\";\n \t\treg = <0x10000 0x0 0x0 0x0 0x0>;\n@@ -1165,9 +1165,6 @@ wifi@0 {\n };\n \n &pcie6a {\n-\tperst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n-\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n-\n \tvddpe-3v3-supply = <&vreg_nvme>;\n \n \tpinctrl-0 = <&pcie6a_default>;\n@@ -1183,6 +1180,11 @@ &pcie6a_phy {\n \tstatus = \"okay\";\n };\n \n+&pcie6a_port0 {\n+\treset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;\n+\twake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;\n+};\n+\n &pm8550_pwm {\n \tstatus = \"okay\";\n };\n", "prefixes": [ "v2", "1/1" ] }