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GET /api/patches/2217509/?format=api
{ "id": 2217509, "url": "http://patchwork.ozlabs.org/api/patches/2217509/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260329231754.2325557-2-vineet.gupta@linux.dev/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260329231754.2325557-2-vineet.gupta@linux.dev>", "list_archive_url": null, "date": "2026-03-29T23:17:52", "name": "[1/3] bpf: md: Enable zero_extend{hi, qi}di2 to generate wN regs ...", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d2b753a88258018fea85fde9ba5f957931e1ab98", "submitter": { "id": 82303, "url": "http://patchwork.ozlabs.org/api/people/82303/?format=api", "name": "Vineet Gupta", "email": "vineet.gupta@linux.dev" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260329231754.2325557-2-vineet.gupta@linux.dev/mbox/", "series": [ { "id": 497942, "url": "http://patchwork.ozlabs.org/api/series/497942/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=497942", "date": "2026-03-29T23:17:51", "name": "bpf: Enable wN reg codegen for bug-fix and fun", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497942/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217509/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217509/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=linux.dev header.i=@linux.dev header.a=rsa-sha256\n header.s=key1 header.b=ik6gnZNk;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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Sun, 29 Mar 2026 23:20:14 +0000 (GMT)", "from out-170.mta1.migadu.com (out-170.mta1.migadu.com\n [95.215.58.170])\n by sourceware.org (Postfix) with ESMTPS id BB6C84BA23E5\n for <gcc-patches@gcc.gnu.org>; Sun, 29 Mar 2026 23:18:16 +0000 (GMT)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org D0DDA4BA23CB", "OpenDKIM Filter v2.11.0 sourceware.org BB6C84BA23E5" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org BB6C84BA23E5", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org BB6C84BA23E5", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1774826296; cv=none;\n b=ULFdGQcd1xa8F1rn1aI5ag8+yAQfDmC2AzZmWXarmAaauoIGOuRRnk9ULxq1r7vMznnszrTMHxSRz00wDzUbyGX5+dW2ITm2P73RI9sVoE1+d7ZUSjqaXAmLhBLDG30CD4bbp0KZhvRoVzYE32hK02sCli8i3uPS/9X3fwmp+LU=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1774826296; c=relaxed/simple;\n bh=bVQHD0kT6Nah09BJqpuFnPUoa4z9kuAuedsjH8sUtK4=;\n h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version;\n b=Ts5RuOp7e8gElV9TV8YguDX0Cm5uYnpwIYUPTxtW9K1UD3uFXsNPTUInOiyxFZnD1fddVORyaGUQLRJ9VK2alLKI6iE0cJSBd2LbM671502LJx6xQWWjARhfD/MdBTU+0oTO7gmz+eLEQNU3Sc0mdwcRCjTZEXvCc+nC3A4k1IA=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "X-Report-Abuse": "Please report any abuse attempt to abuse@migadu.com and\n include these headers.", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1;\n t=1774826294;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=UqQaxvYI6GVhWsWm8lKtteXS3cPKTKgZKFDh49/mNDs=;\n b=ik6gnZNkaPHe+/VE2v1oId0toaHHCW7LxmfrJOpHDMN+oiZ6FmO1oo3UgFlsEv2bv33ESD\n l4Q1oJkD6mPiy8Un4BNH34i9TAvLLCeTA/DmpKEgkbyqC388dfH4FPCiEmcnOYvP0Xumls\n n7lwEhiKrML+yYXs/v0OAs4lV6gX414=", "From": "Vineet Gupta <vineet.gupta@linux.dev>", "To": "bpf@gcc.gnu.org", "Cc": "gcc-patches@gcc.gnu.org, jose.marchesi@oracle.com, ast@kernel.org,\n Eduard Zingerman <eddyz87@gmail.com>,\n Yonghong Song <yonghong.song@linux.dev>,\n Vineet Gupta <vineet.gupta@linux.dev>", "Subject": "[PATCH 1/3] bpf: md: Enable zero_extend{hi,\n qi}di2 to generate wN regs ...", "Date": "Sun, 29 Mar 2026 16:17:52 -0700", "Message-ID": "<20260329231754.2325557-2-vineet.gupta@linux.dev>", "In-Reply-To": "<20260329231754.2325557-1-vineet.gupta@linux.dev>", "References": "<20260329231754.2325557-1-vineet.gupta@linux.dev>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Migadu-Flow": "FLOW_OUT", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "... by adjusting the asm template reg string to 'W', similar to commit\ngbd275e81812c for zero_extendsidi2. However unike that change, this is\nnot a bug fix: zero_extendsidi2 relies on wN reg move to achieve the\n32->64 semantics. A {8,16}->64 extension needs to be emulated anyways\nby masking out extra bits so the reg used is not imp.\n\nHowever wN reg based codegen is still preferable in general:\n - It is easier on verifier as it has to track fewer bits and avoids\n corner cases which could trip it up for false positives.\n - Better native codegen as upper bits are guarateed to be zero and can\n leverage target ISA mechanisms to achieve that mostly for free.\n - Better nativ codegen on 32-bit targets which need to use 2 regs for\n rN regs.\n\ngcc/ChangeLog:\n\n\t* config/bpf/bpf.md (zero_extendhidi2): Add alternates for\n\talu32 and use 'W' for reg operands.\n\t(zero_extendqidi2): Ditto.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/bpf/zero-ext.c: Add tests for {HI,QI}mode values.\n\nSigned-off-by: Vineet Gupta <vineet.gupta@linux.dev>\n---\n gcc/config/bpf/bpf.md | 8 ++++----\n gcc/testsuite/gcc.target/bpf/zero-ext.c | 16 ++++++++++++++++\n 2 files changed, 20 insertions(+), 4 deletions(-)", "diff": "diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md\nindex c2c3152b5d7c..a2bceb8998d7 100644\n--- a/gcc/config/bpf/bpf.md\n+++ b/gcc/config/bpf/bpf.md\n@@ -279,8 +279,8 @@\n \t(zero_extend:DI (match_operand:HI 1 \"nonimmediate_operand\" \"0,r,q\")))]\n \"\"\n \"@\n- {and\\t%0,0xffff|%0 &= 0xffff}\n- *return bpf_output_move (operands, \\\"{mov\\t%0,%1\\;and\\t%0,0xffff|%0 = %1;%0 &= 0xffff}\\\");\n+ *return bpf_has_alu32 ? \\\"{and32\\t%0,0xffff|%W0 &= 0xffff}\\\" : \\\"{and\\t%0,0xffff|%0 &= 0xffff}\\\";\n+ *return bpf_output_move (operands, bpf_has_alu32 ? \\\"{mov\\t%0,%1\\;and\\t%0,0xffff|%W0 = %W1;%W0 &= 0xffff}\\\" : \\\"{mov\\t%0,%1\\;and\\t%0,0xffff|%0 = %1;%0 &= 0xffff}\\\");\n *return bpf_output_move (operands, \\\"{ldxh\\t%0,%1|%0 = *(u16 *) %1}\\\");\"\n [(set_attr \"type\" \"alu,alu,ldx\")])\n \n@@ -289,8 +289,8 @@\n \t(zero_extend:DI (match_operand:QI 1 \"nonimmediate_operand\" \"0,r,q\")))]\n \"\"\n \"@\n- {and\\t%0,0xff|%0 &= 0xff}\n- *return bpf_output_move (operands, \\\"{mov\\t%0,%1\\;and\\t%0,0xff|%0 = %1;%0 &= 0xff}\\\");\n+ *return bpf_has_alu32 ? \\\"{and32\\t%0,0xff|%W0 &= 0xff}\\\" : \\\"{and\\t%0,0xff|%0 &= 0xff}\\\";\n+ *return bpf_output_move (operands, bpf_has_alu32 ? \\\"{mov\\t%0,%1\\;and\\t%0,0xff|%W0 = %W1;%W0 &= 0xff}\\\" : \\\"{mov\\t%0,%1\\;and\\t%0,0xff|%0 = %1;%0 &= 0xff}\\\");\n *return bpf_output_move (operands, \\\"{ldxb\\t%0,%1|%0 = *(u8 *) %1}\\\");\"\n [(set_attr \"type\" \"alu,alu,ldx\")])\n \ndiff --git a/gcc/testsuite/gcc.target/bpf/zero-ext.c b/gcc/testsuite/gcc.target/bpf/zero-ext.c\nindex a57c7dc521f0..b6ab7dab8bc0 100644\n--- a/gcc/testsuite/gcc.target/bpf/zero-ext.c\n+++ b/gcc/testsuite/gcc.target/bpf/zero-ext.c\n@@ -2,6 +2,8 @@\n /* { dg-options \"-O2 -mcpu=v4\" } */\n \n int bar_int(void);\n+short bar_short(void);\n+_Bool bar_bool(void);\n \n int foo_int(void) {\n if (bar_int() != 1) return 0; else return 1;\n@@ -9,3 +11,17 @@ int foo_int(void) {\n \n /* { dg-final { scan-assembler-not {r0 = r0} } } */\n /* { dg-final { scan-assembler-times {w0 = w0} 1 } } */\n+\n+int trigger_zext_hidi(void) {\n+ if (bar_short() != 1) return 0; else return 1;\n+}\n+\n+/* { dg-final { scan-assembler-not {r0 &= 0xffff} } } */\n+/* { dg-final { scan-assembler-times {w0 &= 0xffff} 1 } } */\n+\n+int trigger_zext_qidi(void) {\n+ if (bar_bool() != 0) return 0; else return 1;\n+}\n+\n+/* { dg-final { scan-assembler-not {r0 &= 0xff\\n} } } */\n+/* { dg-final { scan-assembler-times {w0 &= 0xff\\n} 1 } } */\n", "prefixes": [ "1/3" ] }