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GET /api/patches/2217418/?format=api
{ "id": 2217418, "url": "http://patchwork.ozlabs.org/api/patches/2217418/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260328170913.3673-1-tanyaagarwal25699@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260328170913.3673-1-tanyaagarwal25699@gmail.com>", "list_archive_url": null, "date": "2026-03-28T17:09:14", "name": "target: convert TABS indentation to spaces for consistency", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "901ede59ea353b6b70c201240761ab9157d63eea", "submitter": { "id": 92998, "url": "http://patchwork.ozlabs.org/api/people/92998/?format=api", "name": "Tanya Agarwal", "email": "tanyaagarwal25699@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260328170913.3673-1-tanyaagarwal25699@gmail.com/mbox/", "series": [ { "id": 497885, "url": "http://patchwork.ozlabs.org/api/series/497885/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497885", "date": "2026-03-28T17:09:14", "name": "target: convert TABS indentation to spaces for consistency", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497885/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217418/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217418/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n 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"X-Received": "by 2002:a17:903:19d0:b0:2b0:afb4:7d41 with SMTP id\n d9443c01a7336-2b0cdc02e54mr73581625ad.10.1774717792102;\n Sat, 28 Mar 2026 10:09:52 -0700 (PDT)", "From": "Tanya Agarwal <tanyaagarwal25699@gmail.com>", "X-Google-Original-From": "Tanya Agarwal <tanyaagarwal25699@gmail.com", "To": "richard.henderson@linaro.org, pbonzini@redhat.com, zhao1.liu@intel.com,\n edgar.iglesias@gmail.com, mark.cave-ayland@ilande.co.uk,\n atar4qemu@gmail.com", "Cc": "qemu-devel@nongnu.org, thuth@redhat.com, peter.maydell@linaro.org,\n Tanya Agarwal <tanyaagarwal25699@gmail.com>", "Subject": "[PATCH] target: convert TABS indentation to spaces for consistency", "Date": "Sat, 28 Mar 2026 22:39:14 +0530", "Message-Id": "<20260328170913.3673-1-tanyaagarwal25699@gmail.com>", "X-Mailer": "git-send-email 2.39.5", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::636;\n envelope-from=tanyaagarwal25699@gmail.com; helo=mail-pl1-x636.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Sat, 28 Mar 2026 13:37:22 -0400", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Tanya Agarwal <tanyaagarwal25699@gmail.com>\n\nTo follow consistent coding style, convert TABS indentation to spaces\nfor consistency.\n\nResolves: https://gitlab.com/qemu-project/qemu/-/work_items/372\n\nSigned-off-by: Tanya Agarwal <tanyaagarwal25699@gmail.com>\n---\n target/alpha/cpu.h | 6 +-\n target/i386/cpu.h | 40 ++---\n target/i386/svm.h | 308 ++++++++++++++++++-------------------\n target/microblaze/cpu.h | 12 +-\n target/sparc/asi.h | 328 ++++++++++++++++++++--------------------\n 5 files changed, 347 insertions(+), 347 deletions(-)", "diff": "diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h\nindex 45944e46b5..b530cd0088 100644\n--- a/target/alpha/cpu.h\n+++ b/target/alpha/cpu.h\n@@ -311,9 +311,9 @@ enum {\n };\n \n /* Alpha-specific interrupt pending bits. */\n-#define CPU_INTERRUPT_TIMER\tCPU_INTERRUPT_TGT_EXT_0\n-#define CPU_INTERRUPT_SMP\tCPU_INTERRUPT_TGT_EXT_1\n-#define CPU_INTERRUPT_MCHK\tCPU_INTERRUPT_TGT_EXT_2\n+#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0\n+#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1\n+#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2\n \n /* OSF/1 Page table bits. */\n enum {\ndiff --git a/target/i386/cpu.h b/target/i386/cpu.h\nindex 0b539155c4..a09d5de121 100644\n--- a/target/i386/cpu.h\n+++ b/target/i386/cpu.h\n@@ -417,12 +417,12 @@ typedef enum X86Seg {\n #define MSR_IA32_CORE_CAPABILITY 0xcf\n \n #define MSR_IA32_ARCH_CAPABILITIES 0x10a\n-#define ARCH_CAP_TSX_CTRL_MSR\t\t(1<<7)\n+#define ARCH_CAP_TSX_CTRL_MSR (1 << 7)\n \n #define MSR_IA32_PERF_CAPABILITIES 0x345\n #define PERF_CAP_LBR_FMT 0x3f\n \n-#define MSR_IA32_TSX_CTRL\t\t0x122\n+#define MSR_IA32_TSX_CTRL 0x122\n #define MSR_IA32_TSCDEADLINE 0x6e0\n #define MSR_IA32_PKRS 0x6e1\n #define MSR_RAPL_POWER_UNIT 0x00000606\n@@ -1482,24 +1482,24 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);\n #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF\n #endif\n \n-#define EXCP00_DIVZ\t0\n-#define EXCP01_DB\t1\n-#define EXCP02_NMI\t2\n-#define EXCP03_INT3\t3\n-#define EXCP04_INTO\t4\n-#define EXCP05_BOUND\t5\n-#define EXCP06_ILLOP\t6\n-#define EXCP07_PREX\t7\n-#define EXCP08_DBLE\t8\n-#define EXCP09_XERR\t9\n-#define EXCP0A_TSS\t10\n-#define EXCP0B_NOSEG\t11\n-#define EXCP0C_STACK\t12\n-#define EXCP0D_GPF\t13\n-#define EXCP0E_PAGE\t14\n-#define EXCP10_COPR\t16\n-#define EXCP11_ALGN\t17\n-#define EXCP12_MCHK\t18\n+#define EXCP00_DIVZ 0\n+#define EXCP01_DB 1\n+#define EXCP02_NMI 2\n+#define EXCP03_INT3 3\n+#define EXCP04_INTO 4\n+#define EXCP05_BOUND 5\n+#define EXCP06_ILLOP 6\n+#define EXCP07_PREX 7\n+#define EXCP08_DBLE 8\n+#define EXCP09_XERR 9\n+#define EXCP0A_TSS 10\n+#define EXCP0B_NOSEG 11\n+#define EXCP0C_STACK 12\n+#define EXCP0D_GPF 13\n+#define EXCP0E_PAGE 14\n+#define EXCP10_COPR 16\n+#define EXCP11_ALGN 17\n+#define EXCP12_MCHK 18\n \n #define EXCP_VMEXIT 0x100 /* only for system emulation */\n #define EXCP_SYSCALL 0x101 /* only for user emulation */\ndiff --git a/target/i386/svm.h b/target/i386/svm.h\nindex 1bd7844730..23c36637d4 100644\n--- a/target/i386/svm.h\n+++ b/target/i386/svm.h\n@@ -54,88 +54,88 @@\n \n #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK\n \n-#define\tSVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR\n-#define\tSVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI\n-#define\tSVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT\n-#define\tSVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT\n+#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR\n+#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI\n+#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT\n+#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT\n \n #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID\n #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR\n \n-#define\tSVM_EXIT_READ_CR0 \t0x000\n-#define\tSVM_EXIT_READ_CR3 \t0x003\n-#define\tSVM_EXIT_READ_CR4 \t0x004\n-#define\tSVM_EXIT_READ_CR8 \t0x008\n-#define\tSVM_EXIT_WRITE_CR0 \t0x010\n-#define\tSVM_EXIT_WRITE_CR3 \t0x013\n-#define\tSVM_EXIT_WRITE_CR4 \t0x014\n-#define\tSVM_EXIT_WRITE_CR8 \t0x018\n-#define\tSVM_EXIT_READ_DR0 \t0x020\n-#define\tSVM_EXIT_READ_DR1 \t0x021\n-#define\tSVM_EXIT_READ_DR2 \t0x022\n-#define\tSVM_EXIT_READ_DR3 \t0x023\n-#define\tSVM_EXIT_READ_DR4 \t0x024\n-#define\tSVM_EXIT_READ_DR5 \t0x025\n-#define\tSVM_EXIT_READ_DR6 \t0x026\n-#define\tSVM_EXIT_READ_DR7 \t0x027\n-#define\tSVM_EXIT_WRITE_DR0 \t0x030\n-#define\tSVM_EXIT_WRITE_DR1 \t0x031\n-#define\tSVM_EXIT_WRITE_DR2 \t0x032\n-#define\tSVM_EXIT_WRITE_DR3 \t0x033\n-#define\tSVM_EXIT_WRITE_DR4 \t0x034\n-#define\tSVM_EXIT_WRITE_DR5 \t0x035\n-#define\tSVM_EXIT_WRITE_DR6 \t0x036\n-#define\tSVM_EXIT_WRITE_DR7 \t0x037\n+#define SVM_EXIT_READ_CR0 0x000\n+#define SVM_EXIT_READ_CR3 0x003\n+#define SVM_EXIT_READ_CR4 0x004\n+#define SVM_EXIT_READ_CR8 0x008\n+#define SVM_EXIT_WRITE_CR0 0x010\n+#define SVM_EXIT_WRITE_CR3 0x013\n+#define SVM_EXIT_WRITE_CR4 0x014\n+#define SVM_EXIT_WRITE_CR8 0x018\n+#define SVM_EXIT_READ_DR0 0x020\n+#define SVM_EXIT_READ_DR1 0x021\n+#define SVM_EXIT_READ_DR2 0x022\n+#define SVM_EXIT_READ_DR3 0x023\n+#define SVM_EXIT_READ_DR4 0x024\n+#define SVM_EXIT_READ_DR5 0x025\n+#define SVM_EXIT_READ_DR6 0x026\n+#define SVM_EXIT_READ_DR7 0x027\n+#define SVM_EXIT_WRITE_DR0 0x030\n+#define SVM_EXIT_WRITE_DR1 0x031\n+#define SVM_EXIT_WRITE_DR2 0x032\n+#define SVM_EXIT_WRITE_DR3 0x033\n+#define SVM_EXIT_WRITE_DR4 0x034\n+#define SVM_EXIT_WRITE_DR5 0x035\n+#define SVM_EXIT_WRITE_DR6 0x036\n+#define SVM_EXIT_WRITE_DR7 0x037\n #define SVM_EXIT_EXCP_BASE 0x040\n-#define SVM_EXIT_INTR\t\t0x060\n-#define SVM_EXIT_NMI\t\t0x061\n-#define SVM_EXIT_SMI\t\t0x062\n-#define SVM_EXIT_INIT\t\t0x063\n-#define SVM_EXIT_VINTR\t\t0x064\n-#define SVM_EXIT_CR0_SEL_WRITE\t0x065\n-#define SVM_EXIT_IDTR_READ\t0x066\n-#define SVM_EXIT_GDTR_READ\t0x067\n-#define SVM_EXIT_LDTR_READ\t0x068\n-#define SVM_EXIT_TR_READ\t0x069\n-#define SVM_EXIT_IDTR_WRITE\t0x06a\n-#define SVM_EXIT_GDTR_WRITE\t0x06b\n-#define SVM_EXIT_LDTR_WRITE\t0x06c\n-#define SVM_EXIT_TR_WRITE\t0x06d\n-#define SVM_EXIT_RDTSC\t\t0x06e\n-#define SVM_EXIT_RDPMC\t\t0x06f\n-#define SVM_EXIT_PUSHF\t\t0x070\n-#define SVM_EXIT_POPF\t\t0x071\n-#define SVM_EXIT_CPUID\t\t0x072\n-#define SVM_EXIT_RSM\t\t0x073\n-#define SVM_EXIT_IRET\t\t0x074\n-#define SVM_EXIT_SWINT\t\t0x075\n-#define SVM_EXIT_INVD\t\t0x076\n-#define SVM_EXIT_PAUSE\t\t0x077\n-#define SVM_EXIT_HLT\t\t0x078\n-#define SVM_EXIT_INVLPG\t\t0x079\n-#define SVM_EXIT_INVLPGA\t0x07a\n-#define SVM_EXIT_IOIO\t\t0x07b\n-#define SVM_EXIT_MSR\t\t0x07c\n-#define SVM_EXIT_TASK_SWITCH\t0x07d\n-#define SVM_EXIT_FERR_FREEZE\t0x07e\n-#define SVM_EXIT_SHUTDOWN\t0x07f\n-#define SVM_EXIT_VMRUN\t\t0x080\n-#define SVM_EXIT_VMMCALL\t0x081\n-#define SVM_EXIT_VMLOAD\t\t0x082\n-#define SVM_EXIT_VMSAVE\t\t0x083\n-#define SVM_EXIT_STGI\t\t0x084\n-#define SVM_EXIT_CLGI\t\t0x085\n-#define SVM_EXIT_SKINIT\t\t0x086\n-#define SVM_EXIT_RDTSCP\t\t0x087\n-#define SVM_EXIT_ICEBP\t\t0x088\n-#define SVM_EXIT_WBINVD\t\t0x089\n+#define SVM_EXIT_INTR 0x060\n+#define SVM_EXIT_NMI 0x061\n+#define SVM_EXIT_SMI 0x062\n+#define SVM_EXIT_INIT 0x063\n+#define SVM_EXIT_VINTR 0x064\n+#define SVM_EXIT_CR0_SEL_WRITE 0x065\n+#define SVM_EXIT_IDTR_READ 0x066\n+#define SVM_EXIT_GDTR_READ 0x067\n+#define SVM_EXIT_LDTR_READ 0x068\n+#define SVM_EXIT_TR_READ 0x069\n+#define SVM_EXIT_IDTR_WRITE 0x06a\n+#define SVM_EXIT_GDTR_WRITE 0x06b\n+#define SVM_EXIT_LDTR_WRITE 0x06c\n+#define SVM_EXIT_TR_WRITE 0x06d\n+#define SVM_EXIT_RDTSC 0x06e\n+#define SVM_EXIT_RDPMC 0x06f\n+#define SVM_EXIT_PUSHF 0x070\n+#define SVM_EXIT_POPF 0x071\n+#define SVM_EXIT_CPUID 0x072\n+#define SVM_EXIT_RSM 0x073\n+#define SVM_EXIT_IRET 0x074\n+#define SVM_EXIT_SWINT 0x075\n+#define SVM_EXIT_INVD 0x076\n+#define SVM_EXIT_PAUSE 0x077\n+#define SVM_EXIT_HLT 0x078\n+#define SVM_EXIT_INVLPG 0x079\n+#define SVM_EXIT_INVLPGA 0x07a\n+#define SVM_EXIT_IOIO 0x07b\n+#define SVM_EXIT_MSR 0x07c\n+#define SVM_EXIT_TASK_SWITCH 0x07d\n+#define SVM_EXIT_FERR_FREEZE 0x07e\n+#define SVM_EXIT_SHUTDOWN 0x07f\n+#define SVM_EXIT_VMRUN 0x080\n+#define SVM_EXIT_VMMCALL 0x081\n+#define SVM_EXIT_VMLOAD 0x082\n+#define SVM_EXIT_VMSAVE 0x083\n+#define SVM_EXIT_STGI 0x084\n+#define SVM_EXIT_CLGI 0x085\n+#define SVM_EXIT_SKINIT 0x086\n+#define SVM_EXIT_RDTSCP 0x087\n+#define SVM_EXIT_ICEBP 0x088\n+#define SVM_EXIT_WBINVD 0x089\n /* only included in documentation, maybe wrong */\n-#define SVM_EXIT_MONITOR\t0x08a\n-#define SVM_EXIT_MWAIT\t\t0x08b\n-#define SVM_EXIT_XSETBV\t\t0x08d\n-#define SVM_EXIT_NPF \t\t0x400\n+#define SVM_EXIT_MONITOR 0x08a\n+#define SVM_EXIT_MWAIT 0x08b\n+#define SVM_EXIT_XSETBV 0x08d\n+#define SVM_EXIT_NPF 0x400\n \n-#define SVM_EXIT_ERR\t\t-1\n+#define SVM_EXIT_ERR -1\n \n #define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */\n \n@@ -146,96 +146,96 @@\n \n #define SVM_CR0_RESERVED_MASK 0xffffffff00000000U\n \n-#define SVM_MSRPM_SIZE\t\t(1ULL << 13)\n-#define SVM_IOPM_SIZE\t\t((1ULL << 13) + 1)\n+#define SVM_MSRPM_SIZE (1ULL << 13)\n+#define SVM_IOPM_SIZE ((1ULL << 13) + 1)\n \n struct QEMU_PACKED vmcb_control_area {\n-\tuint16_t intercept_cr_read;\n-\tuint16_t intercept_cr_write;\n-\tuint16_t intercept_dr_read;\n-\tuint16_t intercept_dr_write;\n-\tuint32_t intercept_exceptions;\n-\tuint64_t intercept;\n-\tuint8_t reserved_1[44];\n-\tuint64_t iopm_base_pa;\n-\tuint64_t msrpm_base_pa;\n-\tuint64_t tsc_offset;\n-\tuint32_t asid;\n-\tuint8_t tlb_ctl;\n-\tuint8_t reserved_2[3];\n-\tuint32_t int_ctl;\n-\tuint32_t int_vector;\n-\tuint32_t int_state;\n-\tuint8_t reserved_3[4];\n-\tuint64_t exit_code;\n-\tuint64_t exit_info_1;\n-\tuint64_t exit_info_2;\n-\tuint32_t exit_int_info;\n-\tuint32_t exit_int_info_err;\n-\tuint64_t nested_ctl;\n-\tuint8_t reserved_4[16];\n-\tuint32_t event_inj;\n-\tuint32_t event_inj_err;\n-\tuint64_t nested_cr3;\n-\tuint64_t lbr_ctl;\n-\tuint8_t reserved_5[832];\n+ uint16_t intercept_cr_read;\n+ uint16_t intercept_cr_write;\n+ uint16_t intercept_dr_read;\n+ uint16_t intercept_dr_write;\n+ uint32_t intercept_exceptions;\n+ uint64_t intercept;\n+ uint8_t reserved_1[44];\n+ uint64_t iopm_base_pa;\n+ uint64_t msrpm_base_pa;\n+ uint64_t tsc_offset;\n+ uint32_t asid;\n+ uint8_t tlb_ctl;\n+ uint8_t reserved_2[3];\n+ uint32_t int_ctl;\n+ uint32_t int_vector;\n+ uint32_t int_state;\n+ uint8_t reserved_3[4];\n+ uint64_t exit_code;\n+ uint64_t exit_info_1;\n+ uint64_t exit_info_2;\n+ uint32_t exit_int_info;\n+ uint32_t exit_int_info_err;\n+ uint64_t nested_ctl;\n+ uint8_t reserved_4[16];\n+ uint32_t event_inj;\n+ uint32_t event_inj_err;\n+ uint64_t nested_cr3;\n+ uint64_t lbr_ctl;\n+ uint8_t reserved_5[832];\n };\n \n struct QEMU_PACKED vmcb_seg {\n-\tuint16_t selector;\n-\tuint16_t attrib;\n-\tuint32_t limit;\n-\tuint64_t base;\n+ uint16_t selector;\n+ uint16_t attrib;\n+ uint32_t limit;\n+ uint64_t base;\n };\n \n struct QEMU_PACKED vmcb_save_area {\n-\tstruct vmcb_seg es;\n-\tstruct vmcb_seg cs;\n-\tstruct vmcb_seg ss;\n-\tstruct vmcb_seg ds;\n-\tstruct vmcb_seg fs;\n-\tstruct vmcb_seg gs;\n-\tstruct vmcb_seg gdtr;\n-\tstruct vmcb_seg ldtr;\n-\tstruct vmcb_seg idtr;\n-\tstruct vmcb_seg tr;\n-\tuint8_t reserved_1[43];\n-\tuint8_t cpl;\n-\tuint8_t reserved_2[4];\n-\tuint64_t efer;\n-\tuint8_t reserved_3[112];\n-\tuint64_t cr4;\n-\tuint64_t cr3;\n-\tuint64_t cr0;\n-\tuint64_t dr7;\n-\tuint64_t dr6;\n-\tuint64_t rflags;\n-\tuint64_t rip;\n-\tuint8_t reserved_4[88];\n-\tuint64_t rsp;\n-\tuint8_t reserved_5[24];\n-\tuint64_t rax;\n-\tuint64_t star;\n-\tuint64_t lstar;\n-\tuint64_t cstar;\n-\tuint64_t sfmask;\n-\tuint64_t kernel_gs_base;\n-\tuint64_t sysenter_cs;\n-\tuint64_t sysenter_esp;\n-\tuint64_t sysenter_eip;\n-\tuint64_t cr2;\n-\tuint8_t reserved_6[32];\n-\tuint64_t g_pat;\n-\tuint64_t dbgctl;\n-\tuint64_t br_from;\n-\tuint64_t br_to;\n-\tuint64_t last_excp_from;\n-\tuint64_t last_excp_to;\n+ struct vmcb_seg es;\n+ struct vmcb_seg cs;\n+ struct vmcb_seg ss;\n+ struct vmcb_seg ds;\n+ struct vmcb_seg fs;\n+ struct vmcb_seg gs;\n+ struct vmcb_seg gdtr;\n+ struct vmcb_seg ldtr;\n+ struct vmcb_seg idtr;\n+ struct vmcb_seg tr;\n+ uint8_t reserved_1[43];\n+ uint8_t cpl;\n+ uint8_t reserved_2[4];\n+ uint64_t efer;\n+ uint8_t reserved_3[112];\n+ uint64_t cr4;\n+ uint64_t cr3;\n+ uint64_t cr0;\n+ uint64_t dr7;\n+ uint64_t dr6;\n+ uint64_t rflags;\n+ uint64_t rip;\n+ uint8_t reserved_4[88];\n+ uint64_t rsp;\n+ uint8_t reserved_5[24];\n+ uint64_t rax;\n+ uint64_t star;\n+ uint64_t lstar;\n+ uint64_t cstar;\n+ uint64_t sfmask;\n+ uint64_t kernel_gs_base;\n+ uint64_t sysenter_cs;\n+ uint64_t sysenter_esp;\n+ uint64_t sysenter_eip;\n+ uint64_t cr2;\n+ uint8_t reserved_6[32];\n+ uint64_t g_pat;\n+ uint64_t dbgctl;\n+ uint64_t br_from;\n+ uint64_t br_to;\n+ uint64_t last_excp_from;\n+ uint64_t last_excp_to;\n };\n \n struct QEMU_PACKED vmcb {\n-\tstruct vmcb_control_area control;\n-\tstruct vmcb_save_area save;\n+ struct vmcb_control_area control;\n+ struct vmcb_save_area save;\n };\n \n #endif\ndiff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h\nindex d26b933b6d..5a856edaaa 100644\n--- a/target/microblaze/cpu.h\n+++ b/target/microblaze/cpu.h\n@@ -122,9 +122,9 @@ typedef struct CPUArchState CPUMBState;\n #define PVR0_USE_ICACHE_MASK 0x02000000\n #define PVR0_USE_DCACHE_MASK 0x01000000\n #define PVR0_USE_MMU_MASK 0x00800000\n-#define PVR0_USE_BTC\t\t\t0x00400000\n+#define PVR0_USE_BTC 0x00400000\n #define PVR0_ENDI_MASK 0x00200000\n-#define PVR0_FAULT\t\t\t0x00100000\n+#define PVR0_FAULT 0x00100000\n #define PVR0_VERSION_MASK 0x0000FF00\n #define PVR0_USER1_MASK 0x000000FF\n #define PVR0_SPROT_MASK 0x00000001\n@@ -271,10 +271,10 @@ struct CPUArchState {\n /* MSR_UM (1 << 11) */\n /* MSR_VM (1 << 13) */\n /* ESR_ESS_MASK [11:5] -- unwind into iflags for unaligned excp */\n-#define D_FLAG\t\t(1 << 12) /* Bit in ESR. */\n-#define DRTI_FLAG\t(1 << 16)\n-#define DRTE_FLAG\t(1 << 17)\n-#define DRTB_FLAG\t(1 << 18)\n+#define D_FLAG (1 << 12) /* Bit in ESR. */\n+#define DRTI_FLAG (1 << 16)\n+#define DRTE_FLAG (1 << 17)\n+#define DRTB_FLAG (1 << 18)\n \n /* TB dependent CPUMBState. */\n #define IFLAGS_TB_MASK (D_FLAG | BIMM_FLAG | IMM_FLAG | \\\ndiff --git a/target/sparc/asi.h b/target/sparc/asi.h\nindex 14ffaa3842..7d6dae6d61 100644\n--- a/target/sparc/asi.h\n+++ b/target/sparc/asi.h\n@@ -102,7 +102,7 @@\n \n #define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */\n \n-#define ASI_M_VIKING_TMP1 0x40\t /* Emulation temporary 1 on Viking */\n+#define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */\n /* only available on SuperSparc I */\n /* #define ASI_M_VIKING_TMP2 0x41 */ /* Emulation temporary 2 on Viking */\n \n@@ -123,20 +123,20 @@\n #define ASI_LEON_FLUSH_PAGE 0x10\n \n /* V9 Architecture mandary ASIs. */\n-#define ASI_N\t\t\t0x04 /* Nucleus\t\t\t\t*/\n-#define ASI_NL\t\t\t0x0c /* Nucleus, little endian\t\t*/\n-#define ASI_AIUP\t\t0x10 /* Primary, user\t\t\t*/\n-#define ASI_AIUS\t\t0x11 /* Secondary, user\t\t\t*/\n-#define ASI_AIUPL\t\t0x18 /* Primary, user, little endian\t*/\n-#define ASI_AIUSL\t\t0x19 /* Secondary, user, little endian\t*/\n-#define ASI_P\t\t\t0x80 /* Primary, implicit\t\t*/\n-#define ASI_S\t\t\t0x81 /* Secondary, implicit\t\t*/\n-#define ASI_PNF\t\t\t0x82 /* Primary, no fault\t\t*/\n-#define ASI_SNF\t\t\t0x83 /* Secondary, no fault\t\t*/\n-#define ASI_PL\t\t\t0x88 /* Primary, implicit, l-endian\t*/\n-#define ASI_SL\t\t\t0x89 /* Secondary, implicit, l-endian\t*/\n-#define ASI_PNFL\t\t0x8a /* Primary, no fault, l-endian\t*/\n-#define ASI_SNFL\t\t0x8b /* Secondary, no fault, l-endian\t*/\n+#define ASI_N 0x04 /* Nucleus */\n+#define ASI_NL 0x0c /* Nucleus, little endian */\n+#define ASI_AIUP 0x10 /* Primary, user */\n+#define ASI_AIUS 0x11 /* Secondary, user */\n+#define ASI_AIUPL 0x18 /* Primary, user, little endian */\n+#define ASI_AIUSL 0x19 /* Secondary, user, little endian */\n+#define ASI_P 0x80 /* Primary, implicit */\n+#define ASI_S 0x81 /* Secondary, implicit */\n+#define ASI_PNF 0x82 /* Primary, no fault */\n+#define ASI_SNF 0x83 /* Secondary, no fault */\n+#define ASI_PL 0x88 /* Primary, implicit, l-endian */\n+#define ASI_SL 0x89 /* Secondary, implicit, l-endian */\n+#define ASI_PNFL 0x8a /* Primary, no fault, l-endian */\n+#define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */\n \n /* SpitFire and later extended ASIs. The \"(III)\" marker designates\n * UltraSparc-III and later specific ASIs. The \"(CMT)\" marker designates\n@@ -147,170 +147,170 @@\n #define ASI_MON_AIUP 0x12 /* (VIS4) Primary, user, monitor */\n #define ASI_MON_AIUS 0x13 /* (VIS4) Secondary, user, monitor */\n #define ASI_REAL 0x14 /* Real address, cacheable */\n-#define ASI_PHYS_USE_EC\t\t0x14 /* PADDR, E-cacheable\t\t*/\n+#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cacheable */\n #define ASI_REAL_IO 0x15 /* Real address, non-cacheable */\n-#define ASI_PHYS_BYPASS_EC_E\t0x15 /* PADDR, E-bit\t\t\t*/\n-#define ASI_BLK_AIUP_4V\t\t0x16 /* (4V) Prim, user, block ld/st\t*/\n-#define ASI_BLK_AIUS_4V\t\t0x17 /* (4V) Sec, user, block ld/st\t*/\n+#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */\n+#define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */\n+#define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */\n #define ASI_REAL_L 0x1c /* Real address, cacheable, LE */\n-#define ASI_PHYS_USE_EC_L\t0x1c /* PADDR, E-cacheable, little endian*/\n+#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cacheable, little endian*/\n #define ASI_REAL_IO_L 0x1d /* Real address, non-cacheable, LE */\n-#define ASI_PHYS_BYPASS_EC_E_L\t0x1d /* PADDR, E-bit, little endian\t*/\n-#define ASI_BLK_AIUP_L_4V\t0x1e /* (4V) Prim, user, block, l-endian*/\n-#define ASI_BLK_AIUS_L_4V\t0x1f /* (4V) Sec, user, block, l-endian\t*/\n-#define ASI_SCRATCHPAD\t\t0x20 /* (4V) Scratch Pad Registers\t*/\n-#define ASI_MMU\t\t\t0x21 /* (4V) MMU Context Registers\t*/\n+#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */\n+#define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/\n+#define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */\n+#define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */\n+#define ASI_MMU 0x21 /* (4V) MMU Context Registers */\n #define ASI_TWINX_AIUP 0x22 /* twin load, primary user */\n #define ASI_TWINX_AIUS 0x23 /* twin load, secondary user */\n #define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,\n-\t\t\t\t\t * secondary, user\n-\t\t\t\t\t */\n-#define ASI_NUCLEUS_QUAD_LDD\t0x24 /* Cacheable, qword load\t\t*/\n-#define ASI_QUEUE\t\t0x25 /* (4V) Interrupt Queue Registers\t*/\n-#define ASI_TWINX_REAL 0x26 /* twin load, real, cacheable\t*/\n-#define ASI_QUAD_LDD_PHYS_4V\t0x26 /* (4V) Physical, qword load\t*/\n+ * secondary, user\n+ */\n+#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cacheable, qword load */\n+#define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */\n+#define ASI_TWINX_REAL 0x26 /* twin load, real, cacheable */\n+#define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */\n #define ASI_TWINX_N 0x27 /* twin load, nucleus */\n #define ASI_TWINX_AIUP_L 0x2a /* twin load, primary user, LE */\n #define ASI_TWINX_AIUS_L 0x2b /* twin load, secondary user, LE */\n-#define ASI_NUCLEUS_QUAD_LDD_L\t0x2c /* Cacheable, qword load, l-endian */\n-#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cacheable, LE\t*/\n-#define ASI_QUAD_LDD_PHYS_L_4V\t0x2e /* (4V) Phys, qword load, l-endian\t*/\n+#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cacheable, qword load, l-endian */\n+#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cacheable, LE */\n+#define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */\n #define ASI_TWINX_NL 0x2f /* twin load, nucleus, LE */\n-#define ASI_PCACHE_DATA_STATUS\t0x30 /* (III) PCache data stat RAM diag\t*/\n-#define ASI_PCACHE_DATA\t\t0x31 /* (III) PCache data RAM diag\t*/\n-#define ASI_PCACHE_TAG\t\t0x32 /* (III) PCache tag RAM diag\t*/\n-#define ASI_PCACHE_SNOOP_TAG\t0x33 /* (III) PCache snoop tag RAM diag\t*/\n-#define ASI_QUAD_LDD_PHYS\t0x34 /* (III+) PADDR, qword load\t*/\n-#define ASI_WCACHE_VALID_BITS\t0x38 /* (III) WCache Valid Bits diag\t*/\n-#define ASI_WCACHE_DATA\t\t0x39 /* (III) WCache data RAM diag\t*/\n-#define ASI_WCACHE_TAG\t\t0x3a /* (III) WCache tag RAM diag\t*/\n-#define ASI_WCACHE_SNOOP_TAG\t0x3b /* (III) WCache snoop tag RAM diag\t*/\n-#define ASI_QUAD_LDD_PHYS_L\t0x3c /* (III+) PADDR, qw-load, l-endian\t*/\n-#define ASI_SRAM_FAST_INIT\t0x40 /* (III+) Fast SRAM init\t\t*/\n-#define ASI_CORE_AVAILABLE\t0x41 /* (CMT) LP Available\t\t*/\n-#define ASI_CORE_ENABLE_STAT\t0x41 /* (CMT) LP Enable Status\t\t*/\n-#define ASI_CORE_ENABLE\t\t0x41 /* (CMT) LP Enable RW\t\t*/\n-#define ASI_XIR_STEERING\t0x41 /* (CMT) XIR Steering RW\t\t*/\n-#define ASI_CORE_RUNNING_RW\t0x41 /* (CMT) LP Running RW\t\t*/\n-#define ASI_CORE_RUNNING_W1S\t0x41 /* (CMT) LP Running Write-One Set\t*/\n-#define ASI_CORE_RUNNING_W1C\t0x41 /* (CMT) LP Running Write-One Clr\t*/\n-#define ASI_CORE_RUNNING_STAT\t0x41 /* (CMT) LP Running Status\t\t*/\n-#define ASI_CMT_ERROR_STEERING\t0x41 /* (CMT) Error Steering RW\t\t*/\n-#define ASI_DCACHE_INVALIDATE\t0x42 /* (III) DCache Invalidate diag\t*/\n-#define ASI_DCACHE_UTAG\t\t0x43 /* (III) DCache uTag diag\t\t*/\n-#define ASI_DCACHE_SNOOP_TAG\t0x44 /* (III) DCache snoop tag RAM diag\t*/\n-#define ASI_LSU_CONTROL\t\t0x45 /* Load-store control unit\t\t*/\n-#define ASI_DCU_CONTROL_REG\t0x45 /* (III) DCache Unit Control reg\t*/\n-#define ASI_DCACHE_DATA\t\t0x46 /* DCache data-ram diag access\t*/\n-#define ASI_DCACHE_TAG\t\t0x47 /* Dcache tag/valid ram diag access*/\n-#define ASI_INTR_DISPATCH_STAT\t0x48 /* IRQ vector dispatch status\t*/\n-#define ASI_INTR_RECEIVE\t0x49 /* IRQ vector receive status\t*/\n-#define ASI_UPA_CONFIG\t\t0x4a /* UPA config space\t\t*/\n-#define ASI_JBUS_CONFIG\t\t0x4a /* (IIIi) JBUS Config Register\t*/\n-#define ASI_SAFARI_CONFIG\t0x4a /* (III) Safari Config Register\t*/\n-#define ASI_SAFARI_ADDRESS\t0x4a /* (III) Safari Address Register\t*/\n-#define ASI_ESTATE_ERROR_EN\t0x4b /* E-cache error enable space\t*/\n-#define ASI_AFSR\t\t0x4c /* Async fault status register\t*/\n-#define ASI_AFAR\t\t0x4d /* Async fault address register\t*/\n-#define ASI_EC_TAG_DATA\t\t0x4e /* E-cache tag/valid ram diag acc\t*/\n-#define ASI_HYP_SCRATCHPAD\t0x4f /* (4V) Hypervisor scratchpad\t*/\n-#define ASI_IMMU\t\t0x50 /* Insn-MMU main register space\t*/\n-#define ASI_IMMU_TSB_8KB_PTR\t0x51 /* Insn-MMU 8KB TSB pointer reg\t*/\n-#define ASI_IMMU_TSB_64KB_PTR\t0x52 /* Insn-MMU 64KB TSB pointer reg\t*/\n-#define ASI_ITLB_DATA_IN\t0x54 /* Insn-MMU TLB data in reg\t*/\n-#define ASI_ITLB_DATA_ACCESS\t0x55 /* Insn-MMU TLB data access reg\t*/\n-#define ASI_ITLB_TAG_READ\t0x56 /* Insn-MMU TLB tag read reg\t*/\n-#define ASI_IMMU_DEMAP\t\t0x57 /* Insn-MMU TLB demap\t\t*/\n-#define ASI_DMMU\t\t0x58 /* Data-MMU main register space\t*/\n-#define ASI_DMMU_TSB_8KB_PTR\t0x59 /* Data-MMU 8KB TSB pointer reg\t*/\n-#define ASI_DMMU_TSB_64KB_PTR\t0x5a /* Data-MMU 16KB TSB pointer reg\t*/\n-#define ASI_DMMU_TSB_DIRECT_PTR\t0x5b /* Data-MMU TSB direct pointer reg\t*/\n-#define ASI_DTLB_DATA_IN\t0x5c /* Data-MMU TLB data in reg\t*/\n-#define ASI_DTLB_DATA_ACCESS\t0x5d /* Data-MMU TLB data access reg\t*/\n-#define ASI_DTLB_TAG_READ\t0x5e /* Data-MMU TLB tag read reg\t*/\n-#define ASI_DMMU_DEMAP\t\t0x5f /* Data-MMU TLB demap\t\t*/\n-#define ASI_IIU_INST_TRAP\t0x60 /* (III) Instruction Breakpoint\t*/\n-#define ASI_INTR_ID\t\t0x63 /* (CMT) Interrupt ID register\t*/\n-#define ASI_CORE_ID\t\t0x63 /* (CMT) LP ID register\t\t*/\n-#define ASI_CESR_ID\t\t0x63 /* (CMT) CESR ID register\t\t*/\n-#define ASI_IC_INSTR\t\t0x66 /* Insn cache instruction ram diag\t*/\n-#define ASI_IC_TAG\t\t0x67 /* Insn cache tag/valid ram diag \t*/\n-#define ASI_IC_STAG\t\t0x68 /* (III) Insn cache snoop tag ram\t*/\n-#define ASI_IC_PRE_DECODE\t0x6e /* Insn cache pre-decode ram diag\t*/\n-#define ASI_IC_NEXT_FIELD\t0x6f /* Insn cache next-field ram diag\t*/\n-#define ASI_BRPRED_ARRAY\t0x6f /* (III) Branch Prediction RAM diag*/\n-#define ASI_BLK_AIUP\t\t0x70 /* Primary, user, block load/store\t*/\n-#define ASI_BLK_AIUS\t\t0x71 /* Secondary, user, block ld/st\t*/\n-#define ASI_MCU_CTRL_REG\t0x72 /* (III) Memory controller regs\t*/\n-#define ASI_EC_DATA\t\t0x74 /* (III) E-cache data staging reg\t*/\n-#define ASI_EC_CTRL\t\t0x75 /* (III) E-cache control reg\t*/\n-#define ASI_EC_W\t\t0x76 /* E-cache diag write access\t*/\n-#define ASI_UDB_ERROR_W\t\t0x77 /* External UDB error regs W\t*/\n-#define ASI_UDB_CONTROL_W\t0x77 /* External UDB control regs W\t*/\n-#define ASI_INTR_W\t\t0x77 /* IRQ vector dispatch write\t*/\n-#define ASI_INTR_DATAN_W\t0x77 /* (III) Out irq vector data reg N\t*/\n-#define ASI_INTR_DISPATCH_W\t0x77 /* (III) Interrupt vector dispatch\t*/\n-#define ASI_BLK_AIUPL\t\t0x78 /* Primary, user, little, blk ld/st*/\n-#define ASI_BLK_AIUSL\t\t0x79 /* Secondary, user, little, blk ld/st*/\n-#define ASI_EC_R\t\t0x7e /* E-cache diag read access\t*/\n-#define ASI_UDBH_ERROR_R\t0x7f /* External UDB error regs rd hi\t*/\n-#define ASI_UDBL_ERROR_R\t0x7f /* External UDB error regs rd low\t*/\n-#define ASI_UDBH_CONTROL_R\t0x7f /* External UDB control regs rd hi\t*/\n-#define ASI_UDBL_CONTROL_R\t0x7f /* External UDB control regs rd low*/\n-#define ASI_INTR_R\t\t0x7f /* IRQ vector dispatch read\t*/\n-#define ASI_INTR_DATAN_R\t0x7f /* (III) In irq vector data reg N\t*/\n+#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */\n+#define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */\n+#define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */\n+#define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */\n+#define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */\n+#define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */\n+#define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */\n+#define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */\n+#define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */\n+#define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */\n+#define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */\n+#define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */\n+#define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */\n+#define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */\n+#define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */\n+#define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */\n+#define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */\n+#define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */\n+#define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */\n+#define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */\n+#define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */\n+#define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */\n+#define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */\n+#define ASI_LSU_CONTROL 0x45 /* Load-store control unit */\n+#define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */\n+#define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */\n+#define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/\n+#define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */\n+#define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */\n+#define ASI_UPA_CONFIG 0x4a /* UPA config space */\n+#define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */\n+#define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */\n+#define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */\n+#define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */\n+#define ASI_AFSR 0x4c /* Async fault status register */\n+#define ASI_AFAR 0x4d /* Async fault address register */\n+#define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */\n+#define ASI_HYP_SCRATCHPAD 0x4f /* (4V) Hypervisor scratchpad */\n+#define ASI_IMMU 0x50 /* Insn-MMU main register space */\n+#define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */\n+#define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */\n+#define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */\n+#define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */\n+#define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */\n+#define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */\n+#define ASI_DMMU 0x58 /* Data-MMU main register space */\n+#define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */\n+#define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */\n+#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */\n+#define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */\n+#define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */\n+#define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */\n+#define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */\n+#define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */\n+#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */\n+#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */\n+#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */\n+#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */\n+#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */\n+#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */\n+#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */\n+#define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */\n+#define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/\n+#define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */\n+#define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */\n+#define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */\n+#define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */\n+#define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */\n+#define ASI_EC_W 0x76 /* E-cache diag write access */\n+#define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */\n+#define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */\n+#define ASI_INTR_W 0x77 /* IRQ vector dispatch write */\n+#define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */\n+#define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */\n+#define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/\n+#define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/\n+#define ASI_EC_R 0x7e /* E-cache diag read access */\n+#define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */\n+#define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */\n+#define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */\n+#define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/\n+#define ASI_INTR_R 0x7f /* IRQ vector dispatch read */\n+#define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */\n #define ASI_MON_P 0x84 /* (VIS4) Primary, monitor */\n #define ASI_MON_S 0x85 /* (VIS4) Secondary, monitor */\n-#define ASI_PIC\t\t\t0xb0 /* (NG4) PIC registers\t\t*/\n-#define ASI_PST8_P\t\t0xc0 /* Primary, 8 8-bit, partial\t*/\n-#define ASI_PST8_S\t\t0xc1 /* Secondary, 8 8-bit, partial\t*/\n-#define ASI_PST16_P\t\t0xc2 /* Primary, 4 16-bit, partial\t*/\n-#define ASI_PST16_S\t\t0xc3 /* Secondary, 4 16-bit, partial\t*/\n-#define ASI_PST32_P\t\t0xc4 /* Primary, 2 32-bit, partial\t*/\n-#define ASI_PST32_S\t\t0xc5 /* Secondary, 2 32-bit, partial\t*/\n-#define ASI_PST8_PL\t\t0xc8 /* Primary, 8 8-bit, partial, L\t*/\n-#define ASI_PST8_SL\t\t0xc9 /* Secondary, 8 8-bit, partial, L\t*/\n-#define ASI_PST16_PL\t\t0xca /* Primary, 4 16-bit, partial, L\t*/\n-#define ASI_PST16_SL\t\t0xcb /* Secondary, 4 16-bit, partial, L\t*/\n-#define ASI_PST32_PL\t\t0xcc /* Primary, 2 32-bit, partial, L\t*/\n-#define ASI_PST32_SL\t\t0xcd /* Secondary, 2 32-bit, partial, L\t*/\n-#define ASI_FL8_P\t\t0xd0 /* Primary, 1 8-bit, fpu ld/st\t*/\n-#define ASI_FL8_S\t\t0xd1 /* Secondary, 1 8-bit, fpu ld/st\t*/\n-#define ASI_FL16_P\t\t0xd2 /* Primary, 1 16-bit, fpu ld/st\t*/\n-#define ASI_FL16_S\t\t0xd3 /* Secondary, 1 16-bit, fpu ld/st\t*/\n-#define ASI_FL8_PL\t\t0xd8 /* Primary, 1 8-bit, fpu ld/st, L\t*/\n-#define ASI_FL8_SL\t\t0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/\n-#define ASI_FL16_PL\t\t0xda /* Primary, 1 16-bit, fpu ld/st, L\t*/\n-#define ASI_FL16_SL\t\t0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/\n-#define ASI_BLK_COMMIT_P\t0xe0 /* Primary, blk store commit\t*/\n-#define ASI_BLK_COMMIT_S\t0xe1 /* Secondary, blk store commit\t*/\n+#define ASI_PIC 0xb0 /* (NG4) PIC registers */\n+#define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */\n+#define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */\n+#define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */\n+#define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */\n+#define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */\n+#define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */\n+#define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */\n+#define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */\n+#define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */\n+#define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */\n+#define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */\n+#define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */\n+#define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */\n+#define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */\n+#define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */\n+#define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */\n+#define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */\n+#define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/\n+#define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */\n+#define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/\n+#define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */\n+#define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */\n #define ASI_TWINX_P 0xe2 /* twin load, primary implicit */\n-#define ASI_BLK_INIT_QUAD_LDD_P\t0xe2 /* (NG) init-store, twin load,\n-\t\t\t\t * primary, implicit */\n+#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load,\n+ * primary, implicit */\n #define ASI_TWINX_S 0xe3 /* twin load, secondary implicit */\n-#define ASI_BLK_INIT_QUAD_LDD_S\t0xe3 /* (NG) init-store, twin load,\n-\t\t\t\t * secondary, implicit */\n+#define ASI_BLK_INIT_QUAD_LDD_S 0xe3 /* (NG) init-store, twin load,\n+ * secondary, implicit */\n #define ASI_TWINX_PL 0xea /* twin load, primary implicit, LE */\n #define ASI_TWINX_SL 0xeb /* twin load, secondary implicit, LE */\n-#define ASI_BLK_P\t\t0xf0 /* Primary, blk ld/st\t\t*/\n-#define ASI_BLK_S\t\t0xf1 /* Secondary, blk ld/st\t\t*/\n-#define ASI_ST_BLKINIT_MRU_P\t0xf2 /* (NG4) init-store, twin load,\n-\t\t\t\t * Most-Recently-Used, primary,\n-\t\t\t\t * implicit\n-\t\t\t\t */\n-#define ASI_ST_BLKINIT_MRU_S\t0xf2 /* (NG4) init-store, twin load,\n-\t\t\t\t * Most-Recently-Used, secondary,\n-\t\t\t\t * implicit\n-\t\t\t\t */\n-#define ASI_BLK_PL\t\t0xf8 /* Primary, blk ld/st, little\t*/\n-#define ASI_BLK_SL\t\t0xf9 /* Secondary, blk ld/st, little\t*/\n-#define ASI_ST_BLKINIT_MRU_PL\t0xfa /* (NG4) init-store, twin load,\n-\t\t\t\t * Most-Recently-Used, primary,\n-\t\t\t\t * implicit, little-endian\n-\t\t\t\t */\n-#define ASI_ST_BLKINIT_MRU_SL\t0xfb /* (NG4) init-store, twin load,\n-\t\t\t\t * Most-Recently-Used, secondary,\n-\t\t\t\t * implicit, little-endian\n-\t\t\t\t */\n+#define ASI_BLK_P 0xf0 /* Primary, blk ld/st */\n+#define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */\n+#define ASI_ST_BLKINIT_MRU_P 0xf2 /* (NG4) init-store, twin load,\n+ * Most-Recently-Used, primary,\n+ * implicit\n+ */\n+#define ASI_ST_BLKINIT_MRU_S 0xf2 /* (NG4) init-store, twin load,\n+ * Most-Recently-Used, secondary,\n+ * implicit\n+ */\n+#define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */\n+#define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */\n+#define ASI_ST_BLKINIT_MRU_PL 0xfa /* (NG4) init-store, twin load,\n+ * Most-Recently-Used, primary,\n+ * implicit, little-endian\n+ */\n+#define ASI_ST_BLKINIT_MRU_SL 0xfb /* (NG4) init-store, twin load,\n+ * Most-Recently-Used, secondary,\n+ * implicit, little-endian\n+ */\n \n #endif /* SPARC_ASI_H */\n", "prefixes": [] }