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{
    "id": 2217379,
    "url": "http://patchwork.ozlabs.org/api/patches/2217379/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260328090548.84124-1-biju.das.jz@bp.renesas.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
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    "msgid": "<20260328090548.84124-1-biju.das.jz@bp.renesas.com>",
    "list_archive_url": null,
    "date": "2026-03-28T09:05:45",
    "name": "pinctrl: renesas: rzg2l: Fix incorrect PUPD register offset for high pins during suspend/resume",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "0d2b1bb1efde360cecffa071d02e917d593f6ebf",
    "submitter": {
        "id": 87968,
        "url": "http://patchwork.ozlabs.org/api/people/87968/?format=api",
        "name": "Biju",
        "email": "biju.das.au@gmail.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260328090548.84124-1-biju.das.jz@bp.renesas.com/mbox/",
    "series": [
        {
            "id": 497858,
            "url": "http://patchwork.ozlabs.org/api/series/497858/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=497858",
            "date": "2026-03-28T09:05:45",
            "name": "pinctrl: renesas: rzg2l: Fix incorrect PUPD register offset for high pins during suspend/resume",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/497858/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2217379/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2217379/checks/",
    "tags": {},
    "related": [],
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        "From": "Biju <biju.das.au@gmail.com>",
        "X-Google-Original-From": "Biju <biju.das.jz@bp.renesas.com>",
        "To": "Geert Uytterhoeven <geert+renesas@glider.be>,\n\tLinus Walleij <linusw@kernel.org>",
        "Cc": "Biju Das <biju.das.jz@bp.renesas.com>,\n\tLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,\n\tClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,\n\tlinux-renesas-soc@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tBiju Das <biju.das.au@gmail.com>",
        "Subject": "[PATCH] pinctrl: renesas: rzg2l: Fix incorrect PUPD register offset\n for high pins during suspend/resume",
        "Date": "Sat, 28 Mar 2026 09:05:45 +0000",
        "Message-ID": "<20260328090548.84124-1-biju.das.jz@bp.renesas.com>",
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    },
    "content": "From: Biju Das <biju.das.jz@bp.renesas.com>\n\nWhen saving/restoring pull-up/down register state during suspend/resume,\nthe second PUPD register access was incorrectly using the same base offset\nas the first, effectively reading/writing the same register twice instead\nof the adjacent one.\n\nAdd the correct + 4 byte offset to the second RZG2L_PCTRL_REG_ACCESS32\ncall so that pupd[1][port] is properly saved and restored from the next\n32-bit register in the PUPD register pair, covering pins 4–7 of ports\nwith 4 or more pins.\n\nFixes: b2bd65fbb617 (\"pinctrl: renesas: rzg2l: Add suspend/resume support for pull up/down\")\nSigned-off-by: Biju Das <biju.das.jz@bp.renesas.com>\n---\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)",
    "diff": "diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\nindex 561e6018fd89..68b94c748f53 100644\n--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n@@ -3049,7 +3049,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen\n \t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),\n \t\t\t\t\t\t cache->pupd[0][port]);\n \t\t\tif (pincnt >= 4) {\n-\t\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),\n+\t\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off) + 4,\n \t\t\t\t\t\t\t cache->pupd[1][port]);\n \t\t\t}\n \t\t}\n",
    "prefixes": []
}