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GET /api/patches/2217353/?format=api
{ "id": 2217353, "url": "http://patchwork.ozlabs.org/api/patches/2217353/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260328021036.85945-6-mailingradian@gmail.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260328021036.85945-6-mailingradian@gmail.com>", "list_archive_url": null, "date": "2026-03-28T02:10:36", "name": "[v3,5/5] arm64: dts: qcom: sdm670-google: add reserved lpi gpios", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "161cba6a6b5ade85fc1c3f305a6af1d240cf4584", "submitter": { "id": 84825, "url": "http://patchwork.ozlabs.org/api/people/84825/?format=api", "name": "Richard Acayan", "email": "mailingradian@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260328021036.85945-6-mailingradian@gmail.com/mbox/", "series": [ { "id": 497848, "url": "http://patchwork.ozlabs.org/api/series/497848/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=497848", "date": "2026-03-28T02:10:34", "name": "SDM670 LPASS LPI pin controller support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497848/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217353/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217353/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-34341-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Mqgo4Mgs;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-gpio+bounces-34341-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"Mqgo4Mgs\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.219.53", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fjLc90lP4z1y1x\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 28 Mar 2026 13:11:53 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id A496B30570D0\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 28 Mar 2026 02:10:43 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 3902E3563D2;\n\tSat, 28 Mar 2026 02:10:43 +0000 (UTC)", "from mail-qv1-f53.google.com (mail-qv1-f53.google.com\n [209.85.219.53])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id C8BFF358361\n\tfor <linux-gpio@vger.kernel.org>; Sat, 28 Mar 2026 02:10:41 +0000 (UTC)", "by mail-qv1-f53.google.com with SMTP id\n 6a1803df08f44-89a6ac6f389so30981676d6.3\n for <linux-gpio@vger.kernel.org>;\n Fri, 27 Mar 2026 19:10:41 -0700 (PDT)", "from localhost\n (bras-base-toroon21-grc-75-184-144-58-243.dsl.bell.ca. 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Add the reserved GPIOs for the LPI pin controller.\n\nSigned-off-by: Richard Acayan <mailingradian@gmail.com>\n---\n arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi | 4 ++++\n 1 file changed, 4 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi\nindex cf7b130ea0c4..b0da24fd1aee 100644\n--- a/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi\n+++ b/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi\n@@ -519,6 +519,10 @@ rmi4_f12: rmi4-f12@12 {\n \t};\n };\n \n+&lpi_tlmm {\n+\tgpio-reserved-ranges = <0 8>, <12 6>;\n+};\n+\n &mdss {\n \tstatus = \"okay\";\n };\n", "prefixes": [ "v3", "5/5" ] }