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GET /api/patches/2217346/?format=api
{ "id": 2217346, "url": "http://patchwork.ozlabs.org/api/patches/2217346/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20260327-dts_enable_nic_mctp-v1-1-5b5c05f4442c@amd.com/", "project": { "id": 57, "url": "http://patchwork.ozlabs.org/api/projects/57/?format=api", "name": "Linux ASPEED SoC development", "link_name": "linux-aspeed", "list_id": "linux-aspeed.lists.ozlabs.org", "list_email": "linux-aspeed@lists.ozlabs.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327-dts_enable_nic_mctp-v1-1-5b5c05f4442c@amd.com>", "list_archive_url": null, "date": "2026-03-27T06:59:16", "name": "ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cc8a19ec4485fda5f323ab481d48b16b5605121a", "submitter": { "id": 92993, "url": "http://patchwork.ozlabs.org/api/people/92993/?format=api", "name": "Andy Chung via B4 Relay", "email": "devnull+Andy.Chung.amd.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20260327-dts_enable_nic_mctp-v1-1-5b5c05f4442c@amd.com/mbox/", "series": [ { "id": 497846, "url": "http://patchwork.ozlabs.org/api/series/497846/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/list/?series=497846", "date": "2026-03-27T06:59:16", "name": "ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497846/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217346/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217346/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-aspeed+bounces-3794-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=rUIMEOJR;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; 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lists.ozlabs.org;\n dmarc=pass (p=quarantine dis=none) header.from=kernel.org;\n dkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=rUIMEOJR; dkim-atps=neutral;\n spf=pass (client-ip=2600:3c04:e001:324:0:1991:8:25;\n helo=tor.source.kernel.org;\n envelope-from=devnull+andy.chung.amd.com@kernel.org;\n receiver=lists.ozlabs.org) smtp.mailfrom=kernel.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1774594762;\n\tbh=+uYAGgoOPo8bLq2pJEoGgnHWXNq5+Y92SxzPmrm3lx0=;\n\th=From:Date:Subject:To:Cc:Reply-To:From;\n\tb=rUIMEOJRSYCB7RucQGG4PaxxD/Gxp+WS5WI2qbdgQUR2Tezsv5UaPTu5Sccjew3BX\n\t /STHbYE7fN8R2g8rR/pcnMiqRXxf2EEhaqdzOyCCgBt2XP7lxC+8yh/N1f9oXGJr/5\n\t dscnBFVUJrH1CyUTBjLG0OqxI+Vgs/9eEgtVn0zoxpDmQ8MBd+9Q9FCB2GE4cyIPlt\n\t HERoddZgvkEx2+vGkrdfTxBaIFLj7XQ+k8K6tGE1mFvY1E/fGMwDNqDZwX7hLh7n+o\n\t qLemUUVgm38RIIn76yV/h9dcnjRaXAmDvvjzhhORqyMhSDW6LXLWIosxV7zJJ7/4Xy\n\t S+yHbeaC+gZvw==", "From": "Andy Chung via B4 Relay <devnull+Andy.Chung.amd.com@kernel.org>", "Date": "Fri, 27 Mar 2026 14:59:16 +0800", "Subject": "[PATCH] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC", "X-Mailing-List": "linux-aspeed@lists.ozlabs.org", "List-Id": "<linux-aspeed.lists.ozlabs.org>", "List-Help": "<mailto:linux-aspeed+help@lists.ozlabs.org>", "List-Owner": "<mailto:linux-aspeed+owner@lists.ozlabs.org>", "List-Post": "<mailto:linux-aspeed@lists.ozlabs.org>", "List-Archive": "<https://lore.kernel.org/linux-aspeed/>,\n <https://lists.ozlabs.org/pipermail/linux-aspeed/>", "List-Subscribe": "<mailto:linux-aspeed+subscribe@lists.ozlabs.org>,\n <mailto:linux-aspeed+subscribe-digest@lists.ozlabs.org>,\n <mailto:linux-aspeed+subscribe-nomail@lists.ozlabs.org>", "List-Unsubscribe": "<mailto:linux-aspeed+unsubscribe@lists.ozlabs.org>", "Precedence": "list", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260327-dts_enable_nic_mctp-v1-1-5b5c05f4442c@amd.com>", "X-B4-Tracking": "v=1; b=H4sIAMMqxmkC/yXMQQrCMBBG4auUWRtoU5KAVxEJSfqrIxpLJopQe\n ndTu/wW7y0kKAyhY7dQwYeFX7lhOHSUbiFfoXhqJt1r24/aqamKRw7xAZ85+Weqs8JognHWxMF\n ZauVccOHv/3o675Z3vCPVbUXr+gP88bJ9dwAAAA==", "X-Change-ID": "20260327-dts_enable_nic_mctp-e35a5765b176", "To": "Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,\n Andrew Jeffery <andrew@codeconstruct.com.au>", "Cc": "devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,\n Andy Chung <andy.chung@amd.com>, Andy Chung <Andy.Chung@amd.com>", "X-Mailer": "b4 0.15.1", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1774594761; l=3825;\n i=Andy.Chung@amd.com; s=20260327; h=from:subject:message-id;\n bh=nPjZUWkxYiROesPBYSRnJtyY+ooYKRCOwqAAXx0E5II=;\n b=426Yu7gf6eNtDB2/x526jYc4Z1JqYnU4txLYevBKxAhEn8zHWmwRTqtXFJAuEiVW5EmT0Xyud\n qS5QpdP/rNHDPpoqYK3BCbkLuAfO8zBi5AI7c0GwHoMl+hQ/Ps7C6nE", "X-Developer-Key": "i=Andy.Chung@amd.com; a=ed25519;\n pk=X2gaHRnhU2q5hvMjkC6xmIcC03vKNvHY9CQRdsj9ecM=", "X-Endpoint-Received": "by B4 Relay for Andy.Chung@amd.com/20260327 with\n auth_id=696", "X-Original-From": "Andy Chung <Andy.Chung@amd.com>", "Reply-To": "Andy.Chung@amd.com", "X-Spam-Status": "No, score=-0.2 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED,\n\tDKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS\n\tautolearn=disabled version=4.0.1", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org" }, "content": "From: Andy Chung <Andy.Chung@amd.com>\n\nAdd the mctp-controller property to enable frontend NIC management\nvia PLDM over MCTP.\nAlso add EEPROM device for NIC FRU.\n\nSigned-off-by: Andy Chung <Andy.Chung@amd.com>\n---\nAdd the mctp-controller property to enable frontend NIC management\nvia PLDM over MCTP.\nAlso add EEPROM device for NIC FRU.\n---\n .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 67 +++++++++++++++++++++-\n 1 file changed, 65 insertions(+), 2 deletions(-)\n\n\n---\nbase-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f\nchange-id: 20260327-dts_enable_nic_mctp-e35a5765b176\n\nBest regards,\n-- \nAndy Chung <Andy.Chung@amd.com>", "diff": "diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts\nindex 221af858cb6b..138b081be049 100644\n--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts\n+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts\n@@ -584,38 +584,67 @@ eeprom@56 {\n // R Bridge Board\n &i2c10 {\n \tstatus = \"okay\";\n+\tmulti-master;\n+\tmctp@10 {\n+\t\tcompatible = \"mctp-i2c-controller\";\n+\t\treg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;\n+\t};\n \n \ti2c-mux@71 {\n \t\tcompatible = \"nxp,pca9548\";\n \t\treg = <0x71>;\n \t\t#address-cells = <1>;\n \t\t#size-cells = <0>;\n-\t\ti2c-mux-idle-disconnect;\n \n \t\ti2c10mux0ch0: i2c@0 {\n \t\t\treg = <0>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n+\t\t\tmctp-controller;\n \t\t};\n \t\ti2c10mux0ch1: i2c@1 {\n \t\t\treg = <1>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n+\t\t\tmctp-controller;\n+\t\t\t// BE NIC FRU\n+\t\t\teeprom@50 {\n+\t\t\t\tcompatible = \"atmel,24c32\";\n+\t\t\t\treg = <0x50>;\n+\t\t\t};\n \t\t};\n \t\ti2c10mux0ch2: i2c@2 {\n \t\t\treg = <2>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n+\t\t\tmctp-controller;\n+\t\t\t// BE NIC FRU\n+\t\t\teeprom@50 {\n+\t\t\t\tcompatible = \"atmel,24c32\";\n+\t\t\t\treg = <0x50>;\n+\t\t\t};\n \t\t};\n \t\ti2c10mux0ch3: i2c@3 {\n \t\t\treg = <3>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n+\t\t\tmctp-controller;\n+\t\t\t// BE NIC FRU\n+\t\t\teeprom@50 {\n+\t\t\t\tcompatible = \"atmel,24c32\";\n+\t\t\t\treg = <0x50>;\n+\t\t\t};\n \t\t};\n \t\ti2c10mux0ch4: i2c@4 {\n \t\t\treg = <4>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n+\t\t\tmctp-controller;\n+\t\t\t// BE NIC FRU\n+\t\t\teeprom@50 {\n+\t\t\t\tcompatible = \"atmel,24c32\";\n+\t\t\t\treg = <0x50>;\n+\t\t\t};\n \t\t};\n \t\ti2c10mux0ch5: i2c@5 {\n \t\t\treg = <5>;\n@@ -661,38 +690,72 @@ i2c10mux0ch7: i2c@7 {\n // L Bridge Board\n &i2c11 {\n \tstatus = \"okay\";\n+\tmulti-master;\n+\tmctp@10 {\n+\t\tcompatible = \"mctp-i2c-controller\";\n+\t\treg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;\n+\t};\n \n \ti2c-mux@71 {\n \t\tcompatible = \"nxp,pca9548\";\n \t\treg = <0x71>;\n \t\t#address-cells = <1>;\n \t\t#size-cells = <0>;\n-\t\ti2c-mux-idle-disconnect;\n \n \t\ti2c11mux0ch0: i2c@0 {\n \t\t\treg = <0>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n+\t\t\tmctp-controller;\n+\t\t\t// FE NIC FRU\n+\t\t\teeprom@50 {\n+\t\t\t\tcompatible = \"atmel,24c32\";\n+\t\t\t\treg = <0x50>;\n+\t\t\t};\n \t\t};\n \t\ti2c11mux0ch1: i2c@1 {\n \t\t\treg = <1>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n+\t\t\tmctp-controller;\n+\t\t\t// BE NIC FRU\n+\t\t\teeprom@50 {\n+\t\t\t\tcompatible = \"atmel,24c32\";\n+\t\t\t\treg = <0x50>;\n+\t\t\t};\n \t\t};\n \t\ti2c11mux0ch2: i2c@2 {\n \t\t\treg = <2>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n+\t\t\tmctp-controller;\n+\t\t\t// BE NIC FRU\n+\t\t\teeprom@50 {\n+\t\t\t\tcompatible = \"atmel,24c32\";\n+\t\t\t\treg = <0x50>;\n+\t\t\t};\n \t\t};\n \t\ti2c11mux0ch3: i2c@3 {\n \t\t\treg = <3>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n+\t\t\tmctp-controller;\n+\t\t\t// BE NIC FRU\n+\t\t\teeprom@50 {\n+\t\t\t\tcompatible = \"atmel,24c32\";\n+\t\t\t\treg = <0x50>;\n+\t\t\t};\n \t\t};\n \t\ti2c11mux0ch4: i2c@4 {\n \t\t\treg = <4>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n+\t\t\tmctp-controller;\n+\t\t\t// BE NIC FRU\n+\t\t\teeprom@50 {\n+\t\t\t\tcompatible = \"atmel,24c32\";\n+\t\t\t\treg = <0x50>;\n+\t\t\t};\n \t\t};\n \t\ti2c11mux0ch5: i2c@5 {\n \t\t\treg = <5>;\n", "prefixes": [] }