Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2217297/?format=api
{ "id": 2217297, "url": "http://patchwork.ozlabs.org/api/patches/2217297/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260327211649.3816010-1-dmatlack@google.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327211649.3816010-1-dmatlack@google.com>", "list_archive_url": null, "date": "2026-03-27T21:16:40", "name": "[v2] PCI: Disable ATS via quirk before notifying IOMMU drivers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fa2e51186f3cb3b4783057640b2ca8a4b60d6865", "submitter": { "id": 69449, "url": "http://patchwork.ozlabs.org/api/people/69449/?format=api", "name": "David Matlack", "email": "dmatlack@google.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260327211649.3816010-1-dmatlack@google.com/mbox/", "series": [ { "id": 497829, "url": "http://patchwork.ozlabs.org/api/series/497829/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497829", "date": "2026-03-27T21:16:40", "name": "[v2] PCI: Disable ATS via quirk before notifying IOMMU drivers", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497829/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217297/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217297/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51359-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256\n header.s=20251104 header.b=jerDzyr8;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-51359-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=google.com header.i=@google.com\n header.b=\"jerDzyr8\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.216.73", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=google.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=flex--dmatlack.bounces.google.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fjD9k3dr0z1y0D\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 28 Mar 2026 08:22:02 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 92599302D5E0\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 21:17:03 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 0173F37BE70;\n\tFri, 27 Mar 2026 21:17:03 +0000 (UTC)", "from mail-pj1-f73.google.com (mail-pj1-f73.google.com\n [209.85.216.73])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AB112D0620\n\tfor <linux-pci@vger.kernel.org>; Fri, 27 Mar 2026 21:17:01 +0000 (UTC)", "by mail-pj1-f73.google.com with SMTP id\n 98e67ed59e1d1-35c0bd3a968so2508436a91.0\n for <linux-pci@vger.kernel.org>; Fri, 27 Mar 2026 14:17:01 -0700 (PDT)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774646222; cv=none;\n b=UwZLCn9fA63+ie+bplasiZzx824QqS1VL+E3o+ELhk0pYoYiM/SrXiC+gmCxf0rm+ATwhu+5QM3VJHcNNvpbNXP01nSTwatgvI0N53lxigAktz845k4xUYdKQgRhvl6X2v1z1UzS8zQZCeODCjd3gNgyYci4vewTLyTOCs6pnqQ=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774646222; c=relaxed/simple;\n\tbh=GsELgrNxz8NysXFVGpuJJb49OBemyS6+o7WjbjUqBrQ=;\n\th=Date:Mime-Version:Message-ID:Subject:From:To:Cc:Content-Type;\n b=ZAad4l8fnjiMN9RkDoZG3AI9f20H3CZNU2iibHxIJTYMF7cWGBDvYtm2fjJXzYw47MipXx6vQwjNSTJgGpBNcO8ZiaSHKgaUfRaHh1DMH5ZFD4OZ//SSdoz3JCi5KyJI9dMTjaxkKJNpKKjuh7ZqXIWmS+rSYI0Et/NQFO1RVv4=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=google.com;\n spf=pass smtp.mailfrom=flex--dmatlack.bounces.google.com;\n dkim=pass (2048-bit key) header.d=google.com header.i=@google.com\n header.b=jerDzyr8; arc=none smtp.client-ip=209.85.216.73", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=google.com; s=20251104; t=1774646220; x=1775251020;\n darn=vger.kernel.org;\n h=cc:to:from:subject:message-id:mime-version:date:from:to:cc:subject\n :date:message-id:reply-to;\n bh=trO8rmzZPr0RQOymFCLZQOIxeJZ/gPQu+3jTXW69zB0=;\n b=jerDzyr8g1/PV3aJWcODRsQNtUbIg8oGt2n+6fr8SH6Hf8BPdCZwNUQ1aMMPtfdEyK\n FyEfAqAUbYaBZ6yztd/MscakCNR0Z1QGP1oLXmtDtQziASzCawx+zUHo9PqfatBj69+w\n Z+S6UNVtM3BeOLmLFuohDBrlLg0CgfvlB13yOGzEYTSHnL7Ccnklv6gW6eFQq2MiyV3h\n iYu060dZls0BwXizp3cpCrk6qg7sXTJkzF7kDe16idjvX5vNFXcmFablAcFQ+HN7UZ6B\n EbsObRyCDPbh6dk3X/EO9nu0QC9tqsKgWO8+ZNeo+wz161l1iqv+l049BLOmh9SZUIvL\n fkbA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774646220; x=1775251020;\n h=cc:to:from:subject:message-id:mime-version:date:x-gm-message-state\n :from:to:cc:subject:date:message-id:reply-to;\n bh=trO8rmzZPr0RQOymFCLZQOIxeJZ/gPQu+3jTXW69zB0=;\n b=mV1Sshpu5AX9dXpFHJSN2PKIO2KJr/2YPN097cpI/sOdF320nxrIcDwcTkQonTeR/D\n 2C/6/5aP6OK1a4WKyGMgoBuHGZupi018P2nGpq/i45I7w08HoCjkiBVubDuqgs/uOwft\n eX7bRbJh3y707BzNmFo8RrBgy1XxTRhMNw2T+yJJPYNwmiwiVo/uAY2EWXSoqKgIJZDw\n dYoe/RdGWtCtIeag2hoDUkGo5/X2qIlsVc2MRiKXkY6RBpKXf2SXZTmqNJxUJjFS5gRd\n 1ttDJZv0Q5l+Gh41Uvrm8IjpdJlomQ1lR/YapvEub0/0FRsR/xijIErfsFh8w2CqSauC\n gzFw==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCVBeWr+s4zlQ0iTli7EGs5wdL6PWayObDeCOnemP8RE7uQYfOpAsVJfwrOxxQ+pkfgICLnqLd19918=@vger.kernel.org", "X-Gm-Message-State": "AOJu0YzYnZ5RMYNzKuzEKUVnsNbR3NdteUQL4bRZxlwP+S4DEEty+t58\n\tKcEXawKQ4Q6ep+k7Fvep+X6iaHB+l2Gj+i/cmbN67fee87TXY9cLvvMvTgCOh+bMc+l1vlj9K46\n\tfCF7SyqFX2lvzgA==", "X-Received": "from pjbpv14.prod.google.com\n ([2002:a17:90b:3c8e:b0:35c:2b6d:7890])\n (user=dmatlack job=prod-delivery.src-stubby-dispatcher) by\n 2002:a17:90b:4cc6:b0:35b:e4f8:7cb0 with SMTP id\n 98e67ed59e1d1-35c300c19c4mr3887836a91.21.1774646220375;\n Fri, 27 Mar 2026 14:17:00 -0700 (PDT)", "Date": "Fri, 27 Mar 2026 21:16:40 +0000", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "Mime-Version": "1.0", "X-Mailer": "git-send-email 2.53.0.1018.g2bb0e51243-goog", "Message-ID": "<20260327211649.3816010-1-dmatlack@google.com>", "Subject": "[PATCH v2] PCI: Disable ATS via quirk before notifying IOMMU drivers", "From": "David Matlack <dmatlack@google.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>", "Cc": "Alexander Lobakin <aleksander.lobakin@intel.com>,\n\tAndy Shevchenko <andriy.shevchenko@linux.intel.com>,\n\tBartosz Pawlowski <bartosz.pawlowski@intel.com>,\n David Woodhouse <dwmw2@infradead.org>,\n\tlinux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n\tLu Baolu <baolu.lu@linux.intel.com>,\n Raghavendra Rao Ananta <rananta@google.com>,\n\tDavid Matlack <dmatlack@google.com>", "Content-Type": "text/plain; charset=\"UTF-8\"" }, "content": "Ensure that PCI devices with ATS disabled via quirk have it disabled\nbefore IOMMU drivers are notified about the device rather than after.\nFix this by converting the existing quirks from final to early fixups\nand changing the quirk logic to set a new no_ats bit in struct pci_dev\nthat prevents pci_dev.ats_cap from ever gettting set.\n\nThis change ensures that pci_ats_supported() takes quirks into account\nduring iommu_ops.probe_device(), when IOMMU drivers are first notified\nabout devices. It also ensures that pci_ats_supported() returns the same\nvalue when the device is released in iommu_ops.release_device().\n\nNotably, the Intel IOMMU driver uses pci_ats_supported() in\nprobe/release to determine whether to add/remove a device from a data\nstructure, which easily leads to a use-after-free without this fix.\n\nThis change also makes disabling ATS via quirk behave the same way as\nthe pci=noats command line option, in that pci_ats_init() bails\nimmediately and never intializes pci_dev.ats_cap.\n\nFixes: a18615b1cfc0 (\"PCI: Disable ATS for specific Intel IPU E2000 devices\")\nCloses: https://lore.kernel.org/linux-iommu/aYUQ_HkDJU9kjsUl@google.com/\nSigned-off-by: David Matlack <dmatlack@google.com>\n---\nv2:\n - Update the commit message with reasons why this is being fixed in the\n PCI core, rather than applying a point fix to the Intel IOMMU driver\n (Andy)\n - Condense the pci_ats_disabled() and dev->no_ats checks into a single\n line in pci_ats_init()\n - Reorder the no_ats bitfield to be after ats_stu since there is likely\n u8-sized gap there for alignment purposes\n\nv1: https://lore.kernel.org/linux-pci/20260223184017.688212-1-dmatlack@google.com/\n\nCc: Raghavendra Rao Ananta <rananta@google.com>\nCc: David Woodhouse <dwmw2@infradead.org>\nCc: Lu Baolu <baolu.lu@linux.intel.com>\nCc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>\n\n drivers/pci/ats.c | 2 +-\n drivers/pci/quirks.c | 50 ++++++++++++++++++++++----------------------\n include/linux/pci.h | 1 +\n 3 files changed, 27 insertions(+), 26 deletions(-)\n\n\nbase-commit: 7df48e36313029e4c0907b2023905dd7213fd678", "diff": "diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c\nindex ec6c8dbdc5e9..ceb6f5d3cb10 100644\n--- a/drivers/pci/ats.c\n+++ b/drivers/pci/ats.c\n@@ -21,7 +21,7 @@ void pci_ats_init(struct pci_dev *dev)\n {\n \tint pos;\n \n-\tif (pci_ats_disabled())\n+\tif (pci_ats_disabled() || dev->no_ats)\n \t\treturn;\n \n \tpos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);\ndiff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\nindex 48946cca4be7..2c7e11830e45 100644\n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -5653,7 +5653,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);\n static void quirk_no_ats(struct pci_dev *pdev)\n {\n \tpci_info(pdev, \"disabling ATS\\n\");\n-\tpdev->ats_cap = 0;\n+\tpdev->no_ats = 1;\n }\n \n /*\n@@ -5676,25 +5676,25 @@ static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)\n }\n \n /* AMD Stoney platform GPU */\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);\n /* AMD Iceland dGPU */\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);\n /* AMD Navi10 dGPU */\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);\n /* AMD Navi14 dGPU */\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);\n /* AMD Raven platform iGPU */\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);\n \n /*\n * Intel IPU E2000 revisions before C0 implement incorrect endianness\n@@ -5705,15 +5705,15 @@ static void quirk_intel_e2000_no_ats(struct pci_dev *pdev)\n \tif (pdev->revision < 0x20)\n \t\tquirk_no_ats(pdev);\n }\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);\n-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);\n #endif /* CONFIG_PCI_ATS */\n \n /* Freescale PCIe doesn't support MSI in RC mode */\ndiff --git a/include/linux/pci.h b/include/linux/pci.h\nindex 1c270f1d5123..850100f209e3 100644\n--- a/include/linux/pci.h\n+++ b/include/linux/pci.h\n@@ -539,6 +539,7 @@ struct pci_dev {\n \t};\n \tu16\t\tats_cap;\t/* ATS Capability offset */\n \tu8\t\tats_stu;\t/* ATS Smallest Translation Unit */\n+\tunsigned int\tno_ats:1;\t/* ATS disabled via quirk */\n #endif\n #ifdef CONFIG_PCI_PRI\n \tu16\t\tpri_cap;\t/* PRI Capability offset */\n", "prefixes": [ "v2" ] }