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GET /api/patches/2217287/?format=api
{ "id": 2217287, "url": "http://patchwork.ozlabs.org/api/patches/2217287/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260327200932.2016910-5-james.hilliard1@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327200932.2016910-5-james.hilliard1@gmail.com>", "list_archive_url": null, "date": "2026-03-27T20:09:16", "name": "[v4,5/5] sunxi: h616: support a default DRAM profile from the device tree", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6e26e19a8f411605d211538655984c6f23699ce5", "submitter": { "id": 66301, "url": "http://patchwork.ozlabs.org/api/people/66301/?format=api", "name": "James Hilliard", "email": "james.hilliard1@gmail.com" }, "delegate": { "id": 114289, "url": "http://patchwork.ozlabs.org/api/users/114289/?format=api", "username": "apritzel", "first_name": "Andre", "last_name": "Przywara", "email": "andre.przywara@arm.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260327200932.2016910-5-james.hilliard1@gmail.com/mbox/", "series": [ { "id": 497825, "url": "http://patchwork.ozlabs.org/api/series/497825/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497825", "date": "2026-03-27T20:09:12", "name": "[v4,1/5] sunxi: h616: make ns_to_t() use the DRAM clock", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/497825/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217287/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217287/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=M0AMeU1D;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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This provides the\nsimplest device-tree-driven parameter flow for boards that need runtime\nselection later, while keeping the existing fixed-profile path in the\nmain H616 driver.\n\nAdd a small device-tree DRAM parameter loader for the default profile\nand use hidden H616 backend symbols so fixed-profile mode builds one\nbackend while device-tree profile mode builds all of them, without\nreusing the visible timing choice symbols as build plumbing. Also make\nSUNXI_DRAM_FIXED_PARAMS a derived hidden symbol so the fixed H616 timing\nchoice and H616 fixed-parameter prompts are hidden automatically when\ndevice-tree profiles are enabled.\n\nSigned-off-by: James Hilliard <james.hilliard1@gmail.com>\n---\n .../include/asm/arch-sunxi/dram_sun50i_h616.h | 31 ++++++-\n arch/arm/mach-sunxi/Kconfig | 78 +++++++++++++---\n arch/arm/mach-sunxi/Makefile | 1 +\n arch/arm/mach-sunxi/dram_sun50i_h616.c | 55 +++++++----\n arch/arm/mach-sunxi/dram_sun50i_h616_dt.c | 93 +++++++++++++++++++\n arch/arm/mach-sunxi/dram_timings/Makefile | 6 +-\n 6 files changed, 227 insertions(+), 37 deletions(-)\n create mode 100644 arch/arm/mach-sunxi/dram_sun50i_h616_dt.c", "diff": "diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h\nindex 6dab3b4832b..9593409b465 100644\n--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h\n+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h\n@@ -170,6 +170,8 @@ struct dram_config {\n \n #define H616_PHY_INIT_LEN\t27\n \n+void h616_get_dram_para_dt(struct dram_para *para);\n+\n static inline int ns_to_t(const struct dram_para *para, int nanoseconds)\n {\n \tconst unsigned int ctrl_freq = para->clk / 2;\n@@ -187,6 +189,22 @@ const u8 *h616_lpddr4_get_phy_init(void);\n \n static inline void mctl_set_timing_params(const struct dram_para *para)\n {\n+\tif (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_DT_PROFILE)) {\n+\t\tswitch (para->type) {\n+\t\tcase SUNXI_DRAM_TYPE_DDR3:\n+\t\t\th616_ddr3_set_timing_params(para);\n+\t\t\treturn;\n+\t\tcase SUNXI_DRAM_TYPE_LPDDR3:\n+\t\t\th616_lpddr3_set_timing_params(para);\n+\t\t\treturn;\n+\t\tcase SUNXI_DRAM_TYPE_LPDDR4:\n+\t\t\th616_lpddr4_set_timing_params(para);\n+\t\t\treturn;\n+\t\tdefault:\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n #ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333\n \th616_ddr3_set_timing_params(para);\n #elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)\n@@ -198,7 +216,18 @@ static inline void mctl_set_timing_params(const struct dram_para *para)\n \n static inline const u8 *h616_get_phy_init(const struct dram_para *para)\n {\n-\t(void)para;\n+\tif (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_DT_PROFILE)) {\n+\t\tswitch (para->type) {\n+\t\tcase SUNXI_DRAM_TYPE_DDR3:\n+\t\t\treturn h616_ddr3_get_phy_init();\n+\t\tcase SUNXI_DRAM_TYPE_LPDDR3:\n+\t\t\treturn h616_lpddr3_get_phy_init();\n+\t\tcase SUNXI_DRAM_TYPE_LPDDR4:\n+\t\t\treturn h616_lpddr4_get_phy_init();\n+\t\tdefault:\n+\t\t\treturn NULL;\n+\t\t}\n+\t}\n \n #ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333\n \treturn h616_ddr3_get_phy_init();\ndiff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig\nindex e979ee4a2cc..e403ef67a0b 100644\n--- a/arch/arm/mach-sunxi/Kconfig\n+++ b/arch/arm/mach-sunxi/Kconfig\n@@ -62,24 +62,74 @@ config DRAM_SUN55I_A523\n \thelp\n \t Select this DRAM controller driver for A523/T527 SoCs.\n \n+if DRAM_SUN50I_H616\n+choice\n+\tprompt \"H616 DRAM profile source\"\n+\tdefault SUNXI_DRAM_H616_FIXED_PROFILE\n+\thelp\n+\t Select whether SPL uses the fixed H616 Kconfig DRAM settings or\n+\t loads a default H616 DRAM profile from the device tree at boot.\n+\n+config SUNXI_DRAM_H616_FIXED_PROFILE\n+\tbool \"Fixed build-time DRAM profile\"\n+\thelp\n+\t Use a single H616 DRAM profile selected at build time.\n+\t This keeps the existing Kconfig-based timing selection flow.\n+\n+config DRAM_SUN50I_H616_DT_PROFILE\n+\tbool \"Default device tree DRAM profile\"\n+\tselect OF_CONTROL\n+\tselect SPL_OF_CONTROL\n+\thelp\n+\t Load the H616 DRAM parameters from /dram-profiles/default in the\n+\t U-Boot device tree at boot.\n+\n+\t The node must provide the H616 DRAM parameters used by the driver,\n+\t including dram-type.\n+endchoice\n+\n+config SUNXI_DRAM_H616_BACKEND_DDR3\n+\tbool\n+\tdefault y if DRAM_SUN50I_H616_DT_PROFILE\n+\tdefault y if SUNXI_DRAM_H616_DDR3_1333\n+\n+config SUNXI_DRAM_H616_BACKEND_LPDDR3\n+\tbool\n+\tdefault y if DRAM_SUN50I_H616_DT_PROFILE\n+\tdefault y if SUNXI_DRAM_H616_LPDDR3\n+\n+config SUNXI_DRAM_H616_BACKEND_LPDDR4\n+\tbool\n+\tdefault y if DRAM_SUN50I_H616_DT_PROFILE\n+\tdefault y if SUNXI_DRAM_H616_LPDDR4\n+endif\n+\n+config SUNXI_DRAM_FIXED_PARAMS\n+\tbool\n+\tdefault y if !DRAM_SUN50I_H616\n+\tdefault y if DRAM_SUN50I_H616 && SUNXI_DRAM_H616_FIXED_PROFILE\n+\n if DRAM_SUN50I_H616 || DRAM_SUN50I_A133 || DRAM_SUN55I_A523\n config DRAM_SUNXI_DX_ODT\n-\thex \"DRAM DX ODT parameter\"\n+\thex \"DRAM DX ODT parameter\" if SUNXI_DRAM_FIXED_PARAMS\n+\tdefault 0x0 if !SUNXI_DRAM_FIXED_PARAMS\n \thelp\n \t DX ODT value from vendor DRAM settings.\n \n config DRAM_SUNXI_DX_DRI\n-\thex \"DRAM DX DRI parameter\"\n+\thex \"DRAM DX DRI parameter\" if SUNXI_DRAM_FIXED_PARAMS\n+\tdefault 0x0 if !SUNXI_DRAM_FIXED_PARAMS\n \thelp\n \t DX DRI value from vendor DRAM settings.\n \n config DRAM_SUNXI_CA_DRI\n-\thex \"DRAM CA DRI parameter\"\n+\thex \"DRAM CA DRI parameter\" if SUNXI_DRAM_FIXED_PARAMS\n+\tdefault 0x0 if !SUNXI_DRAM_FIXED_PARAMS\n \thelp\n \t CA DRI value from vendor DRAM settings.\n \n config DRAM_SUNXI_ODT_EN\n-\thex \"DRAM ODT EN parameter\"\n+\thex \"DRAM ODT EN parameter\" if SUNXI_DRAM_FIXED_PARAMS\n \tdefault 0x1\n \thelp\n \t ODT EN value from vendor DRAM settings.\n@@ -119,49 +169,50 @@ config DRAM_SUNXI_MR14\n \t MR14 value from vendor DRAM settings.\n \n config DRAM_SUNXI_TPR0\n-\thex \"DRAM TPR0 parameter\"\n+\thex \"DRAM TPR0 parameter\" if SUNXI_DRAM_FIXED_PARAMS\n \tdefault 0x0\n \thelp\n \t TPR0 value from vendor DRAM settings.\n \n config DRAM_SUNXI_TPR1\n-\thex \"DRAM TPR1 parameter\"\n+\thex \"DRAM TPR1 parameter\" if SUNXI_DRAM_FIXED_PARAMS\n \tdefault 0x0\n \thelp\n \t TPR1 value from vendor DRAM settings.\n \n config DRAM_SUNXI_TPR2\n-\thex \"DRAM TPR2 parameter\"\n+\thex \"DRAM TPR2 parameter\" if SUNXI_DRAM_FIXED_PARAMS\n \tdefault 0x0\n \thelp\n \t TPR2 value from vendor DRAM settings.\n \n config DRAM_SUNXI_TPR3\n-\thex \"DRAM TPR3 parameter\"\n+\thex \"DRAM TPR3 parameter\" if SUNXI_DRAM_FIXED_PARAMS\n \tdefault 0x0\n \thelp\n \t TPR3 value from vendor DRAM settings.\n \n config DRAM_SUNXI_TPR6\n-\thex \"DRAM TPR6 parameter\"\n+\thex \"DRAM TPR6 parameter\" if SUNXI_DRAM_FIXED_PARAMS\n \tdefault 0x3300c080\n \thelp\n \t TPR6 value from vendor DRAM settings.\n \n config DRAM_SUNXI_TPR10\n-\thex \"DRAM TPR10 parameter\"\n+\thex \"DRAM TPR10 parameter\" if SUNXI_DRAM_FIXED_PARAMS\n+\tdefault 0x0 if !SUNXI_DRAM_FIXED_PARAMS\n \thelp\n \t TPR10 value from vendor DRAM settings. It tells which features\n \t should be configured, like write leveling, read calibration, etc.\n \n config DRAM_SUNXI_TPR11\n-\thex \"DRAM TPR11 parameter\"\n+\thex \"DRAM TPR11 parameter\" if SUNXI_DRAM_FIXED_PARAMS\n \tdefault 0x0\n \thelp\n \t TPR11 value from vendor DRAM settings.\n \n config DRAM_SUNXI_TPR12\n-\thex \"DRAM TPR12 parameter\"\n+\thex \"DRAM TPR12 parameter\" if SUNXI_DRAM_FIXED_PARAMS\n \tdefault 0x0\n \thelp\n \t TPR12 value from vendor DRAM settings.\n@@ -608,6 +659,7 @@ config SUNXI_DRAM_DDR4\n \n choice\n \tprompt \"DRAM Type and Timing\"\n+\tdepends on SUNXI_DRAM_FIXED_PARAMS\n \tdefault SUNXI_DRAM_A523_LPDDR4 if MACH_SUN55I_A523\n \tdefault SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S\n \tdefault SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S\n@@ -718,7 +770,7 @@ config DRAM_TYPE\n \tSet the dram type, 3: DDR3, 7: LPDDR3\n \n config DRAM_CLK\n-\tint \"sunxi dram clock speed\"\n+\tint \"sunxi dram clock speed\" if SUNXI_DRAM_FIXED_PARAMS\n \tdefault 792 if MACH_SUN9I\n \tdefault 648 if MACH_SUN8I_R40\n \tdefault 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \\\ndiff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile\nindex 9c79b55abf3..862386cf6f0 100644\n--- a/arch/arm/mach-sunxi/Makefile\n+++ b/arch/arm/mach-sunxi/Makefile\n@@ -44,6 +44,7 @@ obj-$(CONFIG_SUNXI_DRAM_DW)\t+= dram_timings/\n obj-$(CONFIG_DRAM_SUN50I_H6)\t+= dram_sun50i_h6.o dram_dw_helpers.o\n obj-$(CONFIG_DRAM_SUN50I_H6)\t+= dram_timings/\n obj-$(CONFIG_DRAM_SUN50I_H616)\t+= dram_sun50i_h616.o dram_dw_helpers.o\n+obj-$(CONFIG_DRAM_SUN50I_H616_DT_PROFILE) += dram_sun50i_h616_dt.o\n obj-$(CONFIG_DRAM_SUN50I_H616)\t+= dram_timings/\n obj-$(CONFIG_DRAM_SUN50I_A133)\t+= dram_sun50i_a133.o\n obj-$(CONFIG_DRAM_SUN50I_A133)\t+= dram_timings/\ndiff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c\nindex c3e1286fb35..96d84398eee 100644\n--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c\n+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c\n@@ -1281,33 +1281,48 @@ bool mctl_core_init(const struct dram_para *para,\n \treturn mctl_ctrl_init(para, config);\n }\n \n-static const struct dram_para para = {\n-\t.clk = CONFIG_DRAM_CLK,\n-#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333\n-\t.type = SUNXI_DRAM_TYPE_DDR3,\n-#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)\n-\t.type = SUNXI_DRAM_TYPE_LPDDR3,\n-#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)\n-\t.type = SUNXI_DRAM_TYPE_LPDDR4,\n-#endif\n-\t.dx_odt = CONFIG_DRAM_SUNXI_DX_ODT,\n-\t.dx_dri = CONFIG_DRAM_SUNXI_DX_DRI,\n-\t.ca_dri = CONFIG_DRAM_SUNXI_CA_DRI,\n-\t.odt_en = CONFIG_DRAM_SUNXI_ODT_EN,\n-\t.tpr0 = CONFIG_DRAM_SUNXI_TPR0,\n-\t.tpr2 = CONFIG_DRAM_SUNXI_TPR2,\n-\t.tpr6 = CONFIG_DRAM_SUNXI_TPR6,\n-\t.tpr10 = CONFIG_DRAM_SUNXI_TPR10,\n-\t.tpr11 = CONFIG_DRAM_SUNXI_TPR11,\n-\t.tpr12 = CONFIG_DRAM_SUNXI_TPR12,\n-};\n+static enum sunxi_dram_type h616_get_fixed_dram_type(void)\n+{\n+\tif (IS_ENABLED(CONFIG_SUNXI_DRAM_H616_DDR3_1333))\n+\t\treturn SUNXI_DRAM_TYPE_DDR3;\n+\tif (IS_ENABLED(CONFIG_SUNXI_DRAM_H616_LPDDR3))\n+\t\treturn SUNXI_DRAM_TYPE_LPDDR3;\n+\tif (IS_ENABLED(CONFIG_SUNXI_DRAM_H616_LPDDR4))\n+\t\treturn SUNXI_DRAM_TYPE_LPDDR4;\n+\n+\tpanic(\"No fixed H616 DRAM type selected\\n\");\n+}\n+\n+static void h616_get_fixed_dram_para(struct dram_para *para)\n+{\n+\t*para = (struct dram_para) {\n+\t\t.clk = CONFIG_DRAM_CLK,\n+\t\t.type = h616_get_fixed_dram_type(),\n+\t\t.dx_odt = CONFIG_DRAM_SUNXI_DX_ODT,\n+\t\t.dx_dri = CONFIG_DRAM_SUNXI_DX_DRI,\n+\t\t.ca_dri = CONFIG_DRAM_SUNXI_CA_DRI,\n+\t\t.odt_en = CONFIG_DRAM_SUNXI_ODT_EN,\n+\t\t.tpr0 = CONFIG_DRAM_SUNXI_TPR0,\n+\t\t.tpr2 = CONFIG_DRAM_SUNXI_TPR2,\n+\t\t.tpr6 = CONFIG_DRAM_SUNXI_TPR6,\n+\t\t.tpr10 = CONFIG_DRAM_SUNXI_TPR10,\n+\t\t.tpr11 = CONFIG_DRAM_SUNXI_TPR11,\n+\t\t.tpr12 = CONFIG_DRAM_SUNXI_TPR12,\n+\t};\n+}\n \n unsigned long sunxi_dram_init(void)\n {\n \tvoid *const prcm = (void *)SUNXI_PRCM_BASE;\n+\tstruct dram_para para;\n \tstruct dram_config config;\n \tunsigned long size;\n \n+\tif (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_DT_PROFILE))\n+\t\th616_get_dram_para_dt(¶);\n+\telse\n+\t\th616_get_fixed_dram_para(¶);\n+\n \tsetbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, BIT(8));\n \tclrbits_le32(prcm + CCU_PRCM_OHMS240, 0x3f);\n \ndiff --git a/arch/arm/mach-sunxi/dram_sun50i_h616_dt.c b/arch/arm/mach-sunxi/dram_sun50i_h616_dt.c\nnew file mode 100644\nindex 00000000000..2620e24b41a\n--- /dev/null\n+++ b/arch/arm/mach-sunxi/dram_sun50i_h616_dt.c\n@@ -0,0 +1,93 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * H616 DRAM parameter loading from the device tree\n+ */\n+\n+#include <errno.h>\n+#include <vsprintf.h>\n+#include <asm/global_data.h>\n+#include <asm/arch/dram.h>\n+#include <linux/libfdt.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static int h616_fdt_read_u32(const void *blob, int node, const char *prop_name,\n+\t\t\t u32 *val)\n+{\n+\tconst fdt32_t *prop;\n+\tint len;\n+\n+\tprop = fdt_getprop(blob, node, prop_name, &len);\n+\tif (!prop || len != sizeof(*prop))\n+\t\treturn -EINVAL;\n+\n+\t*val = fdt32_to_cpu(*prop);\n+\n+\treturn 0;\n+}\n+\n+static int h616_get_dram_type(u32 val, enum sunxi_dram_type *type)\n+{\n+\tswitch (val) {\n+\tcase SUNXI_DRAM_TYPE_DDR3:\n+\tcase SUNXI_DRAM_TYPE_LPDDR3:\n+\tcase SUNXI_DRAM_TYPE_LPDDR4:\n+\t\t*type = val;\n+\t\treturn 0;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static int h616_parse_dram_para(const void *blob, int node,\n+\t\t\t\tstruct dram_para *para)\n+{\n+\tu32 val;\n+\n+\tif (h616_fdt_read_u32(blob, node, \"allwinner,dram-clk\", ¶->clk))\n+\t\treturn -EINVAL;\n+\tif (h616_fdt_read_u32(blob, node, \"allwinner,dram-type\", &val))\n+\t\treturn -EINVAL;\n+\tif (h616_get_dram_type(val, ¶->type))\n+\t\treturn -EINVAL;\n+\tif (h616_fdt_read_u32(blob, node, \"allwinner,dx-odt\", ¶->dx_odt))\n+\t\treturn -EINVAL;\n+\tif (h616_fdt_read_u32(blob, node, \"allwinner,dx-dri\", ¶->dx_dri))\n+\t\treturn -EINVAL;\n+\tif (h616_fdt_read_u32(blob, node, \"allwinner,ca-dri\", ¶->ca_dri))\n+\t\treturn -EINVAL;\n+\tif (h616_fdt_read_u32(blob, node, \"allwinner,odt-en\", ¶->odt_en))\n+\t\treturn -EINVAL;\n+\tif (h616_fdt_read_u32(blob, node, \"allwinner,tpr0\", ¶->tpr0))\n+\t\treturn -EINVAL;\n+\tif (h616_fdt_read_u32(blob, node, \"allwinner,tpr2\", ¶->tpr2))\n+\t\treturn -EINVAL;\n+\tif (h616_fdt_read_u32(blob, node, \"allwinner,tpr6\", ¶->tpr6))\n+\t\treturn -EINVAL;\n+\tif (h616_fdt_read_u32(blob, node, \"allwinner,tpr10\", ¶->tpr10))\n+\t\treturn -EINVAL;\n+\tif (h616_fdt_read_u32(blob, node, \"allwinner,tpr11\", ¶->tpr11))\n+\t\treturn -EINVAL;\n+\tif (h616_fdt_read_u32(blob, node, \"allwinner,tpr12\", ¶->tpr12))\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+void h616_get_dram_para_dt(struct dram_para *para)\n+{\n+\tconst void *blob = gd->fdt_blob;\n+\tint node, profiles, ret;\n+\n+\tprofiles = fdt_path_offset(blob, \"/dram-profiles\");\n+\tif (profiles < 0)\n+\t\tpanic(\"H616 DT DRAM profile selection failed: %d\\n\", profiles);\n+\n+\tnode = fdt_subnode_offset(blob, profiles, \"default\");\n+\tif (node < 0)\n+\t\tpanic(\"H616 DT DRAM profile selection failed: %d\\n\", node);\n+\n+\tret = h616_parse_dram_para(blob, node, para);\n+\tif (ret)\n+\t\tpanic(\"H616 DT DRAM profile selection failed: %d\\n\", ret);\n+}\ndiff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile\nindex 5de9fd5aab4..165f6123cb4 100644\n--- a/arch/arm/mach-sunxi/dram_timings/Makefile\n+++ b/arch/arm/mach-sunxi/dram_timings/Makefile\n@@ -3,9 +3,9 @@ obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK)\t+= lpddr3_stock.o\n obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S)\t+= ddr2_v3s.o\n obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3)\t+= h6_lpddr3.o\n obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333)\t+= h6_ddr3_1333.o\n-obj-$(CONFIG_SUNXI_DRAM_H616_DDR3_1333)\t+= h616_ddr3_1333.o\n-obj-$(CONFIG_SUNXI_DRAM_H616_LPDDR3)\t+= h616_lpddr3.o\n-obj-$(CONFIG_SUNXI_DRAM_H616_LPDDR4)\t+= h616_lpddr4_2133.o\n+obj-$(CONFIG_SUNXI_DRAM_H616_BACKEND_DDR3) += h616_ddr3_1333.o\n+obj-$(CONFIG_SUNXI_DRAM_H616_BACKEND_LPDDR3) += h616_lpddr3.o\n+obj-$(CONFIG_SUNXI_DRAM_H616_BACKEND_LPDDR4) += h616_lpddr4_2133.o\n obj-$(CONFIG_SUNXI_DRAM_A133_DDR4)\t+= a133_ddr4.o\n obj-$(CONFIG_SUNXI_DRAM_A133_LPDDR4)\t+= a133_lpddr4.o\n obj-$(CONFIG_SUNXI_DRAM_A523_DDR3)\t+= a523_ddr3.o\n", "prefixes": [ "v4", "5/5" ] }