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GET /api/patches/2217285/?format=api
{ "id": 2217285, "url": "http://patchwork.ozlabs.org/api/patches/2217285/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260327200932.2016910-3-james.hilliard1@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327200932.2016910-3-james.hilliard1@gmail.com>", "list_archive_url": null, "date": "2026-03-27T20:09:14", "name": "[v4,3/5] sunxi: h616: split timing and PHY init helpers by DRAM type", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1c3a6528201d28f8bb2aca29fa449dfc09987ac1", "submitter": { "id": 66301, "url": "http://patchwork.ozlabs.org/api/people/66301/?format=api", "name": "James Hilliard", "email": "james.hilliard1@gmail.com" }, "delegate": { "id": 114289, "url": "http://patchwork.ozlabs.org/api/users/114289/?format=api", "username": "apritzel", "first_name": "Andre", "last_name": "Przywara", "email": "andre.przywara@arm.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260327200932.2016910-3-james.hilliard1@gmail.com/mbox/", "series": [ { "id": 497825, "url": "http://patchwork.ozlabs.org/api/series/497825/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497825", "date": "2026-03-27T20:09:12", "name": "[v4,1/5] sunxi: h616: make ns_to_t() use the DRAM clock", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/497825/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217285/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217285/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", 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5614622812f47-46a7aa0c450mr2683421b6e.26.1774642200878;\n Fri, 27 Mar 2026 13:10:00 -0700 (PDT)", "From": "James Hilliard <james.hilliard1@gmail.com>", "To": "u-boot@lists.denx.de", "Cc": "James Hilliard <james.hilliard1@gmail.com>,\n Andre Przywara <andre.przywara@arm.com>, Tom Rini <trini@konsulko.com>,\n Jernej Skrabec <jernej.skrabec@gmail.com>,\n Paul Kocialkowski <contact@paulk.fr>,\n \"Kory Maincent (TI.com)\" <kory.maincent@bootlin.com>,\n Simon Glass <sjg@chromium.org>,\n Richard Genoud <richard.genoud@bootlin.com>,\n Alexander Graf <agraf@csgraf.de>, Cody Eksal <masterr3c0rd@epochal.quest>,\n Samuel Holland <samuel@sholland.org>,\n Mikhail Kalashnikov <iuncuim@gmail.com>", "Subject": "[PATCH v4 3/5] sunxi: h616: split timing and PHY init helpers by DRAM\n type", "Date": "Fri, 27 Mar 2026 14:09:14 -0600", "Message-ID": "<20260327200932.2016910-3-james.hilliard1@gmail.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327200932.2016910-1-james.hilliard1@gmail.com>", "References": "<20260327200932.2016910-1-james.hilliard1@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Give each H616 timing file its own timing entry point and PHY\ninitialisation accessor, then dispatch to them through inline\nhelpers in the H616 header.\n\nThis keeps the current fixed-profile build model intact while\nmaking the common H616 code consume DRAM-type-specific helpers\nthrough a uniform interface.\n\nSigned-off-by: James Hilliard <james.hilliard1@gmail.com>\n---\n .../include/asm/arch-sunxi/dram_sun50i_h616.h | 34 +++++++++++++++++--\n arch/arm/mach-sunxi/dram_sun50i_h616.c | 1 +\n .../mach-sunxi/dram_timings/h616_ddr3_1333.c | 12 ++++---\n .../arm/mach-sunxi/dram_timings/h616_lpddr3.c | 12 ++++---\n .../dram_timings/h616_lpddr4_2133.c | 12 ++++---\n 5 files changed, 57 insertions(+), 14 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h\nindex fa12d5d2685..6dab3b4832b 100644\n--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h\n+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h\n@@ -177,7 +177,37 @@ static inline int ns_to_t(const struct dram_para *para, int nanoseconds)\n \treturn DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);\n }\n \n-extern const u8 *phy_init;\n-void mctl_set_timing_params(const struct dram_para *para);\n+void h616_ddr3_set_timing_params(const struct dram_para *para);\n+void h616_lpddr3_set_timing_params(const struct dram_para *para);\n+void h616_lpddr4_set_timing_params(const struct dram_para *para);\n+\n+const u8 *h616_ddr3_get_phy_init(void);\n+const u8 *h616_lpddr3_get_phy_init(void);\n+const u8 *h616_lpddr4_get_phy_init(void);\n+\n+static inline void mctl_set_timing_params(const struct dram_para *para)\n+{\n+#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333\n+\th616_ddr3_set_timing_params(para);\n+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)\n+\th616_lpddr3_set_timing_params(para);\n+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)\n+\th616_lpddr4_set_timing_params(para);\n+#endif\n+}\n+\n+static inline const u8 *h616_get_phy_init(const struct dram_para *para)\n+{\n+\t(void)para;\n+\n+#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333\n+\treturn h616_ddr3_get_phy_init();\n+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)\n+\treturn h616_lpddr3_get_phy_init();\n+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)\n+\treturn h616_lpddr4_get_phy_init();\n+#endif\n+\treturn NULL;\n+}\n \n #endif /* _SUNXI_DRAM_SUN50I_H616_H */\ndiff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c\nindex 5ee1ca25311..c3e1286fb35 100644\n--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c\n+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c\n@@ -869,6 +869,7 @@ static bool mctl_phy_init(const struct dram_para *para,\n \t\t\t(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;\n \tstruct sunxi_mctl_ctl_reg * const mctl_ctl =\n \t\t\t(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;\n+\tconst u8 *phy_init = h616_get_phy_init(para);\n \tu32 val, val2, *ptr, mr0, mr2;\n \tint i;\n \ndiff --git a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c\nindex f367f604d5f..20c90f20cb9 100644\n--- a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c\n+++ b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c\n@@ -28,11 +28,15 @@ static const u8 h616_ddr3_phy_init_addr_map_1[H616_PHY_INIT_LEN] = {\n \t0x06, 0x09, 0x0f\n };\n \n-const u8 *phy_init = IS_ENABLED(CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1) ?\n-\t\t h616_ddr3_phy_init_addr_map_1 :\n-\t\t h616_ddr3_phy_init_default;\n+const u8 *h616_ddr3_get_phy_init(void)\n+{\n+\tif (IS_ENABLED(CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1))\n+\t\treturn h616_ddr3_phy_init_addr_map_1;\n+\n+\treturn h616_ddr3_phy_init_default;\n+}\n \n-void mctl_set_timing_params(const struct dram_para *para)\n+void h616_ddr3_set_timing_params(const struct dram_para *para)\n {\n \tstruct sunxi_mctl_ctl_reg * const mctl_ctl =\n \t\t\t(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;\ndiff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c\nindex 7efb1b22a84..23b29cc973c 100644\n--- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c\n+++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c\n@@ -28,11 +28,15 @@ static const u8 h616_lpddr3_phy_init_addr_map_1[H616_PHY_INIT_LEN] = {\n \t0x08, 0x01, 0x1a\n };\n \n-const u8 *phy_init = IS_ENABLED(CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1) ?\n-\t\t h616_lpddr3_phy_init_addr_map_1 :\n-\t\t h616_lpddr3_phy_init_default;\n+const u8 *h616_lpddr3_get_phy_init(void)\n+{\n+\tif (IS_ENABLED(CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1))\n+\t\treturn h616_lpddr3_phy_init_addr_map_1;\n+\n+\treturn h616_lpddr3_phy_init_default;\n+}\n \n-void mctl_set_timing_params(const struct dram_para *para)\n+void h616_lpddr3_set_timing_params(const struct dram_para *para)\n {\n \tstruct sunxi_mctl_ctl_reg * const mctl_ctl =\n \t\t\t(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;\ndiff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c\nindex 055d8dd3cad..c19ae025f75 100644\n--- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c\n+++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c\n@@ -26,11 +26,15 @@ static const u8 h616_lpddr4_phy_init_addr_map_1[H616_PHY_INIT_LEN] = {\n \t0x18, 0x04, 0x1a\n };\n \n-const u8 *phy_init = IS_ENABLED(CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1) ?\n-\t\t h616_lpddr4_phy_init_addr_map_1 :\n-\t\t h616_lpddr4_phy_init_default;\n+const u8 *h616_lpddr4_get_phy_init(void)\n+{\n+\tif (IS_ENABLED(CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1))\n+\t\treturn h616_lpddr4_phy_init_addr_map_1;\n+\n+\treturn h616_lpddr4_phy_init_default;\n+}\n \n-void mctl_set_timing_params(const struct dram_para *para)\n+void h616_lpddr4_set_timing_params(const struct dram_para *para)\n {\n \tstruct sunxi_mctl_ctl_reg * const mctl_ctl =\n \t\t\t(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;\n", "prefixes": [ "v4", "3/5" ] }